CN207691768U - A kind of calibration circuit of the time constant of active filter - Google Patents

Abstract

A time constant calibrating circuit of an active filter includes a capacitor array to be calibrated, an integrator generating a slope voltage, a comparator and a digital logic circuit. The utility model overcomes the problem of the change of the time constant of the active filter circuit due to the deviation of process manufacturing parameters, and can realize the automatic calibration of the time constant calibration circuit of the active filter circuit.

Description

A Calibration Circuit of Time Constant of Active Filter

technical field

The utility model relates to an active filter, in particular to a calibration circuit for the time constant of the active filter.

Background technique

Active filters are widely used in communication systems due to their good linearity, dynamic range and noise performance, and simple implementation methods. In order to meet the system's requirement for frequency accuracy within ±3%, the time constant of the filter needs to meet the accuracy requirement. In the manufacturing process of integrated circuit circuits, the deviation of the resistance value and capacitance value with the change of the manufacturing process parameters can be as high as ±20%, which leads to the drift of the time constant of the filter. Therefore, the time constant of the active filter must be adjusted. calibration.

The matching accuracy of the same type of integrated circuit devices is relatively high, for example, the matching accuracy of resistors can reach 1% or less, and the matching accuracy of capacitors can reach 0.1% or less. This feature can be used to design calibration circuits, using the same type of resistors and capacitors in active filter circuits and calibration circuits, and selecting unit resistors and unit capacitors of the same physical size during layout layout. Calibration circuits and digital filter circuits generally use switched resistors or switched capacitors to calibrate the time constant, but because the matching accuracy of capacitors is higher than that of resistors, the utility model realizes the calibration of time constants based on digital filters and switched capacitors.

There are many methods for calibrating the filter time constant, but there are generally problems of insufficient calibration accuracy and slow calibration speed.

Utility model content

The purpose of this utility model is to provide an automatic calibration circuit of the time constant of the active filter, which overcomes the change of the time constant of the active filter circuit due to the deviation of the process parameters in the manufacturing process, and prevents the The influence of the drift of the characteristic frequency of the source filter on the system has the characteristics of high calibration accuracy and fast calibration speed.

The technical scheme of the utility model is as follows:

A time constant automatic calibration circuit of an active filter, comprising a calibrated capacitor array circuit CBANK of an analog part, an integrator circuit generating a slope voltage, a comparator circuit and a logic circuit of a digital part, wherein the calibrated capacitor array circuit CBANK is composed of N optional capacitors are connected in parallel. The integrator circuit that generates the slope voltage includes a current source generation circuit, a current mirror circuit and a switch control circuit. The comparator is CMP, and the digital logic circuit generates a switch control signal S ₁ /S _1n /S _2. Discharge control signal RST, capacitor array charging cycle T, capacitor array control signal.

The calibrated capacitor array CBANK consists of N capacitors C ₁ ~C _N and N NMOS switches N ₁ ~N _N , where N is a natural number greater than 1, capacitors C ₁ and N ₁ are connected in series, capacitors C ₂ and N ₂ are connected in series, sequentially By analogy, capacitors C _N and N _N are connected in series, and the series branches formed by these capacitors and NMOS switches are then connected in parallel; the design capacitance of capacitor C ₁ is C _u , the design capacitance of capacitor C ₂ is 2C _u , and the design capacitance of capacitor C ₃ is The design capacitance is 4C _u , and so on, the design capacitance of the capacitor C _N is 2 ^N-1 C _u , the common terminal of the capacitor C ₁ ~ _CN is the input terminal of the capacitor array CBANK to be calibrated, and the NMOS switches N ₁ ~N The common end of _N is the output end of the capacitor array CBANK to be calibrated, and the gates of the NMOS switches N ₁ to N _N are controlled by the calibration capacitor array control signal C[N-1:0] of the N bits output by the digital logic circuit; The calibrated capacitor array CBANK and the resistor R of the active filter constitute the time constant of the active filter.

The integrator circuit that generates the slope voltage includes a current source generating circuit, a current mirror circuit and a switch control circuit, wherein the current source generating circuit includes an operational amplifier Opamp, a resistor REF, and an NMOS transistor M1, and the current mirror circuit includes PMOS transistors P0 and P1, and the switch control circuit The circuit includes an NMOS complementary switch M ₂ /M ₃ and a discharge NMOS switch M ₄ , the non-inverting input terminal of the operational amplifier Opamp is connected to the bandgap voltage V _REF , the inverting input terminal of the operational amplifier Opamp is connected to a resistor REF, The other end of the resistor REF is grounded, the output terminal of the operational amplifier Opamp is connected to the gate of the NMOS transistor M1, the source of the NMOS transistor M1 is connected to the inverting input terminal of the operational amplifier Opamp, and the drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor P0. The gate of the PMOS transistor P0 is connected to its own drain and the gate of the PMOS transistor P1 respectively, the sources of the PMOS transistors P0 and P1 are connected to the power supply, and the drain of the PMOS transistor P1 is connected to the common terminal of the complementary switch _M2 / _M3 . The other end of the switch _M3 is connected to the input end of the calibrated capacitor array C _BANK , the other end of the switch _M2 is grounded; the output end of the calibrated capacitor array CBANK is grounded, one end of the discharge switch _M4 is connected to the input end of the calibrated capacitor array CBANK, and the other end grounded.

The positive terminal of the comparator is connected to the bandgap voltage V _REF , the negative terminal of the comparator is connected to the input terminal of the calibrated capacitor array, and the output signal ERR of the comparator is sent to a digital logic circuit.

The optional capacitors C ₁ to C _N in the calibrated capacitor array CBANK are formed by parallel connection of unit capacitors C _u with the same layout shape and layout positions immediately adjacent to each other. When the manufacturing process deviates, the process parameters will affect the The capacitances C ₁ ~C _N have the same influence factor, which is set to β _c . If C _u represents the design value of the unit capacitance, and C' _u represents the actual unit capacitance value affected by the offset of the chip manufacturing process parameters, then C' _u ＝ _βc · _Cu

The resistor REF and the resistor R of the active filter are resistors of the same material type, and both are composed of unit resistors with the same layout shape and symmetrical layout position. When the process parameters deviate during the manufacturing process, the resistance value R of the resistor REF is designed _REF and the design resistance R _R of the active filter resistor R are equal, set as β _r , if R _REF represents the design resistance of the resistance RREF, R _R represents the design resistance of the resistance R, and R ' _REF represents the actual resistance value of the resistor RREF affected by the offset of the chip manufacturing process parameters, R' _R represents the actual resistance value of the resistor R affected by the offset of the chip manufacturing process parameters, then _R'REF = β _r · R _REF , R' _R = β _r · R _R ; and R _REF is m times R _R , m is a natural number greater than or equal to 1.

The beneficial effects of the utility model are:

The utility model overcomes the change of the time constant of the active filter circuit due to the deviation of the process parameters in the manufacturing process, prevents the drift of the characteristic frequency of the active filter from affecting the system, and has high calibration accuracy and fast calibration speed specialty.

Description of drawings

Fig. 1 is the utility model active filter time constant calibration circuit.

Fig. 2 is the capacitor array of the active filter of the utility model.

Fig. 3 is the digital logic circuit block diagram of the utility model.

Figure 4 is a block diagram of the digital filter circuit of the utility model.

Fig. 5 is a sequence diagram of a single calibration of the utility model.

Fig. 6 is a complete calibration sequence diagram of the utility model.

Fig. 7 is an example diagram of the calibration process of the utility model.

Detailed ways

In order to make the above-mentioned purposes, features and advantages of the utility model understandable, the utility model will be described in detail below in conjunction with the accompanying drawings and embodiments, but the protection scope of the utility model should not be limited thereby.

With reference to Fig. 1, Fig. 1 is the utility model active filter time constant calibration circuit. It can be seen from the figure that the active filter time constant automatic calibration circuit of the present invention includes the calibrated capacitor array circuit CBANK of the analog part, the integrator circuit for generating the slope voltage, the comparator circuit and the digital logic circuit.

The capacitor array CBANK to be calibrated adopts the form of parallel connection of optional capacitor arrays, see Fig. 2, and Fig. 2 is part of the capacitor array CBANK of the active filter of the utility model. The capacitor array CBANK consists of N capacitors C ₁ ~C _N and N NMOS switches N ₁ ~N _N , where N is a natural number greater than 1, capacitors C ₁ and N ₁ are connected in series, capacitors C ₂ and N ₂ are connected in series, and so on. Capacitors C _N and N _N are connected in series, and the series branches formed by these capacitors and NMOS switches are connected in parallel; the design capacitance C _u of the capacitance C ₁ , the design capacitance 2C _u of the capacitance C ₂ , and the design capacitance C ₃ The value is 4C _u , and so on, the design capacitance of the capacitor C _N is 2 ^N-1 C _u , the common terminal of the capacitors C ₁ ~C _N and C _fix is the input terminal of the capacitor array CBANK to be calibrated, and the NMOS switches N ₁ ~ The common terminal of N _N is the output terminal of the calibrated capacitor array CBANK, the gates of the NMOS switches N ₁ ~ _NN are connected to the output terminal C[N-1:0] of the digital logic circuit, and the N bits of the calibrated capacitor The array control signal C[N-1:0] controls; the value of N is determined according to the calibration accuracy requirements.

The integrator circuit that generates the slope voltage includes a current source generating circuit, a current mirror circuit and a switch control circuit, wherein the current source generating circuit includes an operational amplifier Opamp, a resistor REF, and an NMOS transistor M1, and the current mirror circuit includes PMOS transistors P0 and P1, and the switch control circuit The circuit includes an NMOS complementary switch M ₂ /M ₃ and a discharge NMOS switch M ₄ , the non-inverting input terminal of the operational amplifier Opamp is connected to the bandgap voltage V _REF , the inverting input terminal of the operational amplifier Opamp is connected to a resistor REF, The other end of the resistor REF is grounded, the output terminal of the operational amplifier Opamp is connected to the gate of the NMOS transistor M1, the source of the NMOS transistor M1 is connected to the inverting input terminal of the operational amplifier Opamp, and the drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor P0. The gate of the PMOS transistor P0 is connected to its own drain and the gate of the PMOS transistor P1 respectively, the sources of the PMOS transistors P0-P1 are connected to the power supply, and the drain of the PMOS transistor P1 is connected to the common terminal of the complementary switch M ₂ /M ₃ , The other end of the switch _M3 is connected to the input end of the calibrated capacitor array C _BANK , the other end of the switch _M2 is grounded; the output end of the calibrated capacitor array C _BANK is grounded, and one end of the discharge switch _M4 is connected to the input end of the calibrated capacitor array C _BANK , The other end is grounded.

The positive terminal of the comparator is connected to the bandgap voltage V _REF , the negative terminal of the comparator is connected to the input terminal of the calibrated capacitor array, and the output signal ERR of the comparator is sent to a digital logic circuit.

Referring to FIG. 3 , the digital logic circuit includes a digital filter 102 and a timing control circuit 101 . The sequence control circuit is written by digital algorithm Verilog HDL program, and the specific circuit is synthesized according to related software, which generates periodic switch control signals S ₁ , S _1n , S ₂ , discharge control signal RST and capacitor array charging cycle T.

With reference to shown in Figure 4, described digital filter 101 comprises flip-flop 201, integrator 202, gain module 203, IIR filter 204, gain module 05, gain module 211, gain module 221, differentiator 212 and adder 206 , wherein the flip-flop 201 and the integrator 202 are connected in sequence, the flip-flop 201 samples the error signal Err output by the comparator CMP under the action of the clock CLK and sends the output to the integrator 202, and the output of the integrator 202 is sent to the gain module 203 The sum gain module 211 and the gain module 221, the gain module 203, the IIR filter 204 and the gain module 205 are connected to the adder 206 in turn, the gain module 211 and the differentiator 212 are connected to the adder 206 in sequence, and the gain module 221 is connected to the adder 206. The adder 206 outputs an N-bit control word C[N-1:0], and the N-bit control word C[N-1:0] is sequentially output to the capacitor array CBANK to be calibrated.

The resistor REF and the resistor R of the active filter are resistors of the same process material type, and both are composed of unit resistors with the same layout shape and symmetrical layout position. When the process parameters deviate from the manufacturing process, the resistance REF The design resistance R _REF and the design resistance R _R influence factor of the active filter resistor R are equal, set to β _r , if R _REF represents the design resistance of the resistance R REF, and R _R represents the design resistance of the resistance R Resistance value, R' _REF represents the resistance value of the resistor REF affected by the deviation of the process manufacturing parameters, R' _R represents the actual resistance of the resistor R after being affected by the deviation of the chip manufacturing process parameters after being affected by the deviation of the process manufacturing parameters value, then R' _REF =β _r ·R _REF , R' _R =β _r · _RR , and R _REF is m times R _R , where m is a natural number greater than or equal to 1.

2 is the capacitor array CBANK to be calibrated. The capacitors C ₁ to C _N are formed by parallel connection of unit capacitors C _u with the same layout shape and layout positions immediately adjacent to each other. The above-mentioned capacitors C ₁ to C _N have equal influence factors, which are set to β _c . If C _u represents the design capacitance value of the unit capacitor, and C' _u represents the capacitance value of the unit capacitor after being affected by the deviation of the process manufacturing parameters, then C ' _u ＝β _c ·C _u

By controlling the switch of the capacitor array, the number of unit capacitors of the capacitor array is increased or decreased, thereby adjusting the capacitance value of CBANK.

The expression of the design capacitance of the calibrated active filter capacitor array CBANK is:

C[i] in the above expression is a certain bit of C[N-1:0] output by the digital logic circuit.

It can be seen from the above that the active filter capacitor array CBANK can be formed by connecting 2 ^N unit capacitors in parallel at most, and taking N=8 as a class, it means that the capacitor array CBANK contains at most 255 unit capacitors;

If the design capacitance of CBANK is C _BANK =2 ⁷ ·C _u +2 ⁵ ·C _u +2 ⁴ ·C _u +2 ² ·C _u ＝180·C _u , since the maximum number of capacitors in the capacitor array is 255, therefore CBANK adjustable range: 108Cu～252Cu expressed in percentage ζ Adjustable range of CBANK capacitance: 60%≤ζ≤140%, since the minimum resolution of the digital logic circuit output control word C[N-1:0] is 1, so the calibration Accuracy η higher than

The working process of automatic calibration is as follows:

1. Connect the main circuit of the active filter to the input terminal of the calibration capacitor array CBANK through the drain, source and resistor R of the fifth NMOS transistor, the grid of the fifth NMOS transistor and the digital logic The signal output terminal of circuit _S2 is connected,

2. During the calibration process, see Figure 5, when the _S2 signal output by the digital logic circuit is at a low level, the calibrated capacitor array CBANK is separated from the main circuit of the active filter;

When S ₁ appears the first high-level pulse, the mirror current I charges the calibrated capacitor array CBANK for the first time with a constant current, and after the charging time T is over, S ₁ changes from high level to low level , the first charge is terminated, at this time the voltage across the calibrated capacitor array CBANK is:

Wherein, C' _BANK represents the capacitance value of the capacitor array CBANK before calibration;

_R'REF represents the resistance value of the resistor REF affected by the manufacturing parameter deviation:

R' _REF ＝ R _REF ·β _r

R' _R represents the resistance value of the resistor R after being affected by the deviation of the process manufacturing parameters:

R' _R ＝β _r R _R

The comparator CMP compares V _o with V _REF and keeps the comparison result E _RR , and the digital logic circuit performs single sampling and operation processing on E _RR to update the capacitance array gate signal C[N- 1:0], and feed it back to the control switch of the calibrated capacitor array, modify the capacitance value of the calibrated capacitor array CBANK, and complete the first calibration,

When the discharge control signal RST is at a high level, the calibrated capacitor array CBANK is completely discharged, and automatically enters the second calibration process, which is exactly the same as the first calibration process; and so on, the third and fourth times , ..., the Mth calibration, the error between V _o and V _REF is gradually reduced after each calibration.

Referring to the timing sequence in Figure 6, the entire calibration process consists of several consecutive single calibrations. Assume that after M calibrations, V ₀ can be close to V _REF . After that, the digital filter no longer adjusts the capacitance gating signal of the capacitor array CBANK, and the system Stability is reached, and the capacitor array gating signal C[N-1:0] sent by the digital filter is the final stable value, and C[N-1:0] is sent to the gating of the capacitor array CBANK of the active filter switch to obtain the final capacitance C _CBANK after calibration, at the end of charging, V _o ≈ V _REF , according to

It can be seen that:

τ represents the time constant of the active filter; therefore, the ratio m of the charging time T, R _REF and _RR can represent the time constant of the active filter; after the calibration, the time constant of the active filter is always And has nothing to do with the process manufacturing parameters. After the calibration, the digital logic circuit outputs the S ₂ high-level control signal, connects CBANK to the main circuit of the active filter, and completes the automatic calibration process. The number of times of calibration M is related to parameters such as the loop bandwidth of the digital filter, and can be obtained by a system simulation tool, M=64 in the utility model;

Single charging time T=k T _CLK (k is the number of clock cycles occupied by single charging time T, T _CLK is the cycle of the clock signal CLK), according to the time constant requirements of the active filter, it is convenient to design the corresponding T.

CLK frequency is 200KHz among the utility model, k=10, and calibration time is then:

M·k·T _CLK ＝64×10×5us＝3.2ms

The above formula further shows that after automatic calibration, the time constant of the active filter is determined by the constants m, k, and T _CLK , and has nothing to do with the manufacturing parameters of the process.

As shown in Figure 7, the system calibration process when the filter time constant caused by process deviation and the design deviation is +22.2%. As shown in Figure 7, the number of unit capacitors contained in the capacitor array after automatic calibration is 140. At this time The calibration range is 180-140/180=22.2%, and the calibration time is 3.2ms.

Although the preferred embodiments of the present invention have been disclosed above, they are not intended to limit the present invention. Any person skilled in the art who makes some simple deductions or replacements without departing from the spirit and scope of the present invention should be regarded as For belonging to the scope of protection of the present utility model.

Claims (4)

1. a kind of calibration circuit of the time constant of active filter, it is characterised in that：It is calibrated electricity including active filter Integrator circuit, comparator circuit and the Digital Logical Circuits held array circuit (CBANK), generate ramp voltage,

The capacitor array circuit (CBANK) that is calibrated includes N number of capacitance (C₁~C_N) and N number of NMOS switch (N₁~N_N), N is Natural number more than 1, the 1st capacitance (C₁) and 1NMOS switches (N₁) series connection, the 2nd capacitance (C₂) and 2NMOS switches (N₂) string Connection ..., N capacitances (C_N) and NNMOS switches (N_N) series connection, the series arm that N number of capacitance and N number of NMOS switch are formed is again simultaneously Connection；1st capacitance (the C₁) design capacitance be C_u, the 2nd capacitance (C₂) design capacitance be 2C_u, the 3rd capacitance (C₃) design Capacitance is 4C_u..., N capacitances (C_N) design capacitance be 2^N-1C_u, all capacitance (C₁~C_N) common end be calibrated capacitance The input terminal of array (CBANK), N number of NMOS switch (N₁~N_N) common end be the output for being calibrated capacitor array (CBANK) End, N number of NMOS switch (N₁~N_N) grid and the Digital Logical Circuits control signal C [N-1:0] output end phase Even；It is described to be calibrated resistance (R) composition active filter time constant of the capacitor array (CBANK) with active filter；

The integrator circuit of the generation ramp voltage includes electric current source generating circuit, current mirror circuit and switch control electricity Road, the electric current source generating circuit include operational amplifier (Opamp), resistance (REF) and the first NMOS tube (M1), described Current mirror circuit includes two PMOS tube (P0, P1), and the ON-OFF control circuit includes by the second NMOS tube (M₂), third NMOS tube (M₃) drain electrode be connected and constitute complementary switch and the 4th NMOS tube (M₄) constitute discharge switch；The operation amplifier The normal phase input end of device (Opamp) meets a reference voltage (V_REF), one end of anti-phase input terminating resistor (REF), the resistance (REF) other end ground connection, the output of operational amplifier (Opamp) terminate the grid of the first NMOS tube (M1), the first NMOS tube (M1) source electrode connects the inverting input of operational amplifier (Opamp), and the drain electrode of the first NMOS tube (M1) connects the first PMOS tube (P0) grid of drain electrode, the first PMOS tube (P0) is connect with the grid of the drain electrode of itself and the second PMOS tube (P1) respectively, The source electrode of first PMOS tube (P0) and the second PMOS tube (P1) connects power supply (VDD), second PMOS tube (P1) Drain electrode meets the second NMOS tube (M of complementary switch₂) and third NMOS tube (M₃) drain electrode common end, the second NMOS tube (M₂) source Pole is grounded, third NMOS tube (M₃) source electrode connect the input terminal for being calibrated capacitor array (CBANK), described is calibrated capacitance battle array Arrange the output end ground connection of (CBANK), the 4th NMOS tube (M₄) drain electrode connect the input for being calibrated capacitor array (CBANK) End, the 4th NMOS tube (M₄) source electrode ground connection；

Reference voltage (V described in the positive termination of the comparator (CMP)_REF), the negative of comparator (CMP) is terminated by school The input terminal of pseudo-capacitance array (CBANK), the output end and the error signal of the Digital Logical Circuits of comparator (CMP) are defeated Enter end (E_RR) be connected；

The Digital Logical Circuits includes digital filter (102) and sequential control circuit (101), the digital filter (102) signal input part connects the output end of the comparator (CMP), the positions N of the output end output of digital filter (102) Control word C [N-1:0] N number of NMOS tube (N of the calibration circuit capacitance array (CBANK) is met successively respectively₁~N_N) grid, The control signal that the sequential control circuit (101) generates includes S1, S1n, S2, S3, RST and T, S1n control letters Number, S1 control signals and RST control signals be respectively applied to the second NMOS tube (M₂) grid, third NMOS tube (M₃) Grid and the 4th NMOS tube (M₃) grid, S2 be active filter be calibrated capacitor array (CBANK) and active filter The control signal of main body circuit separation, T are capacitor array charge cycle, and CLK is consequently exerted at the timing control of Digital Logical Circuits Signal.

2. the calibration circuit of the time constant of active filter according to claim 1, it is characterised in that：The benchmark Voltage is the good band gap voltage of temperature characterisitic, and the voltage value of the reference voltage is 1.25v.

3. the calibration circuit of the time constant of active filter according to claim 1, it is characterised in that：It is described by school Capacitance (C1~C in pseudo-capacitance array (CBANK)_N) by identical layout shape, the tight adjacent specific capacitance C in laying out pattern position_u It is formed in parallel, technological parameter is when deviation occurs for manufacturing process to the capacitance (C1~C_N) capacitance impact factor is equal, it is set as β_cIf C_uIndicate that specific capacitance designs capacitance, C'_uIndicate the effective unit capacitance after being influenced by chip manufacturing process parameter shift It is worth, then C'_u=β_c·C_u。

4. the calibration circuit of the time constant of active filter according to claim 1, it is characterised in that：The resistance R_REFResistance R with active filter is the resistance of same process material type, and by identical layout shape, domain position pair The unit resistance of title is constituted, and technological parameter is when deviation occurs for manufacturing process, to resistance REF resistances and the active power filtering The resistance value impact factor of device resistance R is equal, is set as β_rIf R_REFIndicate the resistance R_REFDesign resistance value, R_RIndicate the resistance R Design resistance value, R'_REFIndicate the resistance R_REFActual resistance, R' after being influenced by chip manufacturing process parameter shift_RIndicate institute Actual resistance after stating resistance R and being influenced by chip manufacturing process parameter shift, then R'_REF=β_r·R_RE、R'_R=β_r·R_R, and R_REF For m times of R_R, wherein m is the natural number more than or equal to 1.