CN207691768U - A kind of calibration circuit of the time constant of active filter - Google Patents
A kind of calibration circuit of the time constant of active filter Download PDFInfo
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Abstract
A kind of time constant calibration circuit of active filter, including it is calibrated integrator, comparator and the Digital Logical Circuits of capacitor array, generation ramp voltage.The utility model overcome active filter circuit due to manufacturing parameter deviation and caused by time constant variation the problem of, can realize the automatic calibration that circuit is calibrated to active filter circuit time constant.
Description
Technical field
The utility model is related to active filter, especially a kind of calibration circuit of the time constant of active filter.
Background technology
For active filter due to having the preferable linearity, dynamic range and noiseproof feature, implementation method is simple, widely transports
For communication system.To meet system to the requirement in frequency accuracy ± 3%, filter time constant is needed to meet precision
It is required that.In integrated circuit manufacturing process, deviation that resistance value and capacitance occur with the variation of fabrication process parameters
Up to ± 20%, so as to cause the drift of filter time constant, it is therefore necessary to the time constant of active filter into
Row calibration.
The matching of integrated circuit same type device is accurately higher, if the matching precision of resistance is up to 1% or smaller, electricity
The matching precision of appearance can reach 0.1% or smaller.Calibration circuit can be designed using this feature, in active filter electricity
The resistance and capacitance of same type are used in road, calibration circuit, and the unit electricity of same physical size is chosen when laying out pattern
Resistance and specific capacitance.Calibration circuit and digital filter circuit generally realize prover time using switch resistance or switching capacity
Constant, but since the matching precision of capacitance is higher than resistance, so the utility model is based on digital filter and switching capacity is realized
The calibration of time constant.
There are many filter time constant calibration method, but the problem that generally existing calibration accuracy is inadequate, calibration speed is partially slow.
Utility model content
The purpose of this utility model is to provide a kind of auto-calibration circuits of the time constant of active filter, the automatic school
Quasi- circuit overcome active filter circuit due to technological parameter when deviation occurs for manufacturing process and caused by time constant
Variation, the influence for preventing the drift of the characteristic frequency of active filter from being generated to system have calibration accuracy height, calibration speed fast
The characteristics of.
The technical solution of the utility model is as follows：
A kind of time constant auto-calibration circuits of active filter, including analog portion are calibrated capacitor array circuit
The logic circuit of CBANK, the integrator circuit for generating ramp voltage, comparator circuit and numerical portion, wherein being calibrated capacitance
Array circuit CBANK is formed in parallel by N number of optional capacitance, and the integrator circuit for generating ramp voltage includes that current source generates electricity
Road, current mirror circuit and ON-OFF control circuit, comparator CMP, Digital Logical Circuits generate switch control signal S1/S1n/
S2, discharge control signal RST, capacitor array charge cycle T, capacitor array control signal.
It includes N number of capacitance C to be calibrated capacitor array CBANK1~CNAnd N number of NMOS switch N1~NNIt constitutes, N is more than 1
Natural number, capacitance C1And N1Series connection, capacitance C2And N2Series connection, and so on, capacitance CNAnd NNSeries connection, these capacitances and NMOS are opened
It is in parallel again to close the series arm formed；The capacitance C1Design capacitance Cu, capacitance C2Design capacitance 2Cu, capacitance C3Set
Count capacitance 4Cu, and so on, capacitance CNDesign capacitance 2N-1Cu, the capacitance C1~CNCommon end be calibrated capacitor array
The input terminal of CBANK, NMOS switch N1~NNCommon end be the output end for being calibrated capacitor array CBANK, NMOS switch N1~
NNThe positions N that are exported by Digital Logical Circuits of grid be calibrated capacitor array control signal C [N-1:0] it controls；It is described to be calibrated
The resistance R of capacitor array CBANK and active filter constitutes active filter time constant.
The integrator circuit for generating ramp voltage includes electric current source generating circuit, current mirror circuit and switch control electricity
Road, wherein electric current source generating circuit include operational amplifier Opamp, resistance REF, NMOS tube M1, and current mirror circuit includes
PMOS tube P0, P1, ON-OFF control circuit include NMOS complementary switch M2/M3With electric discharge NMOS switch M4, the operational amplifier
The normal phase input end of Opamp meets band gap voltage VREF, the anti-phase input terminating resistor REF of the operational amplifier Opamp, electricity
REF other ends ground connection, the grid of the output termination NMOS tube M1 of operational amplifier Opamp are hindered, the source electrode of NMOS tube M1 connects operation
The inverting input of amplifier Opamp, the drain electrode of NMOS tube M1 connect the drain electrode of PMOS tube P0, the grid of PMOS tube P0 respectively with from
The drain electrode of body and the grid connection of PMOS tube P1, the source electrode of PMOS tube P0, P1 connect power supply, and the drain electrode of PMOS tube P1 connects complementation and opens
Close M2/M3Common end, switch M3Another termination is calibrated capacitor array CBANKInput terminal, switch M2The other end is grounded；By school
Pseudo-capacitance array CBANK output ends are grounded, discharge switch M4A termination be calibrated the input terminal of capacitor array CBANK, it is another
End ground connection.
The positive terminal strip gap voltage V of the comparatorREF, the negative of comparator, which terminates, is calibrated the defeated of capacitor array
Enter end, the output signal ERR of comparator is sent into Digital Logical Circuits.
The optional capacitance C being calibrated in capacitor array CBANK1~CNBy identical layout shape, laying out pattern position
Set tight adjacent specific capacitance CuIt is formed in parallel, technological parameter is when deviation occurs for manufacturing process to the capacitance C1~CNHold
It is equal to be worth impact factor, is set as βcIf CuIndicate specific capacitance design value, C'uExpression is influenced by chip manufacturing process parameter shift
Effective unit capacitance afterwards, then C'u=βc·Cu
The resistance R of resistance REF and active filter is the resistance of identical material type, and by identical layout shape, version
The unit resistance of figure positional symmetry is constituted, and technological parameter designs resistance value when deviation occurs for manufacturing process to the resistance REF
RREFWith the design resistance value R of the active filter resistance RRImpact factor is equal, is set as βrIf RREFIndicate the resistance
RREF designs resistance value, RRIndicate the resistance R designs resistance value, R'REFIndicate that the resistance RREF is inclined by chip manufacturing process parameter
Move actual resistance, R' after influencingRIndicate the actual resistance after the resistance R is influenced by chip manufacturing process parameter shift, then
R'REF=βr·RREF、R'R=βr·RR；And RREFFor m times of RR, m is the natural number more than or equal to 1.
The beneficial effects of the utility model are：
The utility model overcomes active filter circuit since technological parameter is caused when deviation occurs for manufacturing process
Time constant variation, the influence for preventing the drift of the characteristic frequency of active filter from being generated to system, have calibration accuracy
Feature high, calibration speed is fast.
Description of the drawings
Fig. 1 is the utility model active filter time constant calibration circuit.
Fig. 2 the utility model active filter capacitor arrays.
The Digital Logical Circuits block diagram of Fig. 3 the utility model.
The digital filter circuit block diagram of Fig. 4 the utility model.
The individual calibration sequence diagram of Fig. 5 the utility model.
The integral calibration sequence diagram of Fig. 6 the utility model.
The calibration process exemplary plot of Fig. 7 the utility model.
Specific implementation mode
For the above objects, features, and advantages of the utility model can be become apparent, below in conjunction with drawings and examples pair
The utility model elaborates, but should not limit the scope of protection of the utility model with this.
With reference to figure 1, Fig. 1 is the utility model active filter time constant calibration circuit.As seen from the figure, the utility model
Active filter time constant auto-calibration circuits, including analog portion be calibrated capacitor array circuit CBANK, generate slope
Integrator circuit, comparator circuit and the Digital Logical Circuits of voltage.
It is calibrated the form that capacitor array CBANK uses the parallel connection of optional capacitor array, referring to Fig. 2, Fig. 2 the utility model has
The parts source filter capacitor array CBANK.Capacitor array CBANK includes N number of capacitance C1~CNAnd N number of NMOS switch N1~NN
It constitutes, N is the natural number more than 1, capacitance C1And N1Series connection, capacitance C2And N2Series connection, and so on, capacitance CNAnd NNSeries connection, this
The series arm that a little capacitances and NMOS switch are formed is in parallel again；The capacitance C1Design capacitance Cu, capacitance C2Design capacitance
2Cu, capacitance C3Design capacitance 4Cu, and so on, capacitance CNDesign capacitance 2N-1Cu, the capacitance C1~CNAnd CfixPublic affairs
End is the input terminal for being calibrated capacitor array CBANK, NMOS switch N altogether1~NNCommon end be calibrated capacitor array CBANK
Output end, NMOS switch N1~NNGrid and the Digital Logical Circuits output end C [N-1:0] be connected, the positions N by school
Pseudo-capacitance array control signal C [N-1:0] it controls；The value of N is determined according to calibration accuracy requirement.
The integrator circuit for generating ramp voltage includes electric current source generating circuit, current mirror circuit and switch control electricity
Road, wherein electric current source generating circuit include operational amplifier Opamp, resistance REF, NMOS tube M1, and current mirror circuit includes
PMOS tube P0, P1, ON-OFF control circuit include NMOS complementary switch M2/M3With electric discharge NMOS switch M4, the operational amplifier
The normal phase input end of Opamp meets band gap voltage VREF, the anti-phase input terminating resistor REF of the operational amplifier Opamp, electricity
REF other ends ground connection, the grid of the output termination NMOS tube M1 of operational amplifier Opamp are hindered, the source electrode of NMOS tube M1 connects operation
The inverting input of amplifier Opamp, the drain electrode of NMOS tube M1 connect the drain electrode of PMOS tube P0, the grid of PMOS tube P0 respectively with from
The drain electrode of body and the grid connection of PMOS tube P1, the source electrode of PMOS tube P0-P1 connect power supply, and the drain electrode of PMOS tube P1 connects complementation and opens
Close M2/M3Common end, switch M3Another termination is calibrated capacitor array CBANKInput terminal, switch M2The other end is grounded；By school
Pseudo-capacitance array CBANKOutput end is grounded, discharge switch M4A termination be calibrated capacitor array CBANKInput terminal, another termination
Ground.
The positive terminal strip gap voltage V of the comparatorREF, the negative of comparator, which terminates, is calibrated the defeated of capacitor array
Enter end, the output signal ERR of comparator is sent into Digital Logical Circuits.
Refering to what is shown in Fig. 3, Digital Logical Circuits includes digital filter 102 and sequential control circuit 101.The sequential
Control circuit writes Verilog HDL programs by digital algorithm, and is integrated according to related software to obtain physical circuit, is generated by it
Periodic switch control signal S1、S1n、S2, discharge control signal RST and capacitor array charge cycle T.
Refering to what is shown in Fig. 4, the digital filter 101 include trigger 201, integrator 202, gain module 203,
Iir filter 204, gain module 05, gain module 211, gain module 221, differentiator 212 and adder 206, wherein triggering
Device 201 and integrator 202 are sequentially connected, and trigger 201 samples the error of the output of comparator CMP under the action of clock CLK
Signal Err simultaneously gives output to integrator 202, the output of integrator 202 send to gain module 203 and gain module 211 and
Gain module 221, gain module 203, iir filter 204 and gain module 205 are consecutively connected to adder 206, gain module
211 and differentiator 212 be sequentially connected to adder 206, gain module 221 is connected to adder 206, the adder 206 export N
Position control word C [N-1:0], the N control word C [N-1:0] it is sequentially output and is calibrated capacitor array CBANK's.
The resistance R of the resistance REF and active filter is the resistance of same process material type, and by identical version
Diagram shape, the unit resistance composition of domain positional symmetry, technological parameter is when deviation occurs for manufacturing process to the resistance REF
Design resistance value RREFWith the design resistance value R of the active filter resistance RRImpact factor is equal, is set as βrIf RREFIndicate institute
State resistance RREF designs resistance value, RRIndicate the resistance R designs resistance value, R'REFIt indicates after by manufacturing parameter deviation effects
The resistance value of the resistance REF, R'RIndicate that the resistance R is by chip manufacturing process parameter after by manufacturing parameter deviation effects
Actual resistance after bias effect, then R'REF=βr·RREF、R'R=βr·RR, and RREFFor m times of RR, wherein m be more than or equal to
1 natural number.
Described Fig. 2 is to be calibrated capacitor array CBANK, the capacitance C1~CNBy identical layout shape, laying out pattern position
Set tight adjacent specific capacitance CuIt is formed in parallel, technological parameter is when deviation occurs for manufacturing process to the capacitance C1~CNHold
It is equal to be worth impact factor, is set as βcIf CuIndicate that specific capacitance designs capacitance, C'uIt indicates after by manufacturing parameter deviation effects
The capacitance of the specific capacitance, then C'u=βc·Cu
By controlling the switch of capacitor array, the specific capacitance quantity of capacitor array is increased or decreased, so as to adjust CBANK
Capacitance.
The expression formula for the active filter capacitor array CBANK design capacitance being calibrated is：
C [i] in above-mentioned expression formula is the C [N-1 that the Digital Logical Circuits exports:0] a certain position.
From the foregoing, it will be observed that active filter capacitor array CBANK at most can be by 2NA specific capacitance is formed in parallel, and is with N=8
Class, then it represents that capacitor array CBANK contains up to 255 specific capacitances；
If the design capacitance of CBANK is CBANK=27·Cu+25·Cu+24·Cu+22·Cu=180Cu, because of capacitor array
Maximum capacitor quantity be 255, therefore CBANK adjustable ranges：108Cu~252Cu indicates that CBANK capacitances can with percentage ζ
Adjusting range：60%≤ζ≤140%, due to Digital Logical Circuits output control word C [N-1:0] minimum resolution is 1, therefore
Calibration accuracy η is higher than
Automatic calibration process is as follows：
1, drain electrode of the active filter main body circuit through the 5th NMOS tube, source electrode, resistance R are connect to the calibration capacitance battle array
Arrange the input terminal of CBANK, the 5th NMOS tube grid and the Digital Logical Circuits S2Signal output end is connected,
2, in calibration process, referring to Fig. 5, as the S of Digital Logical Circuits output2When signal is low level, it is calibrated capacitance
Array CBANK is detached with active filter main body circuit；
Work as S1When there is first time high level pulse, the image current I carries out first to being calibrated capacitor array CBANK
Secondary constant-current charge, after charging time T, S1Low level is become from high level, first time charging termination, the quilt at this time
The both end voltage of calibration capacitance array CBANK is：
Wherein, C'BANKIndicate the capacitor array CBANK capacitances before calibration；
R'REFIndicate the resistance value of the resistance REF after by manufacturing parameter deviation effects：
R'REF=RREF·βr
R'RIndicate the resistance value of resistance R described after by manufacturing parameter deviation effects：
R'R=βr·RR
The comparator CMP is by VoWith VREFIt is compared and by comparison result ERRIt keeps, Digital Logic electricity
Road is to ERRCarry out unitary sampling union processing, update capacitor array gating signal C [N-1:0] value, and be fed back to by
The control of calibration capacitance array switchs, and modification is calibrated the capacitance of capacitor array CBANK, completes to calibrate for the first time,
It when discharge control signal RST is high level, is calibrated capacitor array CBANK and is completely discharged, automatically into the
Secondary calibration process, second of calibration process and first time are just the same；And so on, carry out third time, the 4th time ..., M
Secondary calibration, V after calibrating every timeoWith VREFError be gradually reduced.
With reference to Fig. 6 sequential, entire calibration process is made of several continuous individual calibrations, it is assumed that, can be real after M calibration
Existing V0Approach VREF, hereafter, digital filter no longer adjusts the capacitance gating signal of capacitor array CBANK, and system reaches steady
It is fixed, and the capacitor array gating signal C [N-1 that digital filter is sent out:0] it is final stationary value, C [N-1:0] it has been sent to
The gating switch of the capacitor array CBANK of source filter to be calibrated after final capacitance CCBANK, at the end of charging, Vo
≈VREF, according to
Known to：
τ indicates active filter time constant；Therefore charging time T, RREFWith RRRatio m can characterize active filter
Time constant；After calibration, the time constant of active filter is alwaysAnd it is unrelated with manufacturing parameter.Calibration knot
Digital Logical Circuits exports S after beam2CBANK is linked into active filter main body circuit by high-level control signal, is completed certainly
Dynamic calibration process.It is related to calibrate the parameters such as number M and the loop bandwidth of the digital filter, and can be obtained by system emulation tool
, M=64 in the utility model；
Single charge time T=kTCLK(k is clock periodicity shared by single charge time T, TCLKFor clock signal clk
Period), according to the time constant of active filter require, can conveniently design corresponding T.
CLK frequency is 200KHz, k=10 in the utility model, and prover time is then：
M·k·TCLK=64 × 10 × 5us=3.2ms
Formula further demonstrates that above：After calibrating automatically, the time constant of active filter is by constant m, k, TCLKCertainly
It is fixed, and it is unrelated with manufacturing parameter.
Shown in Fig. 7, system calibration when filter time constant and design deviation caused by process deviation are+22.2%
Process is as shown in Figure 7, and specific capacitance quantity contained by the capacitor array after calibrating automatically is 140, and calibration range at this time is
180-140/180=22.2%, prover time 3.2ms.
Although the utility model preferred embodiment discloses as above, so it is not intended to limit the utility model, Ren Heben
Field technology personnel without departing from the spirit and scope of the utility model, make several simple deduction or replace, should regard
To belong to the scope of protection of the utility model.
Claims (4)
1. a kind of calibration circuit of the time constant of active filter, it is characterised in that：It is calibrated electricity including active filter
Integrator circuit, comparator circuit and the Digital Logical Circuits held array circuit (CBANK), generate ramp voltage,
The capacitor array circuit (CBANK) that is calibrated includes N number of capacitance (C1~CN) and N number of NMOS switch (N1~NN), N is
Natural number more than 1, the 1st capacitance (C1) and 1NMOS switches (N1) series connection, the 2nd capacitance (C2) and 2NMOS switches (N2) string
Connection ..., N capacitances (CN) and NNMOS switches (NN) series connection, the series arm that N number of capacitance and N number of NMOS switch are formed is again simultaneously
Connection；1st capacitance (the C1) design capacitance be Cu, the 2nd capacitance (C2) design capacitance be 2Cu, the 3rd capacitance (C3) design
Capacitance is 4Cu..., N capacitances (CN) design capacitance be 2N-1Cu, all capacitance (C1~CN) common end be calibrated capacitance
The input terminal of array (CBANK), N number of NMOS switch (N1~NN) common end be the output for being calibrated capacitor array (CBANK)
End, N number of NMOS switch (N1~NN) grid and the Digital Logical Circuits control signal C [N-1:0] output end phase
Even；It is described to be calibrated resistance (R) composition active filter time constant of the capacitor array (CBANK) with active filter；
The integrator circuit of the generation ramp voltage includes electric current source generating circuit, current mirror circuit and switch control electricity
Road, the electric current source generating circuit include operational amplifier (Opamp), resistance (REF) and the first NMOS tube (M1), described
Current mirror circuit includes two PMOS tube (P0, P1), and the ON-OFF control circuit includes by the second NMOS tube (M2), third
NMOS tube (M3) drain electrode be connected and constitute complementary switch and the 4th NMOS tube (M4) constitute discharge switch；The operation amplifier
The normal phase input end of device (Opamp) meets a reference voltage (VREF), one end of anti-phase input terminating resistor (REF), the resistance
(REF) other end ground connection, the output of operational amplifier (Opamp) terminate the grid of the first NMOS tube (M1), the first NMOS tube
(M1) source electrode connects the inverting input of operational amplifier (Opamp), and the drain electrode of the first NMOS tube (M1) connects the first PMOS tube
(P0) grid of drain electrode, the first PMOS tube (P0) is connect with the grid of the drain electrode of itself and the second PMOS tube (P1) respectively,
The source electrode of first PMOS tube (P0) and the second PMOS tube (P1) connects power supply (VDD), second PMOS tube (P1)
Drain electrode meets the second NMOS tube (M of complementary switch2) and third NMOS tube (M3) drain electrode common end, the second NMOS tube (M2) source
Pole is grounded, third NMOS tube (M3) source electrode connect the input terminal for being calibrated capacitor array (CBANK), described is calibrated capacitance battle array
Arrange the output end ground connection of (CBANK), the 4th NMOS tube (M4) drain electrode connect the input for being calibrated capacitor array (CBANK)
End, the 4th NMOS tube (M4) source electrode ground connection；
Reference voltage (V described in the positive termination of the comparator (CMP)REF), the negative of comparator (CMP) is terminated by school
The input terminal of pseudo-capacitance array (CBANK), the output end and the error signal of the Digital Logical Circuits of comparator (CMP) are defeated
Enter end (ERR) be connected；
The Digital Logical Circuits includes digital filter (102) and sequential control circuit (101), the digital filter
(102) signal input part connects the output end of the comparator (CMP), the positions N of the output end output of digital filter (102)
Control word C [N-1:0] N number of NMOS tube (N of the calibration circuit capacitance array (CBANK) is met successively respectively1~NN) grid,
The control signal that the sequential control circuit (101) generates includes S1, S1n, S2, S3, RST and T, S1n control letters
Number, S1 control signals and RST control signals be respectively applied to the second NMOS tube (M2) grid, third NMOS tube (M3)
Grid and the 4th NMOS tube (M3) grid, S2 be active filter be calibrated capacitor array (CBANK) and active filter
The control signal of main body circuit separation, T are capacitor array charge cycle, and CLK is consequently exerted at the timing control of Digital Logical Circuits
Signal.
2. the calibration circuit of the time constant of active filter according to claim 1, it is characterised in that：The benchmark
Voltage is the good band gap voltage of temperature characterisitic, and the voltage value of the reference voltage is 1.25v.
3. the calibration circuit of the time constant of active filter according to claim 1, it is characterised in that：It is described by school
Capacitance (C1~C in pseudo-capacitance array (CBANK)N) by identical layout shape, the tight adjacent specific capacitance C in laying out pattern positionu
It is formed in parallel, technological parameter is when deviation occurs for manufacturing process to the capacitance (C1~CN) capacitance impact factor is equal, it is set as
βcIf CuIndicate that specific capacitance designs capacitance, C'uIndicate the effective unit capacitance after being influenced by chip manufacturing process parameter shift
It is worth, then C'u=βc·Cu。
4. the calibration circuit of the time constant of active filter according to claim 1, it is characterised in that：The resistance
RREFResistance R with active filter is the resistance of same process material type, and by identical layout shape, domain position pair
The unit resistance of title is constituted, and technological parameter is when deviation occurs for manufacturing process, to resistance REF resistances and the active power filtering
The resistance value impact factor of device resistance R is equal, is set as βrIf RREFIndicate the resistance RREFDesign resistance value, RRIndicate the resistance R
Design resistance value, R'REFIndicate the resistance RREFActual resistance, R' after being influenced by chip manufacturing process parameter shiftRIndicate institute
Actual resistance after stating resistance R and being influenced by chip manufacturing process parameter shift, then R'REF=βr·RRE、R'R=βr·RR, and RREF
For m times of RR, wherein m is the natural number more than or equal to 1.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108111146A (en) * | 2018-01-30 | 2018-06-01 | 上海航天芯锐电子科技有限公司 | The auto-calibration circuits of the time constant of active filter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108111146A (en) * | 2018-01-30 | 2018-06-01 | 上海航天芯锐电子科技有限公司 | The auto-calibration circuits of the time constant of active filter |
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