CN207651513U - A kind of high brightness LED chip - Google Patents

A kind of high brightness LED chip Download PDF

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Publication number
CN207651513U
CN207651513U CN201721790544.8U CN201721790544U CN207651513U CN 207651513 U CN207651513 U CN 207651513U CN 201721790544 U CN201721790544 U CN 201721790544U CN 207651513 U CN207651513 U CN 207651513U
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layer
led chip
exposed region
thickness
electrode
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艾国齐
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Foshan Nationstar Semiconductor Co Ltd
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Foshan Nationstar Semiconductor Co Ltd
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Abstract

The utility model discloses a kind of high brightness LED chips, including substrate, epitaxial layer, the first exposed region, ITO layer, first electrode, second electrode and insulating layer, wherein the thickness setting of the ITO layer existsIn the range of, by reducing the thickness of ITO layer, to prevent the side wall excessive corrosion of chip, destroy the overall structure of LED chip, and then the light extraction efficiency of LED chip is improved, reduce the production time, improve production efficiency.

Description

A kind of high brightness LED chip
Technical field
The utility model is related to LED technology field more particularly to a kind of high brightness LED chips.
Background technology
LED (Light Emitting Diode, light emitting diode) be it is a kind of using Carrier recombination when release energy shape At luminous semiconductor devices, LED chip is with power consumption is low, coloration is pure, long lifespan, small, the response time is fast, energy conservation and environmental protection Equal many advantages.Wherein, the performance of LED chip directly affects the performance of entire LED light, the production method and material of LED chip Play the role of the performance of chip to pass.
Currently, the material of the ITO layer of LED chip is generally ITO (Indium Tin Oxides, indium tin oxide), ITO Current thickness is generallyWherein mainly it is performed etching using chemical corrosion method, still, using wet chemical The problems such as rotten method be easy to cause excessive corrosion influences the photoelectric properties of LED chip.
Invention content
Technical problem to be solved by the utility model is to provide a kind of high brightness LDE chips, by reducing ITO layer Thickness, to prevent chip side wall excessive corrosion, destroy LED chip overall structure, and then improve LED chip light extraction Efficiency reduces the production time, improves production efficiency.
In order to solve the above-mentioned technical problem, the utility model provides a kind of high brightness LED chip, including：
Substrate；
Set on the epitaxial layer of the substrate surface, wherein the epitaxial layer includes the first semiconductor set on substrate surface Layer is set to the active layer of first semiconductor layer surface, is set to the second semiconductor layer of the active layer surface；
First exposed region, first exposed region runs through second semiconductor layer and active layer, and extends to institute State the first semiconductor layer；
ITO layer, the ITO layer are set on second semiconductor layer, and the thickness of the ITO layer is
First electrode and second electrode, the first electrode are set on the first semiconductor layer of first exposed region, The second electrode runs through the ITO layer, and is arranged on second semiconductor layer；
Insulating layer, the insulating layer are set to the first semiconductor layer surface on ITO layer surface and the first exposed region.
As the improvement of said program, the thickness of the ITO layer is
As the improvement of said program, the thickness of the ITO layer is
As the improvement of said program, the width of first exposed region is 10-30 μm.
As the improvement of said program, the thickness of the insulating layer is
As the improvement of said program, the thickness of the epitaxial layer is 4-10 μm.
As the improvement of said program, the thickness of the epitaxial layer is 6 μm.
Implement the utility model, has the advantages that：
1, the utility model provides a kind of high brightness LED chip, including substrate, epitaxial layer, the first exposed region, ITO Layer, first electrode, second electrode and insulating layer, wherein the thickness setting of the ITO layer existsRange It is interior, by reducing the thickness of ITO layer, to prevent the side wall excessive corrosion of chip, destroy the overall structure of LED chip, in turn The light extraction efficiency of LED chip is improved, the production time is reduced, improves production efficiency.
Description of the drawings
Fig. 1 is the structural schematic diagram of the utility model high brightness LED chip；
Fig. 2 is the production method flow chart of the utility model high brightness LED chip；
Fig. 2 a are the structural schematic diagram after forming epitaxial layer；
Fig. 2 b are the structural schematic diagram to be formed after the first exposed region；
Fig. 2 c are the structural schematic diagram after forming ITO layer；
Fig. 2 d are the structural schematic diagram to be formed after the second exposed region；
Fig. 2 e are the structural schematic diagram to be formed after first electrode and the second motor.
Specific implementation mode
It is new to this practicality below in conjunction with attached drawing to keep the purpose of this utility model, technical solution and advantage clearer Type is described in further detail.
Referring to Fig. 1, the utility model improves a kind of high brightness LED chip, including：
Substrate 10；
Epitaxial layer 20 set on 10 surface of the substrate, wherein the epitaxial layer 20 includes set on the first of 10 surface of substrate Semiconductor layer 21 is set to the active layer 22 on 21 surface of the first semiconductor layer, is set to the second the half of 22 surface of the active layer Conductor layer 23；
First exposed region 24, first exposed region 24 run through second semiconductor layer 23 and active layer 22, and Extend to first semiconductor layer 21；
ITO layer 30, the ITO layer 30 are set on second semiconductor layer 23, and the thickness of the ITO layer 30 is
First electrode 41 and second electrode 42, what the first electrode 41 was set to first exposed region 24 the first half leads On body layer 21, the second electrode 42 runs through the ITO layer 30, and is arranged on second semiconductor layer 23；
Insulating layer 40, the insulating layer 40 are set to the first semiconductor layer on 30 surface of ITO layer and the first exposed region 24 21 surfaces.
It should be noted that the application is by existing the thickness setting of ITO layerIn the range of, by subtracting The thickness of few ITO layer to prevent the side wall excessive corrosion of chip, destroy the overall structure of LED chip, and then improves LED core The light extraction efficiency of piece reduces the production time, improves production efficiency.
Preferably, the thickness of the ITO layer 30 isMore, the thickness of the ITO layer is When the thickness of ITO layer 30 is less thanWhen, the adhesion strength of ITO layer 30 and electrode can be reduced, when the thickness of ITO layer 30 is more thanWhen, not only increase the formation time of ITO layer 30, also reducing the light extraction efficiency of LED chip further can also drop The adhesion strength of low ITO layer 30 and electrode.
In addition, the thickness when ITO layer 30 is more thanWhen, it is unfavorable for the control of subsequent wet etching, be easy to cause Corrosion is excessive, the phenomenon that LED chip side wall excessive erosion occurs, influences the side wall light extraction efficiency of LED chip.Due to ITO layer 30 It is covered in the second semiconductor layer 23 and exposed first semiconductor layer, 21 surface, and the side wall of chip and the first exposed region 24 sidewall surfaces do not have ITO layer 30, therefore, in subsequent corrosion, are easy the side wall excessive corrosion of LED chip.
Wherein, the material of the ITO layer 30 is indium tin oxide, favorably improves the conductive capability of ITO layer 30 in this way, prevents Carrier flocks together, and also improves the light extraction efficiency of LED chip.
In order to form first electrode 41 and not reduce light-emitting area, the width of first exposed region 24 is 10-30 μm.
In order to improve the yield of chip, the thickness of the epitaxial layer 20 is 4-10 μm.When the thickness of epitaxial layer 20 is less than 4 μ The brightness of m, LED chip can reduce, in subsequent etching, the case where LED chip is susceptible to sliver.But the thickness of epitaxial layer 20 More than 10 μm, the brightness of LED chip can reduce, and increase difficulty and the time of etching.In the present embodiment, the thickness of the epitaxial layer Degree is 6 μm.
Wherein, the thickness of the insulating layer 40 isFurther, the insulating layer 40 is silica, nitrogen One kind in SiClx and aluminium oxide.
Correspondingly, present invention also provides a kind of production method of high brightness LED chip, flow chart is as shown in Fig. 2, packet Include following steps：
S1：One substrate is provided；
The material of substrate can be sapphire, silicon carbide or silicon, or other semi-conducting materials, it is excellent in the present embodiment It is Sapphire Substrate to select substrate.
S2：Epitaxial layer is formed in the substrate surface；
As shown in Figure 2 a, epitaxial layer 20 is formed on 10 any one surface of substrate, wherein the epitaxial layer 20 includes being set to institute First semiconductor layer 21 on 10 surface of substrate is stated, the active layer 22 on 21 surface of the first semiconductor layer is set to, is set to 22 table of active layer Second semiconductor layer 23 in face.
Specifically, the first semiconductor layer provided by the embodiments of the present application and the second semiconductor layer are gallium nitride-based semiconductor Layer, active layer are gallium nitride base active layer；In addition, the first semiconductor layer provided by the embodiments of the present application, the second semiconductor layer and The material of active layer can also be other materials, be not particularly limited to this application.
Wherein, the first semiconductor layer can be n type semiconductor layer, then the second semiconductor layer is p type semiconductor layer；Alternatively, First semiconductor layer is p type semiconductor layer, and the second semiconductor layer is n type semiconductor layer, for the first semiconductor layer and second The conduction type of semiconductor layer needs to be designed according to practical application, is not particularly limited to this application.
It should be noted that in order to improve the yield of subsequent etching technics, the thickness of the epitaxial layer is 4-10 μm.When The thickness of epitaxial layer is less than 4 μm, and the brightness of LED chip can reduce, and in subsequent etching, LED chip is susceptible to the feelings of sliver Condition.But the thickness of epitaxial layer is more than 10 μm, and the brightness of LED chip can reduce, and increase difficulty and the time of etching.In the present embodiment In, the thickness of the epitaxial layer is 6 μm.
It should be noted that in the other embodiment of the application, it is equipped between the substrate 10 and the epitaxial layer 20 Caching rushes layer (not shown).
S3：The epitaxial layer is etched, the first exposed region is formed；
As shown in 2b, the epitaxial layer 20 is etched, be etched to the first semiconductor layer 21 and forms the first exposed area Domain 24 exposes first semiconductor layer 21.Specifically, being lost to the epitaxial layer 20 using ICP etching apparatus It carves, etching depth is 1-2 μm.In order to which the width for forming first electrode and do not reduce the first exposed region described in light-emitting area is 10-30μm。
S4：ITO layer is formed on said epitaxial layer there；
As shown in Figure 2 c, ITO layer 30 is formed on the epitaxial layer 20.Specifically, using electron beam evaporation process in institute It states 20 surface of epitaxial layer and one layer of ITO layer 30 is deposited.Wherein, the ITO layer 30 is covered in second semiconductor layer 23 and exposed 21 surface of the first semiconductor layer out.
It should be noted that vapor deposition temperature is 200-350 DEG C, oxygen flow 5-20sccm, vapor deposition chamber vacuum degree is 3.0-10.0E-5 evaporation time 50-300min.When temperature is deposited less than 200 DEG C, ITO layer 30 can not obtain enough energy Amount is migrated, and the ITO layer 30 of formation is second-rate, and defect is more；When temperature is deposited higher than 350 DEG C, temperature is excessively high, film energy Measure it is excessive be not easy to deposit on epitaxial layer, deposition rate is slack-off, efficiency reduce.When oxygen flow is less than 5sccm, oxygen flow Too low, ITO layer 30 aoxidizes insufficient, and film quality is bad, and when oxygen flow is more than 20sccm, oxygen flow is too big, ITO layer 30 Excessive oxidation, film layer defect concentration increase.When evaporation time is less than 50min, film needs higher deposition rate can be only achieved Required thickness, deposition rate is too fast, and atom has little time to migrate, therefore film growth quality is poor, and defect is more.
Preferably, vapor deposition temperature is 290 DEG C, oxygen flow 10sccm, and vapor deposition chamber vacuum degree is 3.0*10-5-10.0* 10-5。
Specifically, the thickness of the ITO layer 30 isPreferably, the thickness of the ITO layer 30 isWhen the thickness of ITO layer 30 is less thanWhen, the adhesion strength of ITO layer 30 and electrode can be reduced, ITO layer is worked as 30 thickness is more thanWhen, not only increase the formation time of ITO layer 30, the light extraction efficiency of LED chip is also reduced, into one Step ground, can also reduce the adhesion strength of ITO layer 30 and electrode.
In addition, the thickness when ITO layer 30 is more thanWhen, it is unfavorable for the control of subsequent wet etching, be easy to cause Corrosion is excessive, the phenomenon that LED chip side wall excessive erosion occurs, influences the side wall light extraction efficiency of LED chip.Due to ITO layer 30 It is covered in the second semiconductor layer 23 and exposed first semiconductor layer, 21 surface, and the side wall of chip and the first exposed region 24 sidewall surfaces do not have ITO layer 30, therefore, in subsequent corrosion, are easy the side wall excessive corrosion of LED chip.
Wherein, the material of the ITO layer 30 is indium tin oxide, but not limited to this.The ratio of indium and tin in indium tin oxide Example is 70-99:1-30.Preferably, the ratio of indium and tin is 95 in indium tin oxide:5.Leading for ITO layer 30 is favorably improved in this way Electric energy power, prevents carrier from flocking together, and also improves the light extraction efficiency of LED chip.
S5：The ITO layer is performed etching using wet corrosion technique, forms the second exposed region；
As shown in Figure 2 d, the ITO layer 30 is performed etching using wet corrosion technique, forms the second exposed region 31, And first exposed area 24 being exposed, wherein second exposed region 31 is etched to second semiconductor layer 23, A diameter of 0.5-8 μm of second exposed region 31.
Specifically, the wet corrosion technique includes：Using FeCl3ITO layer 30 is lost with the mixed solution of HCl It carves, etching period is 100-1000 seconds.It is less than 100 seconds between when etched, etching is insufficient, cannot form the second exposed region 31 With first exposed region 24 cannot be exposed.It is more than 1000 seconds between when etched, etching is excessive, by LED chip Side wall excessive corrosion destroys the structure of LED chip, reduces light extraction efficiency.Preferably, etching period is 170 seconds.It needs to illustrate It is, in order not to excessively reduce the area of ITO layer 30, to ensure the current expansion of LED chip, ensures that second electrode has enough again Formation space, prevent electrode from being fallen in subsequent test, a diameter of 0.5-8 μm of second exposed region 31. Preferably, a diameter of 1 μm of second exposed region 31.It is difficult when the diameter of second exposed region 31 is less than 0.5 μm To form second electrode, and the electric conductivity of electrode is influenced, the current distribution of chip is not uniform enough.When second exposed region When 31 diameter is more than 8 μm, the etching area of ITO layer 30 is larger, influences the performance of ITO layer 30, makes the current distribution of chip not It is enough uniform.
It should be noted that the diameter of the time of the thickness of ITO layer 30, wet etching and the second exposed region 31, three Between there are certain contacts.Wherein, the thickness effect of ITO layer 30 time of wet etching, and the time of wet etching Affect the diameter of the second exposed region 31.Specifically, the thickness of ITO layer 30 is big, in order to go unwanted ITO layer 30 It removes, the time of wet etching is just grown, so that the diameter of the second exposed region 31 is with regard to big；The thickness of ITO layer 30 is small, wet etching Time with regard to short, to the second exposed region 31 diameter with regard to small.
S6：First electrode is formed in first exposed region, second electrode is formed in second exposed region；
As shown in Figure 2 e, first electrode 41 is formed in first exposed region 24, in 31 shape of the second exposed region At second electrode 42.Specifically, using electron beam evaporation plating, magnetron sputtering, plating or chemical plating process, in first exposed area First semiconductor layer, the 21 surface deposition filling metal layer in domain 24 forms first electrode 41, the of second exposed region 31 Two semiconductor layers, 23 surface deposition filling metal layer forms second electrode 42.
It should be noted that in order to increase contact area, the second electrode 42 of first electrode 41 and the first semiconductor layer 21 With the contact area of the second semiconductor layer 23, the thickness of the first electrode 41 and second electrode 42 is 1-4 μm.Wherein, institute The thickness for stating second electrode 42 is more than the depth of the second exposed region 31, and the second electrode 42 is covered in the ITO layer 30 Surface.In this way, increasing the contact area of second electrode 42 and ITO layer 30, to strengthen gluing for second electrode 42 and ITO layer 30 Attached power mentions the reliability of chip.Preferably, the first electrode or the second electrode by Cr, Ni,Ti、Pt、 W、Pb、Rh、Sn、Cu、One or more of be made.
It needs, as shown in Figure 1, after forming first electrode 41 and second electrode 42, it is further comprising the steps of：
Insulating layer 40 is formed on 30 surface of the ITO layer and exposed first semiconductor layer, 21 surface；To described exhausted Edge layer 400 performs etching, and first electrode 41 and second electrode 42 are exposed.
Specifically, the insulating layer 40 is made of one or more of silica, silicon nitride and aluminium oxide.
The utility model is expanded on further with specific embodiment below
Embodiment 1
A kind of production method of high brightness LED chip, including：
One Sapphire Substrate is provided；
Epitaxial layer is formed in the Sapphire Substrate, the epitaxial layer includes being sequentially arranged in the sapphire substrate surface N type gallium nitride layer, active layer and p-type gallium nitride layer, the thickness of the epitaxial layer is 6 μm；
The epitaxial layer is etched using ICP etching apparatus, forms the first exposed region, first exposed region It is etched to the first semiconductor layer；
One layer of ITO layer is deposited on p-type gallium nitride layer surface using electron beam evaporation process, the thickness of the ITO layer isWherein, vapor deposition temperature is 290 DEG C, oxygen flow 10sccm, and vapor deposition chamber vacuum degree is 5.0E-5, evaporation time For 150min；
Using FeCl3Wet etching is carried out to ITO layer with the mixed solution of HCl, forms the second exposed region, and will be described First exposed area exposes, and etching period is 500 seconds, a diameter of 5 μm of second exposed region；
First electrode is formed in first exposed region, second electrode is formed in second exposed region.
Embodiment 2
A kind of production method of high brightness LED chip, including：
One Sapphire Substrate is provided；
Epitaxial layer is formed in the Sapphire Substrate, the epitaxial layer includes being sequentially arranged in the sapphire substrate surface N type gallium nitride layer, active layer and p-type gallium nitride layer, the thickness of the epitaxial layer is 6 μm；
The epitaxial layer is etched using ICP etching apparatus, forms the first exposed region, first exposed region It is etched to the first semiconductor layer；
One layer of ITO layer is deposited on p-type gallium nitride layer surface using electron beam evaporation process, the thickness of the ITO layer isWherein, vapor deposition temperature is 290 DEG C, oxygen flow 10sccm, and vapor deposition chamber vacuum degree is 5.0E-5, evaporation time is 100min；
Using FeCl3Wet etching is carried out to ITO layer with the mixed solution of HCl, forms the second exposed region, and will be described First exposed area exposes, and etching period is 320 seconds, a diameter of 3 μm of second exposed region；
First electrode is formed in first exposed region, second electrode is formed in second exposed region.
Embodiment 3
A kind of production method of high brightness LED chip, including：
One Sapphire Substrate is provided；
Epitaxial layer is formed in the Sapphire Substrate, the epitaxial layer includes being sequentially arranged in the sapphire substrate surface N type gallium nitride layer, active layer and p-type gallium nitride layer, the thickness of the epitaxial layer is 6 μm；
The epitaxial layer is etched using ICP etching apparatus, forms the first exposed region, first exposed region It is etched to the first semiconductor layer；
One layer of ITO layer is deposited on p-type gallium nitride layer surface using electron beam evaporation process, the thickness of the ITO layer isWherein, vapor deposition temperature is 290 DEG C, oxygen flow 10sccm, and vapor deposition chamber vacuum degree is 5.0E-5, evaporation time is 80min；
Using FeCl3Wet etching is carried out to ITO layer with the mixed solution of HCl, forms the second exposed region, and will be described First exposed area exposes, and etching period is 170 seconds, a diameter of 1 μm of second exposed region；
First electrode is formed in first exposed region, second electrode is formed in second exposed region.
Comparative example 1
A kind of production method of LED chip, including：
One Sapphire Substrate is provided；
Epitaxial layer is formed in the Sapphire Substrate, the epitaxial layer includes being sequentially arranged in the sapphire substrate surface N type gallium nitride layer, active layer and p-type gallium nitride layer, the thickness of the epitaxial layer is 6 μm；
The epitaxial layer is etched using ICP etching apparatus, forms the first exposed region, first exposed region It is etched to the first semiconductor layer；
One layer of ITO layer is deposited on p-type gallium nitride layer surface using electron beam evaporation process, the thickness of the ITO layer isWherein, vapor deposition temperature is 290 DEG C, oxygen flow 10sccm, and vapor deposition chamber vacuum degree is 5.0E-5, evaporation time For 200min；
Using FeCl3Wet etching is carried out to ITO layer with the mixed solution of HCl, forms the second exposed region, and will be described First exposed area exposes, and etching period is 600 seconds, a diameter of 7 μm of second exposed region；
First electrode is formed in first exposed region, second electrode is formed in second exposed region.
Comparative example 2
A kind of production method of high brightness LED chip, including：
One Sapphire Substrate is provided；
Epitaxial layer is formed in the Sapphire Substrate, the epitaxial layer includes being sequentially arranged in the sapphire substrate surface N type gallium nitride layer, active layer and p-type gallium nitride layer, the thickness of the epitaxial layer is 6 μm；
The epitaxial layer is etched using ICP etching apparatus, forms the first exposed region, first exposed region It is etched to the first semiconductor layer；
One layer of ITO layer is deposited on p-type gallium nitride layer surface using electron beam evaporation process, the thickness of the ITO layer isWherein, vapor deposition temperature is 290 DEG C, oxygen flow 10sccm, and vapor deposition chamber vacuum degree is 5.0E-5, evaporation time is 70min；
Using FeCl3Wet etching is carried out to ITO layer with the mixed solution of HCl, forms the second exposed region, and will be described First exposed area exposes, and etching period is 100 seconds, a diameter of 0.5 μm of second exposed region；
First electrode is formed in first exposed region, second electrode is formed in second exposed region.
Above-described embodiment 1-3 is the specific embodiment of the production method of the application high brightness LED chip, comparative example 1- 2 be the embodiment of the production method of existing LED chip.Wherein, the size of said chip is consistent, will be in above-described embodiment 1-3 The LED chip that is made in the high brightness LED chip and comparative example 1-2 that are made carries out bonding wire burin-in process and bright Degree test, it is as a result as follows：
It can be seen that the appearance that LED chip is made using the production method of existing LED chip from above-mentioned test result Easily there is bonding wire power down pole phenomenon, and brightness is relatively low.Wherein, the diameter and etch period of the thickness of ITO layer, the second exposed region There is important influence to the photoelectric properties of LED chip.Specifically, the thickness when ITO layer is less thanWhen, electrode can be reduced With the adhesion strength of bonding wire, the brightness of chip is reduced.When the thickness of ITO layer is more thanWhen, not only increase the formation of ITO layer Time increases the time of wet etching, increases the area of the second exposed region, also reduces the light extraction efficiency of LED chip, further Ground can also reduce the adhesion strength of conductive electrode and bonding wire.
Above disclosed is only a kind of the utility model preferred embodiment, cannot limit this practicality with this certainly Novel interest field, therefore equivalent variations made according to the claim of the utility model still belong to what the utility model was covered Range.

Claims (7)

1. a kind of high brightness LED chip, including：
Substrate；
Set on the epitaxial layer of the substrate surface, wherein the epitaxial layer includes the first semiconductor layer set on substrate surface, if In the active layer of first semiconductor layer surface, it is set to the second semiconductor layer of the active layer surface；
First exposed region, first exposed region run through second semiconductor layer and active layer, and extend to described the Semi-conductor layer；
ITO layer, the ITO layer are set on second semiconductor layer, and the thickness of the ITO layer is
First electrode and second electrode, the first electrode is set on the first semiconductor layer of first exposed region, described Second electrode runs through the ITO layer, and is arranged on second semiconductor layer；
Insulating layer, the insulating layer are set to the first semiconductor layer surface on ITO layer surface and the first exposed region.
2. high brightness LED chip according to claim 1, which is characterized in that the thickness of the ITO layer is
3. high brightness LED chip according to claim 2, which is characterized in that the thickness of the ITO layer is
4. high brightness LED chip according to claim 1, which is characterized in that the width of first exposed region is 10- 30μm。
5. high brightness LED chip according to claim 1, which is characterized in that the thickness of the insulating layer is
6. high brightness LED chip according to claim 1, which is characterized in that the thickness of the epitaxial layer is 4-10 μm.
7. high brightness LED chip according to claim 6, which is characterized in that the thickness of the epitaxial layer is 6 μm.
CN201721790544.8U 2017-12-18 2017-12-18 A kind of high brightness LED chip Active CN207651513U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201721790544.8U CN207651513U (en) 2017-12-18 2017-12-18 A kind of high brightness LED chip

Publications (1)

Publication Number Publication Date
CN207651513U true CN207651513U (en) 2018-07-24

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Country Link
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