CN207624697U - A kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor - Google Patents
A kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor Download PDFInfo
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- CN207624697U CN207624697U CN201721916990.9U CN201721916990U CN207624697U CN 207624697 U CN207624697 U CN 207624697U CN 201721916990 U CN201721916990 U CN 201721916990U CN 207624697 U CN207624697 U CN 207624697U
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Abstract
The utility model proposes a kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressors, including chip body, there is the ports I/O on chip body, there are two branches in the ports I/O to the chip body back side, two branches are opened with deep trench isolation, wherein branch routing P+, N epi, BN, a P sub compositions, BN and P sub form TVS pipe, and P+ and N Epi form general-purpose diode；Another branch routing P sub, N epi, N+, P+ are formed, and wherein N+/P+ forms TVS pipe, and P sub, N epi form general-purpose diode；It realizes that bi-directional electrostatic is protected using a chips, need to only select a chips to carry out primary front routing operation when packaged, encapsulation is simple, can reduce production cost.
Description
Technical field
The utility model is related to semiconductor devices more particularly to a kind of vertical structure bidirectional low-capacitance transient voltage to inhibit
Device.
Background technology
The Transient Voltage Suppressor overwhelming majority of low capacitance currently on the market is unidirectional, for forward and reverse electrostatic
Protection then needs two such TVS chips.Realize that bi-directional electrostatics are protected using two unidirectional TVS chips, it is maximum not
Foot place is exactly of high cost, market competition force difference.Therefore, it is necessary to which the Transient Voltage Suppressor to this low capacitance carries out structure
Optimization, to overcome drawbacks described above.
Utility model content
The purpose of this utility model is to provide a kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor, utilizes a core
Piece realizes bi-directional electrostatic protection.
The utility model is technical solution used by solving its technical problem：
A kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor, including chip body have the ends I/O on chip body
Mouthful, wherein：
The ports I/O have two branches, two branches to be opened with deep trench isolation to the chip body back side, wherein a branch route P
+, N-epi, BN, P-sub composition, BN and P-sub form TVS pipe, and P+ and N-Epi forms general-purpose diode；Another branch routing
P-sub, N-epi, N+, P+ are formed, and wherein N+/P+ forms TVS pipe, and P-sub, N-epi form general-purpose diode；When walking for electric current
To be I/O → GND when, the branch on the left side can be selected；When the trend of electric current is GND → I/O, then the branch on right side can be selected.
An electrode is used as in chip body front by routing extraction, and the back side of chip is directly connected to base substrate
Another electrode need to only select a chips to carry out primary front routing operation when packaged.
The current-voltage relation curve and capacitance all same of two branches are a symmetrical low-capacitance TVS structures.
The utility model has the advantage of：
The ports Transient Voltage Suppressor I/O have two branches, two branches to be opened with deep trench isolation to the chip body back side
Come, when the trend of electric current is I/O to GND, the branch on the left side can be selected；When the trend of electric current is GND to I/O, then can select
The branch for selecting right side realizes that bi-directional electrostatic is protected using a chips, and an electricity is used as in chip body front by routing extraction
The back side of pole, chip is directly connected to another electrode with base substrate, need to only select a chips to carry out when packaged primary
Front routing operation, encapsulation is simple, can reduce production cost.
Description of the drawings
Fig. 1 be the utility model proposes vertical structure bidirectional low-capacitance Transient Voltage Suppressor structural schematic diagram；
Fig. 2 is the equivalent circuit diagram of the Transient Voltage Suppressor；
Fig. 3 is the fabrication processing figure of the Transient Voltage Suppressor.
Specific implementation mode
In order to make the technical means, creative features, achievement of purpose, and effectiveness of the utility model be easy to understand, under
Face combines diagram and specific embodiment, and the utility model is expanded on further.
As shown in Figure 1 and Figure 2, the utility model proposes vertical structure bidirectional low-capacitance Transient Voltage Suppressor include core
Piece ontology, has the ports I/O on chip body, and there are two branches in the ports I/O to the chip body back side, two branch deep trouths every
It leaves, wherein branch routing P+, N-epi, BN, P-sub composition, BN and P-sub form TVS pipe, P+ and N-Epi is formed commonly
Diode；Another branch routing P-sub, N-epi, N+, P+ are formed, and wherein N+/P+ forms TVS pipe, and P-sub, N-epi form general
Logical diode；When the trend of electric current is I/O → GND, the branch on the left side can be selected；When the trend of electric current is GND → I/O,
The branch on right side can then be selected.An electrode is used as in chip body front by routing extraction, and the back side of chip is directly and pedestal
Substrate connection need to only select a chips to carry out primary front routing operation when packaged as another electrode.Two branches
Current-voltage relation curve and capacitance all same are a symmetrical low-capacitance TVS structures.
The vertical structure bidirectional low-capacitance Transient Voltage Suppressor includes 7 photoetching levels during front process：It buries
Layer, N plus, P plus, Trench, Contact, Metal and passivation layer.Whole technological process is as shown in Figure 3：
1, Substrate feeds intake, and selects the substrate material of p-type, resistivity is in 10~50M Ω cm or so；
2, Screen OX inject masking layerLeft and right；
3, BN Photo, buried layer photoetching, including gluing, exposure, development；
4, BN implant, injection N-type impurity (arsenic, antimony or phosphorus), energy is in 40~120kev, and dosage is in the E16 orders of magnitude；
5, PR strip remove the photoresist retained after BN photoetching；
6, BN drive in, buried layer promote, and temperature is maintained at 900~1200 DEG C, and the time continues 60min~200min；
7, Back seal are first LPTEOS, then are LPSi3N4Wafer side and back-protective are got up, prevent extension from giving birth to
There is auto-dope in growth process；
8, Remove front oxide＆Nitride remove the SIO of wafer frontside2And Si3N4；
9, EPI Growth, epitaxial growth, N-type extension, resistivity are more than 250 Ω cm, and thickness is 5~20 μm；
10, Screen OX inject masking layerLeft and right；
11, N+Photo, N Plus photoetching, including gluing, exposure, developing process；
12, N+implant, injection N-type impurity (arsenic, antimony or phosphorus), energy is in 40~120kev, and dosage is in the E14 orders of magnitude；
13, PR strip remove the photoresist retained after N+ photoetching；
14, N+drive in, N Plus are promoted, and temperature is maintained at 900~1200 DEG C, and the time continues 60min~200min；
15, P+Photo, P Plus photoetching, including gluing, exposure, developing process；
16, P+implant, implanting p-type boron impurities, energy is in 40~100kev, and dosage is in the E15 orders of magnitude；
17, PR strip remove the photoresist retained after P+ photoetching；
18, Hardmask is deposited, hard mask deposit, 1.5 μm or so of PESiO2；
19, Trench Photo, trench lithography, including gluing, exposure, developing process；
20, Hardmask is etched, hard mask etching, using dry etching；
21, PR strip remove the photoresist retained after trench lithography；
22, Trench is etched, etching groove, and depth is 20 μm or so；
23, Hardmask Remove remove hard mask；
24, Trench fill, deep trouth filling, the first long linear oxide of generally useLeft and right, then long LPTEOS；
25, P+drive in, P Plus are promoted, and temperature is maintained at 900~1200 DEG C, and the time continues 20min~100min；
26, Contact Photo, contact hole photoetching, including gluing, exposure, developing process；
27, Contact Etch, contact hole etching, using dry method or wet etching；
28, Metal Sputter, metal sputtering, generally use Ti/TiN+4UM AlSiCu；
29, Metal Photo, metal lithographic, including gluing, exposure, developing process；
30, Metal Etch, metal etch, using dry method or wet etching；
31, Passivation is deposited, passivation deposit, using USG+Si3N4, overall thickness is 1.5 μm or so；
32, Passivation Photo are passivated photoetching, including gluing, exposure, development；
33, Passivation Etch, passivation etching, using dry etching；
34, Back grind, grinding back surface, thickness is depending on package requirements；
35, Back metal, back metal, type and thickness are depending on package requirements.
Embodiment of above is only to illustrate the technical concepts and features of the utility model, and its object is to allow the skill of this field
Art personnel understand the content of the utility model and are implemented, and can not limit the scope of protection of the utility model with this, all
According to the equivalent change or modification that the spirit of the present invention is substantially done, should all cover within the protection scope of the present utility model.
Claims (3)
1. a kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor, including chip body, there is the ends I/O on chip body
Mouthful, it is characterised in that：
The ports I/O have two branches, two branches to be opened with deep trench isolation to the chip body back side, wherein a branch route P+, N-
Epi, BN, P-sub are formed, and BN and P-sub forms TVS pipe, and P+ and N-Epi forms general-purpose diode；Another branch route P-
Sub, N-epi, N+, P+ are formed, and wherein N+/P+ forms TVS pipe, and P-sub, N-epi form general-purpose diode.
2. a kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor according to claim 1, it is characterised in that：
An electrode is used as in chip body front by routing extraction, and the back side of chip is directly connected to base substrate another
Electrode.
3. a kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor according to claim 1, it is characterised in that：
The current-voltage relation curve and capacitance all same of two branches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721916990.9U CN207624697U (en) | 2017-12-31 | 2017-12-31 | A kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721916990.9U CN207624697U (en) | 2017-12-31 | 2017-12-31 | A kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207624697U true CN207624697U (en) | 2018-07-17 |
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ID=62830814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721916990.9U Active CN207624697U (en) | 2017-12-31 | 2017-12-31 | A kind of vertical structure bidirectional low-capacitance Transient Voltage Suppressor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207624697U (en) |
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2017
- 2017-12-31 CN CN201721916990.9U patent/CN207624697U/en active Active
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