CN108899312A - A kind of unidirectional NPN punch ultralow pressure TVS structure and preparation method thereof - Google Patents
A kind of unidirectional NPN punch ultralow pressure TVS structure and preparation method thereof Download PDFInfo
- Publication number
- CN108899312A CN108899312A CN201810473559.4A CN201810473559A CN108899312A CN 108899312 A CN108899312 A CN 108899312A CN 201810473559 A CN201810473559 A CN 201810473559A CN 108899312 A CN108899312 A CN 108899312A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- sio
- front metal
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000002184 metal Substances 0.000 claims description 64
- 229910052751 metal Inorganic materials 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 44
- 229910052681 coesite Inorganic materials 0.000 claims description 28
- 229910052906 cristobalite Inorganic materials 0.000 claims description 28
- 239000000377 silicon dioxide Substances 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052682 stishovite Inorganic materials 0.000 claims description 28
- 229910052905 tridymite Inorganic materials 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 235000008429 bread Nutrition 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000006263 metalation reaction Methods 0.000 description 1
- 238000013316 zoning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention is a kind of unidirectional NPN punch ultralow pressure TVS structure and preparation method thereof,This TVS is suitable for protecting the semiconducter IC of ultra-low actuation voltage,With the continuous diminution of semiconducter IC manufacturing process minimum feature,The driving voltage of semiconducter IC also becomes lower and lower,Driving voltage is reduced to 5V from 12V,3.3V is arrived again,2.5V,This just needs the TVS breakdown voltage as overvoltage protection also accordingly to reduce,Preferably to protect semiconducter IC,After general-purpose diode TVS breakdown voltage is lower than 5V,Zener breakdown gradually replaces avalanche breakdown to become main breakdown form,The tunnel-effect of Zener breakdown causes electric leakage to increase to 1E-5A level,The not competent IC overvoltage protection work of diode at this time,The unidirectional NPN punch TVS of the invention utilizes the base area punchthrough characteristic of NPN transistor,By the concentration and thickness that control NPN transistor base area,Breakdown voltage can be accomplished lower than 5V,It can guarantee electric leakage down to 1E-9A level again simultaneously,The overvoltage protection work of completely competent ultralow pressure IC.
Description
Technical field
The invention belongs to a kind of TVS structure and preparation method thereof, this TVS is suitable for protecting the semiconductor of ultra-low operating voltage
IC。
Background technique
As the integrated level of semiconducter IC is constantly promoted, the continuous reduction of semiconductor fabrication process minimum feature, semiconductor
The maximum power that IC can be carried becomes lower, this just needs semiconducter IC operating voltage to become lower than original, could effectively drop
The power of low semiconducter IC carrying.In recent years, the operating voltage of semiconducter IC was reduced to 3.3V from 5V, dropped again from 3.3V later
As low as 2.5V, this just needs the TVS breakdown voltage as overvoltage protection also to reduce accordingly, partly leads preferably to protect
Body IC, after diode TVS breakdown voltage is lower than 5V, the tunnel-effect of Zener breakdown will lead to breakdown curve softening, and electric leakage increases
A series of problems, such as greatly to the level of 1E-5A, electric leakage, which increases, will lead to power consumption increase, and calorific value increases etc., the invention it is unidirectional
NPN punch TVS can accomplish that breakdown voltage is lower than 5V, while can guarantee outstanding breakdown curve again, and leak electricity down to 1E-9A
Level.
Summary of the invention
1, a kind of unidirectional NPN punch ultralow pressure TVS structure, structure include：The area NPN 301, the area NP 302, DN isolated area
The connected region 303 and DN 304.
A, 301 structure of the area NPN includes：It is substrate above back metal, is epitaxial layer above substrate, in substrate and epitaxial layer
Bread contains DP, includes SN inside DP, is SiO above epitaxial layer2Layer, SiO2Layer partially opens, SiO2Layer is above front metal,
Front metal partially opens, and is passivation layer above front metal, and passivation layer partially opens, wherein DP is connected with substrate, SN with just
Face metal is connected and is connected by front metal with the SN in the area NP 302.
B, 302 structure of the area NP includes：It is substrate above back metal, is epitaxial layer above substrate, in substrate and epitaxial layer
Bread contains DP, includes SN and SP inside DP, is SiO above epitaxial layer2Layer, SiO2Layer partially opens, SiO2Layer is positive gold above
Belonging to, it is passivation layer above front metal that front metal, which partially opens, wherein DP is connected with substrate, and SN is connected with front metal,
And SN is connected by front metal with the SN in the area NPN 301, SP is connected with front metal, and SP is connected to by front metal with DN
The SN in area 304 is connected, and the SN and SP in the area NP 302 is not attached to.
C, 303 structure of DN isolated area includes：It is substrate above back metal, is epitaxial layer, substrate and extension above substrate
Layer the inside includes DN, includes SN inside DN, is SiO above epitaxial layer2Layer, SiO2Layer is above front metal, front metal part
It opens, is passivation layer above front metal, wherein DN is connected with substrate.
D, 304 structure of the connected region DN includes：It is substrate above back metal, is epitaxial layer, substrate and extension above substrate
Layer the inside includes DN, includes SN inside DN, is SiO above epitaxial layer2Layer, SiO2Layer partially opens, SiO2Layer is positive gold above
Belonging to, it is passivation layer above front metal that front metal, which partially opens, and wherein DN is connected with substrate, and SN is connected with front metal, and
It is connected by front metal with the SP in the area NP 302.
2, a kind of preparation method of unidirectional NPN punch ultralow pressure TVS, method include：
A, the preparation of substrate 211 and the preparation of epitaxial layer 212, on N-type low-resistance single crystal silicon, growing P-type high resistant monocrystalline silicon layer；
B, prepared by DN221, passes through POCL3Technique doping, High temperature diffusion to DN are connected to substrate 211；
C, prepared by SP231, the highly concentrated p type impurity of ion implanting；
D, prepared by DP241, ion implanting p type impurity, high annealing；
E, prepared by SN251, passes through POCL3Technique adulterates P element, high annealing；
F, prepared by fairlead, SiO2Layer 261 deposits, photoetching, SiO2Etching；
G, prepared by front metal 271, metal layer deposit, photoetching, and metal layer etching is removed photoresist；
H, prepared by passivation layer 281, SiO2Deposit, SiN deposit, photoetching, SiN etching, SiO2Etching, removes photoresist；
I, thinning back side and back metal 291 are changed.
Detailed description of the invention
Fig. 1 is the equivalent circuit diagram of the unidirectional NPN punch ultralow pressure TVS of the invention；
Fig. 2 is the technique sectional view of the unidirectional NPN punch ultralow pressure TVS of the invention；
Fig. 3 is the zoning plan of the unidirectional NPN punch ultralow pressure TVS of the invention.
Number explanation：
101：The avalanche diode of TVS；
102：The series rectifier diode of TVS；
103：The rectifier diode in parallel of TVS；
104：The front electrode of TVS chip；
105：The rear electrode of TVS chip；
211：Substrate, substrate of the present invention are N-type low-resistance single crystal silicon；
212：Epitaxial layer, extension of the present invention are p type single crystal silicon；
221：The channel of DN, isolation and connection substrate 211；
231：SP, effect are to form Ohmic contact with front metal 271；
241：Reach through region when DP, TVS puncture, the area avalanche diode 101P, the area P of series rectifier diode 102, and it is in parallel
The area P of rectifier diode 103；
251：The area N of SN, TVS avalanche diode 101 and the ohmic contact regions of DN221 and front metal 271；
261：SiO2Layer, effect are isolation epitaxial layer 212 and 271 layers of front metal, make to insulate between it；
271：Front metal is used as the front electrode 104 of the wiring and TVS between diode, is exposed to outer part and is used as just
Face electrode 104；
281：Passivation layer, effect is to improve device reliability, usually using SiO2Layer+SiN layer；
291：Back metal is used as the rear electrode 105 of TVS chip, metal material and thickness according to encapsulation and requires preparation；
301：The area NPN of TVS, 102 region of avalanche diode 101 and series rectifier diode；
302：The area NP of TVS, 103 region of rectifier diode in parallel；
303：The DN isolated area of TVS, PN save area of isolation；
304：The connected region DN of TVS realizes that the area P of rectifier diode 103 in parallel is connected with substrate.
Specific embodiment
1. the preparation of substrate 211 and the preparation of epitaxial layer 212, on N-type low-resistance single crystal silicon, growing P-type high resistant monocrystalline silicon
Layer.The concentration of substrate, the concentration of extension and thickness have a major impact TVS electrical parameter.
2.DN221 preparation, passes through POCL3Technique doping, High temperature diffusion to DN is connected to substrate 211, effect be isolated and
Connect substrate.Since DN is not critical process, so be made in the preceding part of process flow, can to avoid DN thermal process to key
Process photo causes technique to be difficult to control at excessive heat affecting.
3.SP231 preparation, ion implanting large dosage p type impurity are usually injected into B element.SP with DN metal is connected, and effect is
Extraction electrode is to chip back, as long as accomplishing Ohmic contact.
4.DP241 preparation, ion implanting p type impurity, high annealing.DP is the area P of avalanche diode 101, while being string
The punch through region when area P and TVS for joining rectifier diode 102 puncture, and the area P of rectifier diode 103 in parallel, as
Critical process directly influences the breakdown voltage of TVS, while also influencing series rectifier diode 102 and rectifier diode in parallel
The key electricals such as 103 breakdown voltage, capacitor, electric leakage.
5.SN251 preparation, passes through POCL3Technique adulterates P element, high annealing.Other than lead function, the junction depth of SN
It is directly related to the width of the base area NPN, the concentration of SN is directly related to the breakdown voltage of TVS.
6. prepared by fairlead, SiO2Layer 261 deposits, photoetching, SiO2Etching.
7. prepared by front metal 271, metal layer deposit, photoetching, metal layer etching removes photoresist, is used as front electrode 104 and two
Wiring between pole pipe.
8. prepared by passivation layer 281, SiO2Deposit, SiN deposit, photoetching, SiN etching, SiO2Etching, removes photoresist.
9. thinning back side and back metal 291 are changed, require to carry out back thinning according to encapsulation and back metal, back-side gold
Belong to 291 rear electrode 105 as TVS chip.
The present invention is elaborated through the foregoing embodiment, while can also realize the present invention using other embodiments.The present invention
It is not limited to above-mentioned specific embodiment, therefore the present invention has attached claim scope restriction.
Claims (2)
1. a kind of unidirectional NPN punch ultralow pressure TVS structure, structure include：The area NPN 301, the area NP 302, DN isolated area 303
And the connected region DN 304,
A, 301 structure of the area NPN includes：It is substrate above back metal, is epitaxial layer, packet inside substrate and epitaxial layer above substrate
Containing DP, includes SN inside DP, be SiO above epitaxial layer2Layer, SiO2Layer partially opens, SiO2Layer is above front metal, front
Metal part is opened, and is passivation layer above front metal, passivation layer partially opens, wherein DP is connected with substrate, SN and front gold
Symbolic animal of the birth year even and by front metal is connected with the SN in the area NP 302；
B, 302 structure of the area NP includes：It is substrate above back metal, is epitaxial layer, packet inside substrate and epitaxial layer above substrate
Containing DP, includes SN and SP inside DP, be SiO above epitaxial layer2Layer, SiO2Layer partially opens, SiO2Layer is above front metal,
Front metal partially opens, and is passivation layer above front metal, wherein DP is connected with substrate, and SN is connected with front metal, and SN
It is connected by front metal with the SN in the area NPN 301, SP is connected with front metal, and SP passes through front metal and the connected region DN 304
SN be connected, the SN and SP in the area NP 302 is not attached to；
C, 303 structure of DN isolated area includes：It is substrate above back metal, is epitaxial layer above substrate, in substrate and epitaxial layer
Bread contains DN, includes SN inside DN, is SiO above epitaxial layer2Layer, SiO2Layer is above front metal, and front metal part is beaten
It opens, is passivation layer above front metal, wherein DN is connected with substrate；
D, 304 structure of the connected region DN includes：It is substrate above back metal, is epitaxial layer above substrate, in substrate and epitaxial layer
Bread contains DN, includes SN inside DN, is SiO above epitaxial layer2Layer, SiO2Layer partially opens, SiO2Layer is above front metal,
Front metal partially opens, and is passivation layer above front metal, and wherein DN is connected with substrate, and SN is connected with front metal, and logical
Front metal is crossed to be connected with the SP in the area NP 302.
2. a kind of preparation method of unidirectional NPN punch ultralow pressure TVS, method include：
A, the preparation of substrate 211 and the preparation of epitaxial layer 212, on N-type low-resistance single crystal silicon, growing P-type high resistant monocrystalline silicon layer；
B, prepared by DN221, passes through POCL3Technique doping, High temperature diffusion to DN are connected to substrate 211；
C, prepared by SP231, the highly concentrated p type impurity of ion implanting；
D, prepared by DP241, ion implanting p type impurity, high annealing；
E, prepared by SN251, passes through POCL3Technique adulterates P element, high annealing；
F, prepared by fairlead, SiO2Layer 261 deposits, photoetching, SiO2Etching；
G, prepared by front metal 271, metal layer deposit, photoetching, and metal layer etching is removed photoresist；
H, prepared by passivation layer 281, SiO2Deposit, SiN deposit, photoetching, SiN etching, SiO2Etching, removes photoresist；
I, thinning back side and back metal 291 are changed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810473559.4A CN108899312A (en) | 2018-05-17 | 2018-05-17 | A kind of unidirectional NPN punch ultralow pressure TVS structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810473559.4A CN108899312A (en) | 2018-05-17 | 2018-05-17 | A kind of unidirectional NPN punch ultralow pressure TVS structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108899312A true CN108899312A (en) | 2018-11-27 |
Family
ID=64342865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810473559.4A Pending CN108899312A (en) | 2018-05-17 | 2018-05-17 | A kind of unidirectional NPN punch ultralow pressure TVS structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108899312A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109599332A (en) * | 2018-12-27 | 2019-04-09 | 朝阳无线电元件有限责任公司 | A kind of low volt voltage adjustment diode manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680962A (en) * | 2017-09-27 | 2018-02-09 | 安徽富芯微电子有限公司 | A kind of low forward voltage TVS device and its manufacture method |
| CN207381398U (en) * | 2017-11-14 | 2018-05-18 | 上海芯石半导体股份有限公司 | A kind of unidirectional NPN punches ultralow pressure TVS structures |
-
2018
- 2018-05-17 CN CN201810473559.4A patent/CN108899312A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680962A (en) * | 2017-09-27 | 2018-02-09 | 安徽富芯微电子有限公司 | A kind of low forward voltage TVS device and its manufacture method |
| CN207381398U (en) * | 2017-11-14 | 2018-05-18 | 上海芯石半导体股份有限公司 | A kind of unidirectional NPN punches ultralow pressure TVS structures |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109599332A (en) * | 2018-12-27 | 2019-04-09 | 朝阳无线电元件有限责任公司 | A kind of low volt voltage adjustment diode manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104752417A (en) | Silicon controlled rectifier protection device and forming method thereof | |
| US8692289B2 (en) | Fast turn on silicon controlled rectifiers for ESD protection | |
| CN103384063B (en) | A kind of surge protection circuit and manufacture method thereof | |
| TW201320295A (en) | Semiconductor device | |
| US9019667B2 (en) | Protection device and related fabrication methods | |
| JP2012104834A (en) | High voltage bipolar-based esd protection structure | |
| US10483257B2 (en) | Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection | |
| CN106057781A (en) | Manufacture method of electrostatic discharge protection device | |
| CN105489657B (en) | A kind of one-way low pressure TVS device and manufacture method thereof | |
| CN108520896B (en) | Voltage-resistant bipolar transistor and manufacturing method thereof | |
| CN110518063B (en) | Trench MOSFET integrated with ESD protection and method of manufacture | |
| US11430780B2 (en) | TVS device and manufacturing method therefor | |
| CN108899312A (en) | A kind of unidirectional NPN punch ultralow pressure TVS structure and preparation method thereof | |
| CN207381398U (en) | A kind of unidirectional NPN punches ultralow pressure TVS structures | |
| CN111710675A (en) | Low-voltage ESD protection device and manufacturing method thereof | |
| CN207624703U (en) | A kind of two-way rapid hollow Transient Voltage Suppressor | |
| CN106229349B (en) | A kind of ultra-low capacitance low-voltage semiconductor discharge tube chip and its manufacturing method | |
| JP2021536127A (en) | Transient voltage suppression device and its manufacturing method | |
| CN106298777B (en) | A kind of GGNMOS device and preparation method thereof as ESD protection | |
| CN207381399U (en) | A kind of two-way NPN punches ultralow pressure TVS structures | |
| CN107731813A (en) | A kind of esd protection circuit and its manufacture method | |
| KR100936644B1 (en) | Semiconductor device and method for manufacturing thereof | |
| CN210167361U (en) | Trench MOSFET integrated ESD protection | |
| CN111199970B (en) | Transistor structure for electrostatic protection and manufacturing method thereof | |
| CN111710674A (en) | Ultra-low voltage trigger device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20181127 |
|
| WD01 | Invention patent application deemed withdrawn after publication |