CN207603588U - Digital parametric equalizer - Google Patents
Digital parametric equalizer Download PDFInfo
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- CN207603588U CN207603588U CN201721277310.3U CN201721277310U CN207603588U CN 207603588 U CN207603588 U CN 207603588U CN 201721277310 U CN201721277310 U CN 201721277310U CN 207603588 U CN207603588 U CN 207603588U
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- parametric equalizer
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Abstract
The utility model is related to the digital parametric equalizers in a kind of on-site programmable gate array FPGA, the digital parametric equalizer has the digital parameter balance module that can handle two channel audio data, each sound channel of the digital parameter balance module includes nine piece of digital wave filter groups, the nine piece of digital wave filter group has the 7 parameter peak wave filters connected in cascaded fashion, 1 high-pass filter or lower frame wave filter, 1 overhead wave filter or low-pass filter.Digital parametric equalizer involved by the utility model, it is realized in the field programmable gate array FPGA chip for having DSP processing capacities, various Digital Signal Processings can be carried out to audio signal, such as equalization parameter, audio mixing, synthesis the relevant technologies, and it can realize various effects, improve the parallel processing capability of traditional dsp chip.
Description
Technical field
The utility model is related to Audio Signal Processing technical field more particularly to a kind of digital parametric equalizers.
Background technology
At present, domestic and foreign scholars, research institution have been carried out compared with in-depth study digital parametric equalizer design method.
1997, S.J.Orfanidis proposed a kind of digital parametric equalizer designed with Nyquist sampling frequency processing gain,
This method is converted based on analog filter, it is ensured that the gain of designed digital filter is approached with analog filter.
2006, A.Fernandez-Vazquez and G.Jovanovic-Dolecek proposed straight using Butterworth filter principle
It is connected on the design that numeric field realizes digital parametric equalizer.In the same year, S.Yimman is proposed to be set with the method for zero-pole assignment
Notch filter and peak filter are counted, carries out realization digital parametric equalizer, the limitation of this digital parametric equalizer exists
0 is may be only configured in its yield value.
Invention content
The utility model is related to the digital parametric equalizer in a kind of on-site programmable gate array FPGA, the digital parameter is equal
Weighing apparatus has the digital parameter balance module that can handle two channel audio data, each sound channel of digital parameter balance module
Including nine piece of digital wave filter groups, which has the 7 parameter peak wave filters connected in cascaded fashion,
1 high-pass filter or lower frame wave filter, 1 overhead wave filter or low-pass filter.
Preferably, 7 parameter peak wave filters, 1 high-pass filter or lower frame wave filter, 1 overhead wave filter
Or low-pass filter is respectively iir digital filter.
Preferably, the iir digital filter is second order iir digital filter.
Digital parametric equalizer involved by the utility model, wherein, the maximum sample rate of audio data is 192kHz, is counted
The work clock of word parametric equalization module is 50MHz.
Digital parametric equalizer involved by the utility model, in the field programmable gate array for having DSP processing capacities
It is realized on fpga chip, various Digital Signal Processings, such as equalization parameter, audio mixing, synthesis can be carried out to audio signal
The relevant technologies, and can realize various effects.The utilization of field programmable gate array FPGA chip fully extends DSP in sound
The application of frequency processing, and improve the parallel processing capability of traditional dsp chip.
Description of the drawings
Below with reference to the accompanying drawings the preferred embodiment of the utility model described, attached drawing in order to illustrate the utility model preferred reality
Apply example rather than in order to limit the purpose of this utility model.In attached drawing,
Fig. 1 is that the digital parametric equalizer of the utility model embodiment realizes structural model；
Fig. 2 is the digital parameter balance module block diagram of the utility model embodiment；
Fig. 3 is the digital parameter balance module simulation result figure of the utility model embodiment.
Specific embodiment
Specific embodiment of the present utility model is used for illustrating the utility model, but be not limited to the specific implementation
Mode.
Fig. 1 is the structure diagram of the digital parametric equalizer of the utility model.
Selected frequency range can be strengthened or be weakened to digital parametric equalizer, to correct or change the signal spectrum of the frequency range.Number
Word parametric equalizer is substantially a wave filter with particularity.Due to being mutual indepedent between the multistage of Parametric equalizer
, the frequency response of adjacent segment should not be influenced on the adjusting of a certain section of parameter, it is possible to which N grades of wave filters are realized using cascade mode
Cascade, as shown in Figure 1.
Fig. 2 is the structure diagram of the digital parameter balance module of the utility model one embodiment.
As shown in Fig. 2, the utility model is related to the digital parametric equalizer in a kind of on-site programmable gate array FPGA, it should
Digital parametric equalizer has the digital parameter balance module that can handle two channel audio data, digital parameter balance module
Each sound channel include nine piece of digital wave filter groups, which has 7 parameters connecting in cascaded fashion
Peak filter, 1 high-pass filter or lower frame wave filter, 1 overhead wave filter or low-pass filter.
Digital parameter balance module is minimum module, is responsible for that the frequency spectrum of audio data is corrected or changed.The module
Each sound channel shares 9 iir filter cascades, and supports to handle the audio number that two-way sound channel maximum sample rate is 192kHz simultaneously
According to wherein sound channel can be enabled or closed by macrodefinition variable all the way.
7 parameter peak wave filters in digital parametric equalizer, 1 high-pass filter or lower frame wave filter, 1 overhead
Wave filter or low-pass filter, using second order iir digital filter.The advantages of iir digital filter structure be can with compared with
Few exponent number obtains higher selection characteristic.
Each iir filter exponent number is second order, wave filter calculation formula for y (n)=a0* [b0*x (n)+b1*x (n-1)+
b2*x(n-2)+a1*y(n-1)+a2*y(n-2)]。
One iir filter, which completes primary filtering, needs 6 multiplyings and 4 sub-addition operations.Specific calculating is as follows：
1.b0*x0；
2.b1*x1；
3.b0*x0+b1*x1；
4.b2*x2；
5.a1*y1；
6.a1*y1+b2*x2；
7.(a1*y1+b2*x2)+(b0*x0+b1*x1)；
8.a2*y2；
9.[(a1*y1+b2*x2)+(b0*x0+b1*x1)]+(a2*y2)；
10.a0*{[(a1*y1+b2*x2)+(b0*x0+b1*x1)]+(a2*y2)}.
Input audio data maximum sample rate is 192kHz, and module work clock is 50MHz, therefore audio data update is all
Phase is 260 work clocks, it is possible to realize multiplication and add operation using time division multiplexing mode in specific implementation.
There are 9 sections of wave filters in module, second order IIR filter can be updated using pipeline mode in an audio data again
9 sections of wave filters are realized in period.
Second order IIR multiplexing temporal specifications are as follows：
Calculate 1：B0 and x0 are sent to floating-point multiplier by the 1st clock, and the 7th clock latches the result that b0 is multiplied with x0
(because floating-point multiplier time delay is set as 5 clocks)；
Calculate 2：B1 and x1 are sent to floating-point multiplier by the 7th clock,
Calculate 3：The result that the latch b0 latched the results being multiplied with x0 and b1 are multiplied with x1 is sent to by the 13rd clock
Floating-point adder, the 21st clock latch floating-point adder output result (because floating-point multiplier time delay is set as 7 clocks)；
Calculate 4：B2 and x2 are sent to floating-point multiplier by the 13rd clock, the 19th clock deposit it is that b2 is multiplied with x2 as a result,
Calculate 5：A1 and y1 are sent to floating-point multiplier by the 19th clock,
Calculate 6：The result that the b2 latched the results being multiplied with x2 and a1 are multiplied with y1 is sent to floating-point by the 25th clock
Adder；
Calculate 7：The result that floating-point adder output result and the 21st clock latch is then sent through floating by the 33rd clock
Point adder；
The result of floating add twice is sent to floating-point adder by the 47th clock, and the 55th clock latches floating-point adder
Export result；
Calculate 8：A2 and y2 are sent to floating-point multiplier by the 35th clock；
Calculate 9：The result for calculating 7 and the result for calculating 8 are sent to floating-point adder by the 41st clock.
Calculate 10：The result of a0 and calculating 9 are sent to floating-point multiplier by the 49th clock, are finally obtained in the 55th clock
Filter results.
All it is serially to use since above-mentioned sequential is multiplier and adder when realizing 10 multiply-add calculating, then can profit
With pipeline mode come cascading multiple stages iir filter.According to sequential above, 64 clock cycle can at most realize 6 grades of cascades.
So as to complete to handle two-way sound channel sound simultaneously with 9 sections of wave filters required by the utility model within 256 clock cycle
Frequency data function.
Functional simulation, emulation platform altera-modelsim are carried out to digital parametric equalization module.
Fig. 3 is digital parameter balance module simulation result figure.
Test input signal is a tone signal, and filter parameter is generated the wave filter of 9 all-pass by matlab softwares
And it is cured in test platform.For simulation result as shown in figure 3, from the point of view of waveform, the tone signal of input passes through 9 all-pass IIR
It can normally be exported after wave filter, illustrate that digital parameter balance module function is correct.
The cyclone IV series EP4CE11529C7 encoded number parameters of use site programmable gate array FPGA chip
Balance module.
Digital parametric equalizer involved by the utility model, in the field programmable gate array for having DSP processing capacities
It is realized on fpga chip, various Digital Signal Processings, such as equalization parameter, audio mixing, synthesis can be carried out to audio signal
The relevant technologies, and can realize various effects.
Claims (4)
1. the digital parametric equalizer in a kind of on-site programmable gate array FPGA, it is characterized in that, digital parametric equalizer tool
The standby digital parameter balance module that can handle two channel audio data,
Each sound channel of the digital parameter balance module includes nine piece of digital wave filter groups, which has
The 7 parameter peak wave filters connected in cascaded fashion, 1 high-pass filter or lower frame wave filter, 1 overhead wave filter or low
Bandpass filter.
2. digital parametric equalizer according to claim 1, it is characterized in that, 7 parameter peak wave filters, 1 height
Bandpass filter or lower frame wave filter, 1 overhead wave filter or low-pass filter are respectively iir digital filter.
3. digital parametric equalizer according to claim 2, it is characterized in that, the iir digital filter is second order IIR numbers
Word wave filter.
4. digital parametric equalizer according to claim 1, it is characterized in that, wherein,
The maximum sample rate of the audio data is 192kHz,
The work clock of the digital parameter balance module is 50MHz.
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| CN201721277310.3U CN207603588U (en) | 2017-09-30 | 2017-09-30 | Digital parametric equalizer |
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| CN201721277310.3U CN207603588U (en) | 2017-09-30 | 2017-09-30 | Digital parametric equalizer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111966322A (en) * | 2020-08-31 | 2020-11-20 | 广州视源电子科技股份有限公司 | Audio signal processing method, device, equipment and storage medium |
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2017
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111966322A (en) * | 2020-08-31 | 2020-11-20 | 广州视源电子科技股份有限公司 | Audio signal processing method, device, equipment and storage medium |
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