CN207268837U - Digital frequency divider - Google Patents
Digital frequency divider Download PDFInfo
- Publication number
- CN207268837U CN207268837U CN201721280004.5U CN201721280004U CN207268837U CN 207268837 U CN207268837 U CN 207268837U CN 201721280004 U CN201721280004 U CN 201721280004U CN 207268837 U CN207268837 U CN 207268837U
- Authority
- CN
- China
- Prior art keywords
- frequency
- sound channel
- frequency divider
- iir
- digital filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
It the utility model is related to the digital frequency divider in a kind of on-site programmable gate array FPGA, the digital frequency divider possesses frequency division module, audio signal is divided into low frequency, Low Medium Frequency, high intermediate frequency, high frequency totally four tunnel sound channel by the frequency division module, low-frequency channel is made of 3 iir digital filter cascades, Low Medium Frequency sound channel is made of 6 iir digital filter cascades, high intermediate frequency sound channel is made of 6 iir digital filter cascades, and high frequency sound channel is made of 3 iir digital filter cascades.The digital frequency divider that the utility model is related to, can change frequency divider parameter in real time in the case where not changing hardware, realize that flexibly high-order frequency divider easy to implement, meets high-precision requirement.Using the fpga chip for possessing DSP disposal abilities, applications of the DSP in audio frequency process is fully extended, and improve the parallel processing capability of traditional dsp chip.
Description
Technical field
It the utility model is related to Audio Signal Processing technical field, more particularly to a kind of digital frequency divider.
Background technology
Traditional dividing filter is mainly realized by analog circuit, is divided into Passive device and Active crossover device, wherein by
Dynamic frequency divider is that power amplifier passes behind passive circuit (only inductance, capacitance and resistance) to realize corresponding frequency-division filter, such a
Circuit realizes that simply, but since impedance error is big, the frequency dividing impact of performance is poor, while realizes higher order filter difficulty；Compared to
Passive device, Active crossover device are divided before being power amplifier, because activated amplifier can be used, it can realize higher
The wave filter of rank, its cost are the increase in power amplifier number.
Therefore as the reduction of digital signal processing chip cost, the application of digital frequency divider are more and more extensive.Fig. 1 is number
Word allocator module figure, as shown in Figure 1, compared to analogous frequency divider, digital frequency divider can be real in the situation for not changing hardware
When change frequency divider parameter.
At present, foreign scholar, research institution have been carried out compared with in-depth study digital desiging frequency divider method, it is proposed that
Many design methods, and there are many products to realize the function.Contained if Foobar2000 softwares
This plug-in unit of crossover.
The country also has many research institutions to have studied digital frequency divider and achieves certain achievement in research at present.As greatly
Even Polytechnics completes the design and realization of many digital frequency dividers.But the research of most domestic is mainly concentrated at present
Realized with dsp chip, and the case that few FPGA are realized.
The content of the invention
The digital frequency divider in a kind of on-site programmable gate array FPGA is the utility model is related to, which possesses
Audio signal is divided into low frequency, Low Medium Frequency, high intermediate frequency, high frequency totally four tunnel sound channel by frequency division module, frequency division module, wherein, all-bottom sound
Road is made of 3 iir digital filter cascades, and Low Medium Frequency sound channel is made of 6 iir digital filter cascades, high intermediate frequency sound channel
It is made of 6 iir digital filter cascades, high frequency sound channel is made of 3 iir digital filter cascades.
Preferably, each iir filter exponent number is second order.
Digital frequency divider described in the utility model, input audio data maximum sample rate is 192kHz, when module works
Clock is 50MHz, and multiplication and add operation are realized using time division multiplexing mode.
There are 9 sections of wave filters in the frequency division module, to the second order IIR filter using pipeline mode in an audio number
According to realizing 9 sections of wave filters in the update cycle.
The digital frequency divider that the utility model is related to, can change frequency divider ginseng in real time in the case where not changing hardware
Number, realizes that flexibly high-order frequency divider easy to implement, meets high-precision requirement.Using the fpga chip for possessing DSP disposal abilities,
Applications of the DSP in audio frequency process is fully extended, and improves the parallel processing capability of traditional dsp chip.
Brief description of the drawings
Fig. 1 is the digital frequency divider module frame chart of the prior art；
Fig. 2 is the frequency division module figure of the utility model embodiment；
Fig. 3 is the frequency division module simulation result of the utility model embodiment.
Embodiment
The utility model is specifically described with reference to specific embodiment.
Fig. 2 is the utility model embodiment frequency division module block diagram.
Frequency division module is realized is divided into four road different frequency range signals by audio signal.Module support processing maximum sampling all the way
Rate is the voice data of 192kHz.
As shown in Fig. 2, frequency division module is responsible for audio signal being divided into low frequency, Low Medium Frequency, high intermediate frequency, high frequency totally four road sound
Road.Low-frequency channel is made of 3 iir filter cascades, and Low Medium Frequency sound channel is made of 6 iir filter cascades, high intermediate frequency sound channel
It is made of 6 iir filter cascades, high frequency sound channel is made of 3 iir filter cascades.
Each iir filter exponent number be second order, wave filter calculation formula be y (n)=a0* [b0*x (n)+b1*x (n-1)+
b2*x(n-2)+a1*y(n-1)+a2*y(n-2)]。
One iir filter, which completes once filtering, needs 6 multiplyings and 4 sub-addition computings.Specific calculating is as follows：
b0*x0；
b1*x1；
b0*x0+b1*x1；
b2*x2；
a1*y1；
a1*y1+b2*x2；
(a1*y1+b2*x2)+(b0*x0+b1*x1)；
a2*y2；
[(a1*y1+b2*x2)+(b0*x0+b1*x1)]+(a2*y2)；
a0*{[(a1*y1+b2*x2)+(b0*x0+b1*x1)]+(a2*y2)}.
Input audio data maximum sample rate is 192kHz, and module work clock is 50MHz, therefore voice data renewal is all
Phase is 260 work clocks, it is possible to realizes multiplication and add operation using time division multiplexing mode in specific implementation.
There are 9 sections of wave filters in module, second order IIR filter can be updated using pipeline mode in a voice data again
9 sections of wave filters are realized in cycle.
Second order IIR multiplexing temporal specifications are as follows：
Calculate 1：B0 and x0 are sent to floating-point multiplier by the 1st clock, and the 7th clock latches the result that b0 is multiplied with x0
(because floating-point multiplier time delay is arranged to 5 clocks)；
Calculate 2：B1 and x1 are sent to floating-point multiplier by the 7th clock,
Calculate 3：The result that the latch b0 latched the results being multiplied with x0 and b1 are multiplied with x1 is sent to by the 13rd clock
Floating-point adder, the 21st clock latch floating-point adder output result (because floating-point multiplier time delay is arranged to 7 clocks)；
Calculate 4：B2 and x2 are sent to floating-point multiplier by the 13rd clock, the 19th clock deposit it is that b2 is multiplied with x2 as a result,
Calculate 5：A1 and y1 are sent to floating-point multiplier by the 19th clock,
Calculate 6：The result that the b2 latched the results being multiplied with x2 and a1 are multiplied with y1 is sent to floating-point by the 25th clock
Adder；
Calculate 7：The result that floating-point adder output result and the 21st clock latch is then sent through floating by the 33rd clock
Point adder；
The result of floating add twice is sent to floating-point adder by the 47th clock, and the 55th clock latches floating-point adder
Export result；
Calculate 8：A2 and y2 are sent to floating-point multiplier by the 35th clock；
Calculate 9：The result for calculating 7 and the result for calculating 8 are sent to floating-point adder by the 41st clock.
Calculate 10：The result of a0 and calculating 9 are sent to floating-point multiplier by the 49th clock, are finally obtained in the 55th clock
Filter results.
Since above-mentioned sequential is that multiplier and adder are all serially to use when realizing 10 multiply-add calculating, then can profit
With pipeline mode come cascading multiple stages iir filter.According to sequential above, 64 clock cycle can at most realize 6 grades of cascades.
Calculated so as to complete four road signal iir filters in this frequency division module within 256 clock cycle.
Frequency division module is emulated on emulation platform QuartusII13.1+altera-modelsim.
Fig. 3 is the frequency division module simulation result of the digital frequency divider of the utility model embodiment.
Test input signal is the tone signal that a frequency is 1kHz, and filter parameter is positioned to allow for the tone signal
Exported by Low Medium Frequency section.As shown in figure 3, from the point of view of waveform, the tone signal of input only exports simulation result in Low Medium Frequency section,
Illustrate that frequency division module function is correct.
The cyclone IV family chips EP4CE11529C7 compiling frequency division modules of use site programmable gate array FPGA.
Frequency division module calculation delay is 249 operating clock cycle, that is, 4.98us.
The digital frequency divider that the utility model is related to, can change frequency divider ginseng in real time in the case where not changing hardware
Number, realizes that flexibly high-order frequency divider easy to implement, meets high-precision requirement.
Claims (3)
1. the digital frequency divider in a kind of on-site programmable gate array FPGA, which possesses frequency division module,
Audio signal is divided into low frequency, Low Medium Frequency, high intermediate frequency, high frequency totally four tunnel sound channel by the frequency division module,
The low-frequency channel is made of 3 iir digital filter cascades,
The Low Medium Frequency sound channel is made of 6 iir digital filter cascades,
The high intermediate frequency sound channel is made of 6 iir digital filter cascades,
The high frequency sound channel is made of 3 iir digital filter cascades.
2. digital frequency divider according to claim 1, the iir digital filter exponent number is second order IIR filter.
3. digital frequency divider according to claim 2, input audio data maximum sample rate is 192kHz, when module works
Clock is 50MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721280004.5U CN207268837U (en) | 2017-09-30 | 2017-09-30 | Digital frequency divider |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721280004.5U CN207268837U (en) | 2017-09-30 | 2017-09-30 | Digital frequency divider |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207268837U true CN207268837U (en) | 2018-04-24 |
Family
ID=61955062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721280004.5U Expired - Fee Related CN207268837U (en) | 2017-09-30 | 2017-09-30 | Digital frequency divider |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207268837U (en) |
-
2017
- 2017-09-30 CN CN201721280004.5U patent/CN207268837U/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102053186B (en) | Digital oscilloscope with variable-order digital filter | |
| CN103166598B (en) | Digital filter and collocation method, electronic equipment and wireless communication system | |
| CN103178815B (en) | Pulse wavelength modulation (PWM) generator based on field programmable gate array (FPGA) | |
| CN110365312B (en) | Multiphase structure of two-channel orthogonal mirror image filter bank and coefficient design method thereof | |
| CN103984560A (en) | Embedded reconfigurable system based on large-scale coarseness and processing method thereof | |
| CN110492867A (en) | A kind of interpolation filter system with digital circuit | |
| CN108832917A (en) | It is a kind of for exempting from the spread spectrum modulation technique of filtering figure D class audio frequency power amplifier | |
| Uthaya Kumar et al. | Ambient intelligence architecture of MRPM context based 12-tap further desensitized half band FIR filter for EEG signal | |
| CN207268837U (en) | Digital frequency divider | |
| Guarch et al. | An architecture for real-time arbitrary and variable sampling rate conversion with application to the processing of harmonic signals | |
| Akhter et al. | Design and analysis of distributed arithmetic based FIR filter | |
| CN207603588U (en) | Digital parametric equalizer | |
| CN202385063U (en) | Digital filter based on FPGA | |
| CN104348446A (en) | FIR filtering realization method and filtering device | |
| CN106385311A (en) | Chaotic signal generator of complex chaotic simplified system based on FPGA | |
| Coşkun et al. | FPGA Schematic Implementations and Comparison of FIR Digital Filter Structures | |
| CN104182708A (en) | Hybrid weighting type surface acoustic wave single-scale wavelet transform processor | |
| Hong et al. | Implementation of FIR filter on FPGA using DAOBC algorithm | |
| Li et al. | Application of Distributed FIR filter based on FPGA in the analyzing of ECG signal | |
| Madheswaran et al. | Implementation And Comparison Of Different CIC Filter Structure For Decimation | |
| Ketha et al. | Design & FPGA implementation of reconfigurable fir filter architecture for DSP applications | |
| CN103378821A (en) | Filter system | |
| CN104539258A (en) | Low-power-consumption digital FIR filter | |
| Wu et al. | An Innovative Experimental Project Design of Audio Equalization Processor Based on FPGA | |
| Lin et al. | An design of the 16-order FIR digital filter based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180424 |