CN104539258A - Low-power-consumption digital FIR filter - Google Patents

Abstract

The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption digital FIR filter. According to the filter, input signals and cumulative output signals can be sent to a mode judgment module for mode judgment in a cumulative mode according to the input signals and the output signals, mode switching can be conducted under the control of switching signals through a mode updating module, turn-on and turn-off of gated clock signals can be controlled according to mode control signals, and filter coefficients in a multiplying-adding operation module can be updated to achieve dynamic adjustment of the orders and the coefficients of the filter. The low-power-consumption digital FIR filter has the advantages that as to an actual voice signal, on the condition of guaranteeing completion of the filtering process, power consumption is greatly lowered, and the problem of resource waste caused by a traditional filter designed according to the worst conditions is solved. The low-power-consumption digital FIR filter is particularly suitable for the field of low-power-consumption filters.

Description

A kind of low power consumption digital FIR filter

Technical field

The present invention relates to technical field of integrated circuits, particularly a kind of low power consumption digital FIR filter realized by gated clock based on approximate calculation principle.

Background technology

A filter is in fact a system or network, and it changes the waveform of signal, amplitude versus frequency and phase-frequency characteristic selectively with the pattern that is expected.The object of general filtering is the quality in order to improve a signal, such as, say and eliminate or reduce noise, also have information extraction from signal, or former in order to effectively utilize two or more Signal separator that communication channel combines out.

Digital filter is a kind of algorithm with hardware or software simulating, and this algorithm is that object in order to reach filtering and digital input signal are carried out computing and produced digital output signal.The common effective object of digital filter is digitized analog signal (being converted to by ADC), or is stored in the number representing some variable in computer storage.

Digital filter has very important effect in DSP.In many applications (such as data compression, processing of biomedical signals, speech processes, image procossing, transfer of data, digital audio, listener's echo offsets, etc.), digital filter is compared with analog filter has a lot of advantage.The particularly linear phase characteristic that has of FIR (Finite Impulse Response) digital filter.

The structure of digital FIR filter is provided by following formula:

$H\left(z\right)=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}h\left(k\right)z^{-k}$

H (k) in formula (k=0,1 ...., N-1), be the impulse response coefficient of filter.H (z) is the transfer function of filter, and N is filter order, i.e. the number of filter coefficient.

As shown in Figure 1, the FIR filter that Direct-type structure realizes forms primarily of three parts its most basic Direct-type structure: data shift register, multiplier and multioperand adder.For a N rank FIR filter, the FIR filter that Direct-type structure realizes needs N DBMS shift register, N number of multiplier and N-1 adder altogether.

General digital filter all designs according to worst condition, and chip design is once complete, and performance index just cannot change.But the probability that the poorest this situation occurs is very low, so for practical application, will certainly cause the waste of resource.

Summary of the invention

Object of the present invention is exactly for the problems referred to above, proposes a kind of low power consumption digital FIR filter realized by gated clock based on approximate calculation principle, weighs well in power consumption and filtering performance.

Technical scheme of the present invention: a kind of low power consumption digital FIR filter, as shown in Figure 3, comprise multiply-add operation module, input accumulator module, export accumulator module, gated clock module, mode decision module, schema update module and filter coefficient update module; The input termination external signal input terminals of described input accumulator module, it exports the first input end of termination mode decision module; The input termination signal output part of described output accumulator module, it exports the second input of termination mode decision module; The input of the output termination schema update module of described mode decision module; First of described schema update module exports the 3rd input of termination mode decision module, and its second output connects the first input end of the input of gated clock module, the input of filter coefficient update module and multiply-add operation module respectively; Second input of the output termination multiply-add operation module of described gated clock module; 3rd input of the output termination multiply-add operation module of described filter coefficient update module; The four-input terminal of described multiply-add operation module connects external signal input terminals, and its output is signal output part; Wherein,

Described input accumulator module is used for adding up to multiple input signal, and the input cumulative signal obtained is input to mode decision module;

Described output accumulator module is used for adding up to multiple output signal, and the output cumulative signal obtained is input to mode decision module;

Described mode decision module is used for judging the current pattern needing to switch according to the input cumulative signal received and output cumulative signal, the concrete grammar of mode decision process is: set current input cumulative signal as X, output cumulative signal is Y, first obtain difference Z=X-Y, then difference Z is multiplied by one and obtains data ZK according to the determined Proportional coefficient K of last mode decision process, finally data ZK is compared with the multiple judgment thresholds preset, after determining the current required pattern switched, switching signal is sent to schema update module, and determine the Proportional coefficient K next time used required for mode decision process, described proportionality coefficient is preset value, the corresponding proportionality coefficient of each pattern, when described multiple judgment threshold is 2 judgment thresholds, its determination methods is, if 2 judgment thresholds are respectively U1, U2, wherein U1<U2, as ZK<U1, is judged as low-power consumption mode, as U1<ZK<U2, be judged as middle power consumption mode, as U2<ZK, be judged as high power consumption mode,

Described schema update module carries out pattern switching under the control of switching signal, mode control signal is input to respectively multiply-add operation module, mode decision module and filter coefficient update module;

Described gated clock module is used for the unlatching and the shutoff that control door controling clock signal according to mode control signal;

Described filter coefficient update module is used for the filter coefficient upgraded according to mode control signal in multiply-add operation module;

Described multiply-add operation module is used for carrying out multiply-add operation to input signal under the control of above-mentioned schema update module, gated clock module and filter coefficient update module, is exported by the signal obtained.

Beneficial effect of the present invention is, for an actual voice signal, according to the size adjustment filter order of input signal, under the condition having ensured filtering, greatly can save power consumption, solve the problem of resource waste brought according to the conventional filter of worst case design.

Accompanying drawing explanation

Fig. 1 is Direct-type FIR Filter structural representation;

Fig. 2 is gated clock structural representation;

Fig. 3 is the digital FIR filter structural representation based on approximate calculation;

Fig. 4 is the concrete control mode schematic diagram of gated clock;

Fig. 5 is overall filter workflow schematic diagram.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in detail

Suppose an input signal x [n], can be expressed as:

x[n]＝x _p[n]+x _s[n]；

Wherein x _p[n] is passband portion, namely can by the part of filter, x _s[n] is stopband portion, namely can the part that filters out of filtered device.According to calculating x _sthe size of [n], just can determine the exponent number of filter, reach and utilize minimum exponent number to complete filtering according to this value, so just can reach the object of saving power consumption.

According to adaptive filtration theory, the exponent number of approximate calculation FIR filter by adding a feedback, can upgrade according to input/output signal size in each clock cycle.Suppose that d [n] exports the difference between energy and input energy, E _x[n] is the value of input energy, E _y[n] is for exporting the value of energy.So,

d[n]＝E _x[n]-E _y[n]

$E_x\left[n\right]=\frac{1}{L}\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}{\left|x\right[n-k\left]\right|}^2$

$E_y\left[n\right]=\frac{1}{L}\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}{\left|y\right[n-k\left]\right|}^2$

Wherein x [n-k] is input signal size, and y [n-k] is output signal size, and L is a constant relevant with required computational accuracy demand.

Stopband energy size Q [n] in output signal is provided by formula below:

Q[n]＝α·d[n]·E _SB[k]

Wherein α is a proportionality coefficient, and d [n] exports the difference between energy and input energy, E _sB[k] is the stopband energy size in the filter freguency response of K rank.

According to the value of Q [n], just can determine that the stopband attenuation energy needed has much, so just can determine required filter order.

But, iff adjustment filter exponent number and do not change the coefficient of filter, the value of output signal can produce very big error, very inaccurate, to such an extent as to produces mistake.So the present invention also can adjust for filter coefficient while dynamic conditioning filter order.

As a kind of method reducing digital circuit power consumption, gated clock is not a new technology, but the advantage that gated clock possesses is but very outstanding, and area takies little, low in energy consumption, and structure is simple and be easy to control.

So-called " gate " refers to the clock that a clock signal and the non-clock signal of another one are made logic and exported.Such as, control signal "AND" clock signal is utilized, to control the onset time of clock signal.In ASIC, utilize this to reduce power consumption, because power consumption mainly consumes in the upset of transistor level, the output of gated clock, does not overturn for some time, decreases power consumption.

The simplest gated clock only needs one just can realize with door, although the simple resource occupation of structure is few, but can bring burr, also may cause metastable state.The structure that the present invention adopts as shown in Figure 3, by adding a d type flip flop, when control signal be high level simultaneously rising edge clock signal arrives time, export by d type flip flop the output that a high level serves as gated clock, solve the problems referred to above.

The concrete control mode of gated clock as shown in Figure 3, by adopting gated clock, controls the switch of shift register, thus reaches the object of adjustment filter order.

Filter construction of the present invention as shown in Figure 4, when the exponent number that exponent number update module judges required for filter is minimum, clock signal clk1 and clock signal clk2 will be closed by gated clock, and other modules namely triggered by clk1 and clk2 are also all closed.To reach the object reducing power consumption.When exponent number update module judges that exponent number required for filter is as time the highest, clk1 and clk2 can be opened by gated clock, and now filter is operated in most high power consumption state, and the filter accuracy of certain filter is also best.In like manner, when the exponent number that exponent number update module judges required for filter is medium, clk1 is unlocked, and clk2 is closed, and now energy consumption and performance of filter are all in a medium value.

As shown in Figure 5, when rising edge clock signal arrives, input signal enters multiply-add operation module and input accumulator module to the workflow of whole filter, and output signal also can enter output accumulator module simultaneously.After calculating, by input signal size accumulation result (Ein) and output signal size flower bud elder sister result (Eout) input pattern judge module.Mode decision module calculates next mode control signal (state) input pattern update module according to Ein, Eout and a upper mode control signal (state1).Schema update module, by the value of contrast state and state1, determines whether the value upgrading state1, and the value of state1 is passed to gated clock module, filter coefficient update module and multiply-add operation module.Gated clock module, according to the value of state1, determines unlatching or the shutoff of door controling clock signal clk1 and clk2.Filter coefficient update module is input in multiply-add operation module according to the value determination filter coefficient (coeff) of state1 and calculates.Multiply-add operation module, according to the value of state1, selects correct output signal to complete filtering.

A kind of Finite Impulse Response filter based on approximate calculation that the present invention introduces, emulation and synthesis result demonstrate the correctness of this design.When filter is operated in low level and filter order is lower, compared with the power consumption saving about 85% when being operated in work top step number, when to be operated in mid level and filter order be medium value, compared be operated in top step number be save about 45% power consumption.And for an actual voice signal, design of the present invention can save the power consumption of about 56%.

Claims (1)

1. a low power consumption digital FIR filter, comprises multiply-add operation module, input accumulator module, exports accumulator module, gated clock module, mode decision module, schema update module and filter coefficient update module; The input termination external signal input terminals of described input accumulator module, it exports the first input end of termination mode decision module; The input termination signal output part of described output accumulator module, it exports the second input of termination mode decision module; The input of the output termination schema update module of described mode decision module; First of described schema update module exports the 3rd input of termination mode decision module, and its second output connects the first input end of the input of gated clock module, the input of filter coefficient update module and multiply-add operation module respectively; Second input of the output termination multiply-add operation module of described gated clock module; 3rd input of the output termination multiply-add operation module of described filter coefficient update module; The four-input terminal of described multiply-add operation module connects external signal input terminals, and its output is signal output part; Wherein,

Described input accumulator module is used for adding up to multiple input signal, and the input cumulative signal obtained is input to mode decision module;

Described output accumulator module is used for adding up to multiple output signal, and the output cumulative signal obtained is input to mode decision module;

Described mode decision module is used for judging the current pattern needing to switch according to the input cumulative signal received and output cumulative signal, concrete grammar is: the difference first obtaining current input cumulative signal and output cumulative signal, then the proportionality coefficient corresponding to a pattern is multiplied by, the product obtained is compared with the threshold value preset, after determining the current required pattern switched, switching signal is sent to schema update module;

Described schema update module carries out pattern switching under the control of switching signal, mode control signal is input to respectively multiply-add operation module, mode decision module and filter coefficient update module;

Described gated clock module is used for the unlatching and the shutoff that control door controling clock signal according to mode control signal;

Described filter coefficient update module is used for the filter coefficient upgraded according to mode control signal in multiply-add operation module;

Described multiply-add operation module is used for carrying out multiply-add operation to input signal under the control of above-mentioned schema update module, gated clock module and filter coefficient update module, is exported by the signal obtained.