CN207602196U - A kind of source drive unit, source electrode drive circuit, display device - Google Patents
A kind of source drive unit, source electrode drive circuit, display device Download PDFInfo
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Abstract
Embodiments herein provides a kind of source drive unit, source electrode drive circuit, display device, is related to display technology field, solves the problems, such as there is residual data signal on data line.The source drive unit includes shift register subelement and latches subelement.The latch subelement includes reseting module and at least level-one latch module；Latch module is connected with shift register subelement, data signal end；Latch module is used under the control of shift register subelement output signal, and the data-signal of data signal end output is latched, and data-signal is exported to data line；Reseting module is connected with enable signal end, reset signal end, latch module, and reseting module is used under the control at enable signal end, and the data-signal latched by reset signal end to latch module resets.The source drive unit is used to provide data-signal to data line.
Description
Technical field
The utility model is related to display technology field more particularly to a kind of source drive unit, source electrode drive circuit, displays
Device.
Background technology
(Thin Film Transistor Liquid Crystal Display, Thin Film Transistors-LCD are shown TFT-LCD
Show device) alternatively, Organic Light Emitting Diode (Organic Light Emitting Diode, OLED) display as a kind of tablet
Display device, because it has the characteristics that small, low in energy consumption, radiationless and cost of manufacture is relatively low, and more and more
It is applied in high-performance display field.
The grid line and data line of transverse and longitudinal intersection are provided on the display panel of any one above-mentioned display.Grid line is opened line by line
Open sub-pix.When a line sub-pix is opened, data line is filled with data-signal to the sub-pix of the unlatching, when all sub-pixes are equal
After receiving above-mentioned data-signal, which shows a frame picture.However, when a line sub-pix receives number by data line
It is believed that number when, if also remaining the data-signal of lastrow sub-pix on the data line, then the row sub-pix will be caused
Data-signal can not be correctly written in, cause display abnormal.
Utility model content
Embodiments herein provides a kind of source drive unit, source electrode drive circuit, display device, solves on data line
The problem of with residual data signal.
In order to achieve the above objectives, the embodiment of the utility model adopts the following technical scheme that：
The one side of the embodiment of the present application provides a kind of source drive unit, including shift register subelement and latch
Subelement；The latch subelement includes reseting module and at least level-one latch module；The latch module is posted with the displacement
Storage subelement, data signal end are connected；The latch module is used in the shift register subelement output signal
Under control, the data-signal of data signal end output is latched, and the data-signal is exported to data line；Institute
It states reseting module with enable signal end, reset signal end, the latch module to be connected, the reseting module is used to make described
Under the control of energy signal end, the data-signal latched by the reset signal end to the latch module resets.
Optionally, at least level-one latch module includes first order latch module, second level latch module；Described first
Grade latch module is connected with the shift register subelement, the data signal end and the second level latch module；
The first order latch module is used under the control of the shift register subelement output signal, to the data signal end
The data-signal of output is latched, and the data-signal is exported to the second level latch module；The second level lock
The data-signal that storing module is used to export the first order latch module latches, and exports the number to the data line
It is believed that number；The reseting module is connected with the first order latch module or the second level latch module.
Optionally, the reseting module includes reset transistor；The grid of the reset transistor connects the enabled letter
Number end, the first pole connects the reset signal end, the second pole and the first order latch module or the second level latch module
It is connected.
Optionally, the first order latch module includes the first transmission submodule and the first latch submodule；Described first
First control signal end, the data signal end and the first latch for transmitting submodule and the shift register subelement save
Point is connected；The first transmission submodule is used for the control at the first control signal end of the shift register subelement
Under, the signal transmission of the data signal end to described first is latched into node；Described first latches submodule connection described the
One latches the second control signal end of node, the second level latch module and the shift register subelement；Described
One, which latches submodule, is used under the control at the second control signal end of the shift register subelement, is latched to described first
The data-signal of node is latched, and is exported to the second level latch module.
Optionally, the second level latch module includes the second transmission submodule and the second latch submodule；Described second
It transmits submodule and connects the first order latch module, the first open signal end and the second latch node；Second transmission
Submodule is used under the control at the first open signal end, the data signal transmission that the first order latch module is exported
Node is latched to described second；Described second, which latches submodule connection described second, latches node, the second open signal end,
Described second, which latches submodule, is used under the control at the second open signal end, and the data that node is latched to described second are believed
It number is latched, and the data-signal is exported.
Optionally, the first transmission submodule includes the first transmission gate；The input terminal of first transmission gate with it is described
Data signal end is connected, and the first control terminal and the second control terminal are believed respectively with the first control of the shift register subelement
Number end is connected with second control signal end, and output terminal is connected with the described first latch node.
Optionally, the first latch submodule includes the second transmission gate, the first phase inverter, the second phase inverter and third
Phase inverter；The input terminal of second transmission gate connects the output terminal of the third phase inverter, the first control terminal and the second control
End is connected respectively with the first control signal end of the shift register subelement and second control signal end, output terminal and institute
The first latch node is stated to be connected；The input terminal of first phase inverter with described first latch node be connected, output terminal with
The third phase inverter is connected with the input terminal of second phase inverter；The output terminal connection described the of second phase inverter
Two level latch module.
It is further alternative, it is connected in the reseting module with the first order latch module, and the reseting module
In the case of including reset transistor, the second pole of the reset transistor is connected with the input terminal of first phase inverter；
The reset signal end being connected with the first pole of the reset transistor is first voltage end；Alternatively, the reset transistor
Second pole is connected with the output terminal of first phase inverter；The reset signal being connected with the first pole of the reset transistor
It holds as second voltage end.
Optionally, the second transmission submodule includes third transmission gate；The input terminal of the third transmission gate with it is described
First order latch module is connected, the first control terminal and the second control terminal respectively with the first open signal end and the second open signal
End is connected, and output terminal is connected with the described second latch node.
Optionally, the second latch submodule includes the 4th transmission gate, the 4th phase inverter, the 5th phase inverter and the 6th
Phase inverter；The first control terminal and the second control terminal of 4th transmission gate are opened respectively with the first open signal end and second to be believed
Number end is connected, and input terminal is connected with the output terminal of the 5th phase inverter, and output terminal is connected with the described second latch node
It connects；Alternatively, the input terminal of the 4th transmission gate is connected with the output terminal of the 4th phase inverter, output terminal and the described 5th
The input terminal of phase inverter is connected；The output terminal of 4th phase inverter and the input terminal and the described 6th of the 5th phase inverter
The input terminal of phase inverter is connected；Output terminal of the output terminal of the hex inverter as the second level latch module.
It is further alternative, it is connected in the reseting module with the second level latch module, and the reseting module
In the case of including reset transistor, the second pole of the reset transistor is connected with the input terminal of the 4th phase inverter；
The reset signal end being connected with the first pole of the reset transistor is first voltage end；Alternatively, the reset transistor
Second pole is connected with the output terminal of the 4th phase inverter；The reset signal being connected with the first pole of the reset transistor
It holds as second voltage end.
Optionally, the latch subelement further includes buffer module, and the buffer module includes the 7th phase inverter and the 8th
Phase inverter；The input terminal of 7th phase inverter is connected with the output terminal of the second level latch module, output terminal with it is described
The input terminal of 8th phase inverter is connected；Output terminal of the output terminal of 8th phase inverter as the source drive unit.
The another aspect of the embodiment of the present application provides a kind of source electrode drive circuit, including multiple arranged side by side upper described
Any one source drive unit；Shift register subelement in multiple source drive units cascades successively.
The another aspect of the embodiment of the present application, provides a kind of display device, including host driver and source as described above
Pole driving circuit, the host driver are connected by data signal end with source drive unit.
Embodiments herein provides a kind of source drive unit, source electrode drive circuit, display device.The source drive list
Reseting module in member is used under the control at the enable signal end, the number latched by reset signal end to level-one latch module
It is believed that number being resetted.Based on this, it can be seen from the above, the output terminal of level-one latch module may act as above-mentioned source drive list
The output terminal of member is connected with above-mentioned data line.Therefore, when the source drive unit is needed to coupled data line biography
It, can be by the reseting module in the source drive unit to above-mentioned latch module before the data-signal of defeated next line sub-pix
After the data-signal of middle latch is resetted, remaining upper one on the data line so as to which the output terminal with latch module be connected
The data-signal of row sub-pix is purged so that the data-signal of next line sub-pix can be correctly written in, and be solved with reaching
There is the problem of residual data signal on data line.In addition, the data-signal remained on data line can cause display device to exist
There is ghost during display or after booting.In the case, since the source drive unit that the application provides can solve
Certainly on data line there is the problem of residual data signal, therefore can reach and reduce above-mentioned ghost phenomena odds.
Description of the drawings
It in order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is a kind of structure diagram of source drive unit provided by the embodiments of the present application；
Fig. 2 is the structure diagram of another source drive unit provided by the embodiments of the present application；
Fig. 3 is a kind of concrete structure schematic diagram of modules in Fig. 2；
Fig. 4 is a kind of concrete structure schematic diagram of modules in Fig. 1；
Fig. 5 is another concrete structure schematic diagram of modules in Fig. 2；
Fig. 6 is another concrete structure schematic diagram of modules in Fig. 1；
Fig. 7 is a kind of signal timing diagram provided by the embodiments of the present application；
Fig. 8 is a kind of structure diagram of source electrode drive circuit provided by the embodiments of the present application；
Fig. 9 is another signal timing diagram provided by the embodiments of the present application；
Figure 10 is a kind of driving method flow chart of source drive unit provided by the embodiments of the present application.
Reference numeral：
01- source drive units；10- shift register subelements；20- latches subelement；201- first order latch modules；
210- first transmits submodule；211- first latches submodule；202- second level latch module；220- second transmits submodule；
221- second latches submodule；203- reseting modules；204- buffer modules.
Specific embodiment
The following is a combination of the drawings in the embodiments of the present utility model, and the technical scheme in the embodiment of the utility model is carried out
It clearly and completely describes, it is clear that the described embodiments are only a part of the embodiments of the utility model rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are without making creative work
All other embodiments obtained shall fall within the protection scope of the present invention.
Hereinafter, term " first ", " second " are only used for description purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the embodiment of the present application, unless otherwise indicated, " multiples' " contains
Justice is two or more.
Current mobile display device, such as the size of mobile phone are smaller.In the case, the capacity of battery is relatively low.Cause
This user needs frequently to charge to mobile phone during use, so as to reduce user experience.In order to solve above-mentioned ask
Topic, may be used the technology of MIP (Memory In Pixel, memory are integrated in sub-pix), and electricity is kept to improve sub-pix
The ability of pressure.So, when showing tableaux, the refreshing frequency of display device can be reduced, reaching reduces product work(
Consumption, saves purpose a little.
For the display device using MIP technologies, source driving chip (Source IC) may be used, data line is carried out
Driving, alternatively, the source drive unit 01 of the offer of the application may be used.The source drive unit (H Driver) 01, such as
Include shift register subelement 10 shown in Fig. 1 or Fig. 2 and latch subelement 20.
The display panel for being provided with above-mentioned source drive unit 01 includes display area and positioned at the display area periphery
Non-display area.Above-mentioned source drive unit 01 is set to non-display area, and transverse and longitudinal intersection is provided in the display area
Grid line (Gate Line, GL) and data line (Data Line, DL).Wherein, the output terminal of the source drive unit 01 with it is upper
Data line DL is stated to be connected.
On this basis, which includes reseting module 203 and at least level-one latches (Latch) module.Its
In, at least level-one latch module can include first order latch module 201 as shown in Figure 1, second level latch module 202 for this.
Wherein, above-mentioned first order latch module 201 and shift register subelement 10, data signal end Data and second
Grade latch module 202 is connected.
The first order latch module 201 be used under the control of 10 output signal of shift register subelement, logarithm it is believed that
Number end Data output data-signal latched, and data-signal is exported to second level latch module 202.
Above-mentioned second level latch module 202 is connected with data line DL, which is used for the first order
The data-signal that latch module 201 exports is latched, and to data line DL outputting data signals.
In the case, since second level latch module 202 is connected with data line DL, the second level latch module
202 output terminal may act as the output terminal of above-mentioned source drive unit 01.
It should be noted that with the continuous promotion of display device resolution ratio, the quantity of data line DL on display panel
It greatly increases, in the case, in order to save the wiring space of above-mentioned non-display area, above-mentioned source drive unit 01 can be with
Multiple data lines DL is connected.Based on this, in order to ensure the multiple data lines DL being connected with same source drive unit 01
Correct data-signal can be received, the shift register subelement 10 in the source drive unit 01 can be to the first order
Latch module 201 output control signal so that second level latch module 202 can under the control of above-mentioned control signal, by
One to the corresponding data-signal of pieces of data line output being connected with the second level latch module 202.
In addition, as shown in Fig. 2, above-mentioned reseting module 203 and enable signal end EN, reset signal end RST, the first order latch
Module 201 is connected.The reseting module 203 is used under the control of enable signal end EN, by reset signal end RST to first
The data-signal that grade latch module 201 latches is resetted.
Alternatively, as shown in Figure 1, reseting module 203 and enable signal end EN, reset signal end RST, second level latch module
202 are connected.The reseting module 203 is used under the control of enable signal end EN, and the second level is locked by reset signal end RST
The data-signal that storing module 202 latches is resetted.
Wherein, optionally, above-mentioned reseting module 203, as shown in figure 3, including reset transistor M0.Reset transistor M0
Grid connection enable signal end EN, the first pole connection reset signal end RST, second extremely latches mould with the first order as shown in Figure 3
Block 201 is connected.Alternatively, as shown in figure 4, the second pole of above-mentioned reset transistor M0 is connected with second level latch module 202.
It should be noted that above-mentioned reseting module 203 can also include the reset transistor M0 of multiple parallel connections.
In addition, reset transistor M0 can be N-type transistor or P-type transistor, the application does not limit this.In order to
It is convenient, below by reset transistor M0 to be illustrated for N-type transistor.In addition, the first of above-mentioned reset transistor M0
Can be extremely source electrode, second extremely drains；Or first extremely drain, the second extremely source electrode.
In conclusion reseting module 203 is used under the control of enable signal end EN, by RST pairs of reset signal end
The data-signal that first order latch module 201 latches is resetted.Alternatively, the reseting module 203 is used in enable signal end EN
Control under, to second level latch module 202 latch data-signal reset.
Based on this, it can be seen from the above, first order latch module 201 is connected with second level latch module 202, and the second level
The output terminal that the output terminal of latch module 202 may act as above-mentioned source drive unit 01 is connected with above-mentioned data line DL.
Therefore, when the source drive unit 01 need to coupled data line DL transmission next line sub-pix data-signal it
Before, it can be by the reseting module 203 in the source drive unit 01 to first order latch module 201 or second level latch module
After the data-signal of middle latch is resetted, the data line so as to be connected with the output terminal of the second level latch module 202
The data-signal of the upper remaining lastrow sub-pixes of DL is purged so that the data-signal of next line sub-pix can correctly be write
Enter, solve the problems, such as that there is residual data signal on data line DL to reach.
In addition, the data-signal remained on data line DL can cause display device during the display or booting after
There is ghost.In the case, since the source drive unit 01 that the application provides can solve have residual on data line DL
The problem of data-signal, therefore can reach and reduce above-mentioned ghost phenomena odds.
Below to first order latch module 201, second level latch module 202 and the reset in above-mentioned latch subelement 20
The concrete structure of module 203 is described in detail.
Specifically, as shown in figure 3, above-mentioned first order latch module 201 includes the first transmission latch of submodule 210 and first
Submodule 211.
Wherein, the first control signal end S of the first transmission submodule 210 and shift register subelement 10 is (or such as Fig. 4
Shown, with the first control signal end S of shift register subelement 10 and second control signal end S '), data signal end Data
And first latch node Q be connected.
It should be noted that the first control signal end S of the shift register subelement 10 and second control signal end S '
The signal of output is opposite.
The first transmission submodule 210 is used at least in the control of the first control signal end S of shift register subelement 10
Under system, the signal transmission of data signal end Data to first is latched into node Q.
On this basis, first first latch node of the connection of submodule 211 Q, second level latch module 202 is latched and is moved
Bit register subelement 10 second control signal end S ' (or as shown in figure 4, shift register subelement 10 first control
Signal end S and second control signal end S ').
First, which latches submodule 211, is used at least in the control of the second control signal end S ' of shift register subelement 10
Under, the data-signal of the first latch node Q is latched, and export to second level latch module 202.
In addition, above-mentioned second level latch module 202, includes the second transmission submodule 220 and second and latches son as shown in Figure 3
Module 221.
Wherein, the second transmission submodule 220 connects first order latch module 201, the first open signal end SW1 (alternatively, such as
First open signal end SW1 shown in Fig. 4 and the second open signal end SW2) and the second latch node P.
The second transmission submodule 220 is used at least under the control of the first open signal end SW1, and the first order is latched mould
The data signal transmission that block 201 exports latches node P to second.
On this basis, second latch the connection of submodule 221 second latch node P, the second open signal end SW2 (alternatively,
First open signal end SW1 as shown in Figure 4 and the second open signal end SW2),
Second, which latches submodule 221, is used at least under the control of the second open signal end SW2, and node P is latched to second
Data-signal latched, and data-signal is exported.
Submodule 211 is latched to the first transmission submodule 210 and first in above-mentioned first order latch module 201 below
Structure is described in detail.
Specifically, the first transmission submodule 210, as shown in figure 3, including the first transmission transistor T1 '.First transmission
The first control signal end S of the grid connection shift register subelement 10 of transistor T1 ', the first pole connection data signal end
Data, the second pole are connected with the first latch node Q.
Under the control of the first control signal end S of shift register subelement 10, when the first transmission transistor T1 ' is connected
When, the data-signal of data signal end Data outputs, which can be exported by first transmission transistor T1 ' to above-mentioned first, to latch
Node Q.
Alternatively, in the first transmission submodule 210 and the controls of the first control signal end S of shift register subelement 10 and second
In the case that signal end S ' processed is all connected with, above-mentioned first transmission submodule 210 is as shown in figure 4, including the first transmission gate T1.This
The input terminal of one transmission gate is connected with data signal end Data, the first control terminal and the second control terminal respectively with shift register
The first control signal end S of subelement 10 is connected with second control signal end S ', and output terminal is connected with the first latch node Q
It connects.
Wherein, above-mentioned first transmission gate T1 is made of two transistors, and one of transistor is N-type transistor, another
A transistor is P-type transistor.In the first control signal end S and second control signal end S ' of shift register subelement 10
Under controlling respectively, during two transistor turns in above-mentioned first transmission gate T1, the data-signal of data signal end Data outputs
It can be exported by first transmission gate T1 to above-mentioned first and latch node Q.
On this basis, it above-mentioned first latches submodule 211 and includes the second transmission gate T2 as shown in Figure 4 (or such as Fig. 3
The second shown transmission transistor T2 '), the first phase inverter Inv1, the second phase inverter Inv2 and third phase inverter Inv3.
Wherein, the output terminal of the input terminal connection third phase inverter Inv3 of the second transmission gate T2, the first control terminal and second
Control terminal is connected respectively with the first control signal end S of shift register subelement 10 and second control signal end S ', output
End is connected with the first latch node Inv1.
In the case that first latches submodule 211 including the second transmission transistor T2 as shown in Figure 3, the second transmission is brilliant
The connection mode of body pipe T2 is as shown in figure 3, details are not described herein again.
In addition, as shown in figure 4, the input terminal of the first phase inverter Inv1 is connected with the first latch node Q, output terminal and the
The input terminal of three phase inverter Inv3 and the second phase inverter Inv2 are connected.
The output terminal connection second level latch module 202 of second phase inverter Inv2.
It can be seen from the above, as shown in figure 4, first order latch module 201 is by two transmission gates (T1, T2) and three reverse phases
Device (Inv1, Inv2, Inv3) is formed, therefore simple in structure, and the wiring space of occupancy is small.
Based on this, in reseting module 203 as shown in figure 3, being connected with first order latch module 201, and the reseting module
In the case that 203 include reset transistor M0,
The second pole of above-mentioned reset transistor M0 is connected with the input terminal of the first phase inverter Inv1；With the reset transistor
The reset signal end that the first pole of M0 is connected is first voltage end VGL.
Wherein, first voltage end VGL exports low level.It so, can be by multiple after reset transistor M0 is connected
Signal on first latch node Q is pulled down to first voltage end VGL by bit transistor M0, so as to latch node Q lockings by first
The data-signal deposited is removed.
Alternatively, the connection mode of above-mentioned reset transistor M0 can be with as shown in figure 5, the second pole of reset transistor M0
It is connected with the output terminal of the first phase inverter Inv1.The reset signal end RST being connected with the first pole of reset transistor M0
For second voltage end VGH.
Wherein, second voltage end VGH exports high level.So, by reset transistor M0 by the first phase inverter
The output terminal of Inv1 is pulled to second voltage end VGH, since the output terminal of the first phase inverter Inv1 is high level, in third reverse phase
Under the action of device Inv3, the current potential of node Q is input to as low level by the second transmission gate T2, in the case, with this first
The current potential of the first latch node Q that the input terminal of phase inverter Inv1 is connected is pulled low, so as to be latched on the first latch node Q
Data-signal remove.
It should be noted that when above-mentioned latch subelement 20 includes level-one latch module, which posts with displacement
Storage subelement 10, data signal end Data are connected.The latch module is used in 10 output signal of shift register subelement
Control under, to data signal end output Data data-signal latch, and data-signal is exported to data line DL.
In this case, the structure of first order latch module 201 as shown in figure 3 or 4, the i.e. lock may be used in above-mentioned level-one latch module
Storing module includes the first transmission gate T1 (either the first transmission transistor T1 '), the second transmission gate T2 (or the second transmission transistors
T2 '), the first phase inverter Inv1, the second phase inverter Inv2 and third phase inverter Inv3.Based on this, above-mentioned reset transistor M0
The output terminal or input terminal of the first phase inverter Inv1 can be connected.
Submodule 221 is latched to the second transmission submodule 220 and second in above-mentioned second level latch module 202 below
Structure is described in detail.
The second transmission submodule 220 is as shown in figure 3, including third transmission transistor T3 '.Or include as shown in Figure 4
Third transmission gate T3.The input terminal of third transmission gate T3 is connected with first order latch module 201, the first control terminal and second
Control terminal is connected respectively with the first open signal end SW1 and the second open signal end SW2, and output terminal and second latches node P
It is connected.
On this basis, it second latches submodule 221 and includes the 4th transmission gate T4 (or the as shown in Figure 3 the 4th transmission
Transistor T4 '), the 4th phase inverter Inv4, the 5th phase inverter Inv5 and hex inverter Inv6.
The first control terminal and the second control terminal of 4th transmission gate T4 is opened respectively with the first open signal end SW1 and second
It opens signal end SW2 to be connected, input terminal is connected with the output terminal of the 5th phase inverter Inv5, and output terminal and second latches node P
It is connected.
Alternatively, the set-up mode of above-mentioned 4th transmission gate T4 is also possible that as shown in fig. 6, the input of the 4th transmission gate T4
End is connected with the output terminal of the 4th phase inverter Inv4, and output terminal is connected with the input terminal of the 5th phase inverter Inv5.
Based on this, in the case where the 4th transmission gate T4 is using above-mentioned connection mode, when first order latch module 201 will lock
When the data-signal deposited is transmitted to the second latch node P by the third transmission gate T3 in second level latch module 202, Ke Yitong
Crossing the first open signal end SW1 and the second open signal end SW2 controls the 4th transmission gate T4 to close, at this time second latch node P,
4th phase inverter Inv4, the 5th phase inverter Inv5 and the 4th transmission gate T4 can not form phaselocked loop (P → Inv4 → Inv5 → T4
→P).In the case, even if the driving force of third transmission gate T3 and the 4th transmission gate T4 are insufficient, first latches on node Q
Data-signal can also be transmitted to the second latch node P.
So, on the one hand, data can be transmitted to second level latch module 202 to avoid first order latch module 201
When, data-signal is caused not input normally due to the presence of above-mentioned phaselocked loop, so that second latches the signal of node P
Occur as shown in Figure 7 abnormal (at A).Further, since first order latch module 201 transmits data to second level latch module 202
When, above-mentioned phaselocked loop will not be formed, therefore to third transmission gate T3's and the 4th transmission gate T4 inside second level latch module 202
Driving force it is of less demanding, so the size of third transmission gate T3 and the 4th transmission gate T4 are conducive to reduce without increase
Occupy the area of wiring space.
In addition, after the data signal transmission latched on node Q when first latches node P to second, first can be passed through
Open signal end SW1 and the second open signal end SW2 control third transmission gates T3 is closed, and the 4th transmission gate T4 is opened, so as to
Form above-mentioned phaselocked loop (P → Inv4 → Inv5 → T4 → P) so that data-signal is latching to the second level latch module 202
It is interior.
In addition, as shown in figure 4, the output terminal of above-mentioned 4th phase inverter Inv4 and the input terminal of the 5th phase inverter Inv5 and
The input terminal of hex inverter Inv6 is connected.
Output terminal of the output terminal of hex inverter Inv6 as the second level latch module 202.
Based on this, it is connected in above-mentioned reseting module 203 with second level latch module 202, and reseting module 203 is included again
In the case of bit transistor M0,
As shown in figure 4, the second pole of reset transistor M0 is connected with the input terminal of the 4th phase inverter Inv4.And with answering
The reset signal end RST that the first pole of bit transistor M0 is connected is first voltage end VGL.
After reset transistor M0 is connected, can the signal on node P be latched by second by reset transistor M0 and pulled down
To first voltage end VGL, so as to which the data-signal latched on the second latch node P be removed.Due to belonging to the second latch node P
Second level latch module 202 be connected with data line DL, therefore to the data-signal latched on the second latch node P is clear
During removing, remaining data-signal on data line DL can also be purged, without inputting black picture line by line
Corresponding data-signal reaches the purpose that repid discharge is carried out to AA (Active Area, effective display area) area.It and then can
Display device is avoided image retention occur during booting or normal display.
Alternatively, the second pole of reset transistor M0 is connected with the output terminal of the 4th phase inverter Inv4.At this point, with the reset
The reset signal end RST that the first pole of transistor M0 is connected is second voltage end VGH.
So, the output terminal of the 4th phase inverter Inv4 is pulled to by second voltage end VGH by reset transistor M0,
Since the output terminal of the 4th phase inverter Inv4 is high level, under the action of the 5th phase inverter Inv5, pass through the 4th transmission gate T4
The current potential for being input to node P is low level, in the case, the second lock being connected with the input terminal of the 4th phase inverter Inv4
The current potential for depositing node P is pulled low, so as to which the data-signal latched on the second latch node P be removed.In addition, when the 4th phase inverter
The output terminal of Inv4 be high level when, pass through the acting in opposition of hex inverter Inv6 so that the second level latch module 202 to
Data line DL exports low level, and to be purged to remaining signal on data line DL, being finally reached prevents from having on data line DL
There is signal residual, and realize the purpose of AA area's repid discharges.
It should be noted that when above-mentioned latch subelement 20 includes level-one latch module, which may be used
The structure of second level latch module 202 as shown in figure 3 or 4, the i.e. latch module include third transmission gate T3 (or third pass
Defeated transistor T3 '), the 4th transmission gate T4 (or the 4th transmission transistor T4 '), the 4th phase inverter Inv4, the 5th phase inverter
Inv5 and hex inverter Inv6.In the case, above-mentioned reset transistor M0 can connect the defeated of the 4th phase inverter Inv4
Outlet or input terminal.
In the case, when above-mentioned level-one latch module is second level latch module 202, in order to enable the latch module
It is connected with shift register subelement 10, data signal end Data, the input terminal connection data letter of above-mentioned third transmission gate T3
Number end Data.First open signal end SW1 and the second open signal end SW2 is controlled respectively with the first of shift register subelement 10
Signal end S processed is connected with second control signal end S '.
On this basis, as shown in fig. 6, the latch subelement 20 further includes buffer module 204.The buffer module 204 is wrapped
Include the 7th phase inverter Inv7 and the 8th phase inverter Inv8.The buffer module 204 is used for the number exported to second level latch module 202
It is believed that number into row buffering.
Wherein, the input terminal of the 7th phase inverter Inv7 is connected with the output terminal of second level latch module 202, output terminal with
The input terminal of 8th phase inverter Inv8 is connected.
Output terminal of the output terminal of 8th phase inverter Inv8 as source drive unit 01.8th phase inverter Inv8 at this time
Output terminal can be connected with data line DL.
The embodiment of the present application provides a kind of source electrode drive circuit, as shown in figure 8, including multiple arranged side by side as described above
Any one source drive unit 01.Wherein, the shift register subelement 10 in multiple source drive units cascades successively.
The source electrode drive circuit has the technique effect identical with the source drive unit 01 that previous embodiment provides, herein
It repeats no more.
It should be noted that the letter that wherein the first control signal output terminal S of level-one shift register subelement 10 is exported
Number as shown in figure 9, the upper level shift register subelement 10 of the shift register subelement 10 first control signal output
The signal that S is exported is held as S (n-1), the signal of the first control signal output terminal S outputs of next stage shift register subelement 10
For S (n+1).
The embodiment of the present application provides a kind of display device and includes host driver (not shown) and source as described above
Pole driving circuit, the host driver are connected by data signal end Data with the source drive unit 01.Above-mentioned display dress
It puts with the technique effect identical with the volume source electrode drive circuit that previous embodiment provides, details are not described herein again.
It should be noted that in the utility model embodiment, display device specifically can at least include liquid crystal display and fill
It puts and organic LED display device, such as the display device can be display, TV, Digital Frame, mobile phone or flat
Any product or component with display function such as plate computer.
The embodiment of the present application provides a kind of method for being used to drive any one source drive unit 01 as described above,
In the case that at least level-one latch module includes first order latch module 201 and second level latch module 202, as shown in Figure 10,
The above method includes：
S101, reseting module 203 are under the control of enable signal end EN, to the data of the latch of first order latch module 201
Signal (as shown in Figure 2) as shown in Figure 1, resets the data-signal of the latch of second level latch module 202.
Specifically, for example, above-mentioned reseting module 203 include reset transistor M0 in the case of, above-mentioned steps S101 packets
It includes：As shown in figure 3, enable signal end EN control reset transistor M0 conductings, the signal of reset signal end RST is by resetting crystal
Pipe M0 is exported to first order latch module 203.
Wherein, the input terminal phase that the second of above-mentioned reset transistor M0 extremely can as shown in Figure 3 with the first phase inverter Inv1
Connection, above-mentioned reset signal end RST is first voltage end VGL at this time.Alternatively, as shown in figure 5, the of above-mentioned reset transistor M0
Two can extremely be connected with the output terminal of the first phase inverter Inv1, and above-mentioned reset signal end RST is second voltage end VGH at this time.
It is removed in this case, it is possible to latch the data-signal on node Q by first by reset signal end RST.Specifically locked to first
Process that the data-signal on node Q is purged is deposited as described above, details are not described herein again.
Alternatively, in another example, in the case where above-mentioned reseting module 203 includes reset transistor M0, above-mentioned steps S101 packets
It includes：As shown in figure 4, enable signal end EN control reset transistor M0 conductings, the signal of reset signal end RST is by resetting crystal
Pipe M0 is exported to second level latch module 202.
Wherein, the input terminal phase that the second of above-mentioned reset transistor M0 extremely can as shown in Figure 4 with the 4th phase inverter Inv4
Connection, above-mentioned reset signal end RST is first voltage end VGL at this time.Alternatively, as shown in fig. 6, the of above-mentioned reset transistor M0
Two can extremely be connected with the output terminal of the 4th phase inverter Inv4, and above-mentioned reset signal end RST is second voltage end VGH at this time.
It is removed in this case, it is possible to latch the data-signal on node P by second by reset signal end RST.Specifically locked to second
Process that the data-signal on node P is purged is deposited as described above, details are not described herein again.
On this basis, (include first stage P1, second stage P2, phase III as shown in Figure 9 in a drive cycle
P3 and fourth stage P4) in, the above method further includes：
S102, first order latch module 202 under the control of 10 output signal of shift register subelement (S and S '),
The data-signal of data signal end Data outputs is latched.
First, P1, the first control signal end S of shift register subelement 10 export high level in the first stage, the
Two control signal end S ' export low level.At this time as shown in figure 4, the first transmission gate T1 is opened, the second transmission gate T2 is closed, data
The data-signal (being illustrated in figure 9 high level) of signal end Data outputs is transmitted to the first latch node by the first transmission gate T1
Q。
In addition, the first open signal end SW1 exports low level, the second open signal end SW2 output high level, third transmission
Door T3 is closed.Data-signal on first latch node Q can not be transmitted to the second latch node P.
Therefore, above-mentioned first stage P1 is data signal end Data by data signal transmission to first order latch module 201
Stage.
On this basis, low electricity is exported in the second moment T2, the first control signal end S of shift register subelement 10
It is flat, second control signal end S ' output high level.First transmission gate T1 is closed, and the second transmission gate T2 is opened, third transmission gate
T3 is remained off.At this point, first latches node Q, the first reverser Inv1, third phase inverter Inv3 and the second transmission gate
T2 forms phaselocked loop (Q → Inv1 → Inv3 → T2 → Q), so as to which data signal end Data is transmitted to the first order latch module
201 data-signal is latched.
Therefore, above-mentioned second stage P2 is the latch data signals that data signal end Data is transmitted to first order latch module
201 stage.
S103, first order latch module 201 export data-signal to second level latch module 202.
Specifically, in phase III P3 as shown in Figure 9, the first open signal end SW1 output high level, second opens letter
Number end SW2 output low level, at this time third transmission gate T3 open, the 4th transmission gate T4 close.First latches the data on node Q
Signal is transmitted to the second latch node P by third transmission gate T3.
Since the 4th transmission gate T4 is closed at this time, second node P, the 4th phase inverter Inv4, the 5th phase inverter are latched at this time
Inv5 and the 4th transmission gate T4 can not form phaselocked loop (P → Inv4 → Inv5 → T4 → P).In the case, even if third
The driving force of transmission gate T3 and the 4th transmission gate T4 are insufficient, and the data-signal on the first latch node Q can also be transmitted to the
Two latch node P.
So above-mentioned phase III P3 is first order latch module 201 by data signal transmission to second level latch module
202 stage.
The data-signal that S104, second level latch module 202 export first order latch module 201 latches.
Specifically, in fourth stage P4, the first open signal end SW1 output low level as shown in Figure 9, second opens letter
Number end SW2 output high level, at this time third transmission gate T3 close, the 4th transmission gate T4 open.At this point, first latch reception Q to
Second latches the data-transmission interruptions of node P.Further, since the 4th transmission gate T4 is opened, so that the second latch node P,
4th phase inverter Inv4, the 5th phase inverter Inv5 and the 4th transmission gate T4 formed phaselocked loop (P → Inv4 → Inv5 → T4 →
P), latched so as to which first order latch module 201 to be transmitted to the data-signal of the second level latch module 202.
So the data that above-mentioned fourth stage P4, which is second level latch module 202, exports first order latch module 201 are believed
Number stage latched.
S105, second level latch module 202 export the data-signal of latch to data line DL.
When the grid line GL on display panel is opened line by line, second level latch module 202 passes through the data-signal of latch
The output of buffer module 204 is to the data line DL that is connected with the source drive unit 01, so as to pair be connected with data line DL
Sub-pix charge.
It should be noted that when being provided with two-stage latch module, i.e. first order latch module in the source drive unit 01
201 and second level latch module 202 after, first order latch module 201 can store the data-signal of previous row sub-pix, and
Two level latch module 202 can store the data-signal of next line sub-pix, so as to improve the efficiency of data-signal write-in.
In addition, the charging time of the first row sub-pix is long, the charging time of last column sub-pix is short, by the way that above-mentioned two-stage is set to latch
Module can reduce the difference in the first row sub-pix and last column sub-pix charging time.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above method embodiment can pass through
The relevant hardware of program instruction is completed, and aforementioned program can be stored in a computer read/write memory medium, the program
When being executed, step including the steps of the foregoing method embodiments is performed；And aforementioned storage medium includes：ROM, RAM, magnetic disc or light
The various media that can store program code such as disk.
The above, only specific embodiment of the present utility model, but the scope of protection of the utility model is not limited to
In this, in the technical scope that any one skilled in the art discloses in the utility model, variation can be readily occurred in
Or replace, it should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model should be with the power
Subject to the protection domain of profit requirement.
Claims (14)
1. a kind of source drive unit, which is characterized in that including shift register subelement and latch subelement；
The latch subelement includes reseting module and at least level-one latch module；
The latch module is connected with the shift register subelement, data signal end；The latch module is used in institute
Under the control for stating shift register subelement output signal, the data-signal of data signal end output is latched, and
The data-signal is exported to data line；
The reseting module is connected with enable signal end, reset signal end, the latch module, and the reseting module is used for
Under the control at the enable signal end, the data-signal latched by the reset signal end to the latch module is answered
Position.
2. source drive unit according to claim 1, which is characterized in that at least level-one latch module includes first
Grade latch module, second level latch module；
The first order latch module is latched with the shift register subelement, the data signal end and the second level
Module is connected；The first order latch module is used under the control of the shift register subelement output signal, to institute
The data-signal for stating data signal end output is latched, and the data-signal is exported to the second level latch module；
The second level latch module is used for the data-signal that is exported to the first order latch module and latches, and to described
Data line exports the data-signal；
The reseting module is connected with the first order latch module or the second level latch module.
3. source drive unit according to claim 2, which is characterized in that the reseting module includes reset transistor；
The grid of the reset transistor connects the enable signal end, and the first pole connects the reset signal end, the second pole with it is described
First order latch module or the second level latch module are connected.
4. the source drive unit according to Claims 2 or 3, which is characterized in that the first order latch module includes the
One transmission submodule and first latches submodule；
The first control signal end of first transmission submodule and the shift register subelement, the data signal end with
And first latch node be connected；The first transmission submodule is used for the first control letter in the shift register subelement
Number end control under, by the signal transmission of the data signal end to described first latch node；
Described first, which latches submodule connection described first, latches node, the second level latch module and the shift LD
The second control signal end of device subelement；Described first, which latches submodule, is used to control the second of the shift register subelement
Under the control of signal end processed, the data-signal of the described first latch node is latched, and export to the second level and latch
Module.
5. the source drive unit according to Claims 2 or 3, which is characterized in that the second level latch module includes the
Two transmission submodules and second latch submodule；
The second transmission submodule connects the first order latch module, the first open signal end and the second latch node；
The second transmission submodule is used under the control at the first open signal end, by first order latch module output
Data signal transmission to described second latch node；
Described second, which latches submodule connection described second, latches node, the second open signal end, and described second latches submodule
For under the control at the second open signal end, the data-signal of the described second latch node is latched, and by institute
State data-signal output.
6. source drive unit according to claim 4, which is characterized in that
The first transmission submodule includes the first transmission gate；The input terminal of first transmission gate and the data signal end phase
Connection, the first control terminal and the second control terminal are controlled respectively with the first control signal end of the shift register subelement and second
Signal end processed is connected, and output terminal is connected with the described first latch node.
7. source drive unit according to claim 4, which is characterized in that described first, which latches submodule, includes the second biography
Defeated door, the first phase inverter, the second phase inverter and third phase inverter；
The input terminal of second transmission gate connects the output terminal of the third phase inverter, the first control terminal and the second control terminal point
It is not connected with the first control signal end of the shift register subelement and second control signal end, output terminal and described the
One latch node is connected；
The input terminal of first phase inverter is connected with the described first latch node, output terminal and the third phase inverter and institute
The input terminal for stating the second phase inverter is connected；
The output terminal of second phase inverter connects the second level latch module.
8. source drive unit according to claim 7, which is characterized in that locked in the reseting module and the first order
In the case that storing module is connected, and the reseting module includes reset transistor,
Second pole of the reset transistor is connected with the input terminal of first phase inverter；With the of the reset transistor
The reset signal end that one pole is connected is first voltage end；
Alternatively, the second pole of the reset transistor is connected with the output terminal of first phase inverter；With the reset crystal
The reset signal end that first pole of pipe is connected is second voltage end.
9. source drive unit according to claim 5, which is characterized in that
The second transmission submodule includes third transmission gate；The input terminal of the third transmission gate latches mould with the first order
Block is connected, and the first control terminal and the second control terminal are connected respectively with the first open signal end and the second open signal end, defeated
Outlet is connected with the described second latch node.
10. source drive unit according to claim 5, which is characterized in that
Described second, which latches submodule, includes the 4th transmission gate, the 4th phase inverter, the 5th phase inverter and hex inverter；
The first control terminal and the second control terminal of 4th transmission gate respectively with the first open signal end and the second open signal
End is connected, and input terminal is connected with the output terminal of the 5th phase inverter, and output terminal is connected with the described second latch node；
Alternatively, the input terminal of the 4th transmission gate is connected with the output terminal of the 4th phase inverter, output terminal and described the
The input terminal of five phase inverters is connected；
The output terminal of 4th phase inverter and the input terminal of the 5th phase inverter and the input terminal phase of the hex inverter
Connection；
Output terminal of the output terminal of the hex inverter as the second level latch module.
11. source drive unit according to claim 10, which is characterized in that in the reseting module and the second level
In the case that latch module is connected, and the reseting module includes reset transistor,
Second pole of the reset transistor is connected with the input terminal of the 4th phase inverter；With the of the reset transistor
The reset signal end that one pole is connected is first voltage end；
Alternatively, the second pole of the reset transistor is connected with the output terminal of the 4th phase inverter；With the reset crystal
The reset signal end that first pole of pipe is connected is second voltage end.
12. source drive unit according to claim 2, which is characterized in that the latch subelement further includes buffering mould
Block, the buffer module include the 7th phase inverter and the 8th phase inverter；
The input terminal of 7th phase inverter is connected with the output terminal of the second level latch module, output terminal and the described 8th
The input terminal of phase inverter is connected；
Output terminal of the output terminal of 8th phase inverter as the source drive unit.
13. a kind of source electrode drive circuit, which is characterized in that including multiple arranged side by side as described in claim any one of 1-12
Source drive unit；
Shift register subelement in multiple source drive units cascades successively.
14. a kind of display device, which is characterized in that including host driver and source drive as claimed in claim 13 electricity
Road, the host driver are connected by data signal end with source drive unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721406539.2U CN207602196U (en) | 2017-10-26 | 2017-10-26 | A kind of source drive unit, source electrode drive circuit, display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721406539.2U CN207602196U (en) | 2017-10-26 | 2017-10-26 | A kind of source drive unit, source electrode drive circuit, display device |
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| Publication Number | Publication Date |
|---|---|
| CN207602196U true CN207602196U (en) | 2018-07-10 |
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ID=62755881
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| CN201721406539.2U Withdrawn - After Issue CN207602196U (en) | 2017-10-26 | 2017-10-26 | A kind of source drive unit, source electrode drive circuit, display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107633817A (en) * | 2017-10-26 | 2018-01-26 | 京东方科技集团股份有限公司 | Source drive unit and its driving method, source electrode drive circuit, display device |
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2017
- 2017-10-26 CN CN201721406539.2U patent/CN207602196U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107633817A (en) * | 2017-10-26 | 2018-01-26 | 京东方科技集团股份有限公司 | Source drive unit and its driving method, source electrode drive circuit, display device |
| CN107633817B (en) * | 2017-10-26 | 2023-12-05 | 京东方科技集团股份有限公司 | Source electrode driving unit and driving method thereof, source electrode driving circuit and display device |
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