CN207557361U - A kind of circuit test plate for antistatic damage measure - Google Patents
A kind of circuit test plate for antistatic damage measure Download PDFInfo
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- CN207557361U CN207557361U CN201721236500.0U CN201721236500U CN207557361U CN 207557361 U CN207557361 U CN 207557361U CN 201721236500 U CN201721236500 U CN 201721236500U CN 207557361 U CN207557361 U CN 207557361U
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- chip
- binding post
- access section
- test plate
- circuit test
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Abstract
A kind of circuit test plate for antistatic damage measure, including：Chip access section, wire connecting portion and switch portion, it is characterized in that, chip to be measured is accessed by circuit test plate by chip access section, chip access section is electrically connected by wire connecting portion with switch portion, in test, the electric signal for the external power supply that wire connecting portion selects switch portion is transferred to chip to be measured, selectively to carry out antistatic test to the pin of chip to be measured.
Description
Technical field
The utility model is related to a kind of circuit test plates.More particularly, to a kind of electricity for antistatic damage measure
Drive test test plate (panel).
Background technology
Static discharge (ESD, electrostatic discharge) be the most colored cost of electronics industry the source of damage it
One.With the continuous microminiaturization of the manufacturing process of IC products, product failure problem caused by ESD is more and more prominent.Electrostatic can make MOS
The input, output end leakage current of integrated circuit increases, static angle stability increase, and the metal-oxide-semiconductor of input terminal occurs grid and wears.
In order to the ability for resisting electrostatic strike of IC product of the understanding manufactured by us, the quality of product is promoted, is subtracted
Few damage, IC engineers all over the world because of caused by ESD have developed many electrostatic discharge simulation devices, existing for simulating
The static discharge phenomenon to grow directly from seeds in living, in conventional dead point test, tester is through common Discharge Switch of ESD Simulator to being plugged on
Chip on bread board is tested, but since the distance between pin of chip is very near when being tested with this method, easily
Electric arc is generated, while lead is very thin in test, has very big internal resistance, antistatic test result can be affected.
The present invention devises a kind of electrostatic damage test board suitable for Discharge Switch of ESD Simulator, facilitates tester's test chip
ESD failure threshold, and can to avoid electric arc, reduce lead resistance.
Utility model content
The purpose of this utility model is to provide a kind of circuit test plates for antistatic damage measure.
In order to achieve the above objectives, the utility model uses following technical proposals：
A kind of circuit test plate for antistatic damage measure, including：Chip access section, wire connecting portion and switch portion,
It is characterized in that, chip to be measured is accessed by circuit test plate by chip access section, wire connecting portion is electric by chip access section and switch portion
Connection, in test, the electric signal for the external power supply that wire connecting portion selects switch portion is transferred to chip to be measured, with selectively right
The pin of chip to be measured carries out antistatic test.
Preferably, wire connecting portion includes binding post and pcb board, and wherein binding post is arranged on wiring circuit.
Preferably, chip access section is arranged on pcb board, and is electrically connected by the wiring on pcb board with binding post.
Preferably, switch portion includes multiple single-pole double-throw switch (SPDT)s, and switch portion is high voltage bearing.
Preferably, the first terminal of single-pole double-throw switch (SPDT) is electrically connected with the anode of external power supply, and the of single-pole double-throw switch (SPDT)
Two-terminal is electrically connected with the cathode of external power supply and the third terminal of single-pole double-throw switch (SPDT) is electrically connected with binding post.
Preferably, the quantity of binding post is equal with the number of pins of chip access section.
Preferably, the binding post of half quantity is located at the first side of chip access section and the binding post positioned at the first side is divided into
Two rows close to the first side and separate first side, and the binding post of the other half quantity is located at the second side of chip access section and is located at
The binding post of the second side is divided into close to the second side and the two rows far from the second side.
Preferably, in every side in chip portion, it will be close to the binding post of chip access section and chip access section be electrically connected
It connects up and will be far from the binding post of chip access section and wiring that chip access section is electrically connected is on the different surfaces of pcb board.
Preferably, circuit test plate further includes positive and negative anodes interface, the positive and negative anodes connection of positive and negative anodes interface and external power supply.
Preferably, substrate is insulation, wherein, switch portion, wire connecting portion and positive and negative anodes interface are disposed on substrate.
The beneficial effects of the utility model are as follows：
The circuit test plate that technical solution described in the utility model provides is suitable for a plurality of types of chips, draws in test
Line internal resistance is small and pin between be not likely to produce electric arc, the antistatic test for chip provides more accurate test result.
Description of the drawings
Specific embodiment of the present utility model is described in further detail below in conjunction with the accompanying drawings：
Fig. 1 is the block diagram for showing the circuit test plate according to the disclosure；
Fig. 2 is according to the circuit layout in an embodiment of the present disclosure on pcb board；
Fig. 3 is the circuit connection diagram shown according to substrate in an embodiment of the present disclosure and pcb board；And
Fig. 4 is to schematically show in Fig. 3 two binding posts and switch and external electricity in the circuit connection diagram of embodiment
The figure of specific connection relation between the anode and cathode terminals in source.
Specific embodiment
In order to illustrate more clearly of the utility model, the utility model is done into one with reference to preferred embodiments and drawings
The explanation of step.Similar component is indicated with identical reference numeral in attached drawing.It will be appreciated by those skilled in the art that below
Specifically described content is illustrative and be not restrictive, and should not limit the scope of protection of the utility model with this.
It should be understood that ordinal number first, second described in the specification etc. is intended merely to the clear of description rather than in order to limit
The sequence of element processed, component or component etc., that is, be described as first element, component and component and second element, component or component
It can also be expressed as second element, component and component and first element, component or component.
Circuit test plate provided by the utility model is suitable for carrying out the antistatic damage measure between chip pin.
Fig. 1 is the block diagram for showing the circuit test plate 1000 according to the disclosure.
As shown in Figure 1, circuit test plate 1000 includes chip access section 1002, wire connecting portion 1004 and switch portion 1006.
Chip access section 1002 is to receive the component of chip to be measured, can be dual-in-line socket, in the present embodiment, core
The quantity of piece access section 1002 is 1, it should be appreciated that the present disclosure is not limited thereto.The number of pin of chip access section 1002 can be 14,
16th, the even numbers such as 20, it is preferable that can be 40 (but not limited to)s, the pin of pin and chip to be measured corresponds, can be with
For fixing chip to be measured, and it is electrically connected with the respective pin of chip to be measured.It should be understood that the structure of chip access section 1002 is not
It is limited to such form.Correspondingly, it should be understood that the circuit test plate 1000 of the disclosure can be to can arbitrarily access via chip
The chip that portion 1002 is electrically connected carries out electrostatic damage test.
Wire connecting portion 1004 includes binding post 1004-1,1004-2,1004-3 and 1004-4 and pcb board 2000 (not in Fig. 1
It specifically illustrates, is described in detail hereinafter in conjunction with attached drawing 2 and attached drawing 3).Wire connecting portion 1004 with it is each in circuit test plate 1000
A component electrical connection, for transmitting electric signal, and while electric signal is transmitted, reaches the mesh for avoiding electric arc and reducing error
's.Wire connecting portion 1004 includes binding post 1004-1,1004-2,1004-3 and 1004-4 and pcb board, wherein binding post 1004-
1st, 1004-2,1004-3 and 1004-4 are arranged on pcb board.
Switch portion 1006 is multiple switch.Preferably, the quantity switched in switch portion 1006 and chip access section 1002
Number of pin is equal, and switch portion 1006 participates in the chip pin of test for selection.Preferably, in embodiment of the disclosure,
Switch in switch portion 1006 can be single-pole double-throw switch (SPDT).It should be understood that switch portion 1006 can be by can arbitrarily play multichannel
The element composition of selection index system.
According to the circuit test plate of the disclosure, may also include substrate and positive and negative anodes interface (it is not shown in FIG. 1, will be under
Text combination attached drawing 2 and attached drawing 3 are described in detail).In such embodiments, substrate is located at the lowest level of circuit test plate 1000,
Pcb board and switch portion 1006 are disposed on substrate, chip access section 1002 and binding post 1004-1,1004- are disposed on pcb board
2nd, 1004-3 and 1004-4.(specific connection relation will be described in detail separately below).
Fig. 2 is according to the circuit layout on pcb board in an embodiment of the present disclosure 2000.
As shown in Fig. 2, schematically shown in figure wire laying mode on pcb board 2000 and binding post 1004-1,
The layout of 1004-2,1004-3 and 1004-4 on pcb board 2000.
Various pieces in circuit layout are represented respectively with its corresponding part numbers.
As shown in Fig. 2, four row's binding posts being disposed on pcb board 2000 in chip access section 1002 and wire connecting portion 1004
1004-1,1004-2,1004-3 and 1004-4.Binding post 1004-1,1004-2,1004-3 and 1004-4 are arranged on chip access
The both sides in portion 1002.The chip access section 1002 with 40 pins is shown in FIG. 2, correspondingly, in this embodiment, with
The pin of chip access section 1002 has the total number of binding post 1004-1,1004-2,1004-3 and 1004-4 of identical quantity
Also it is 40.It should be understood that embodiment of the disclosure is without being limited thereto.In addition, binding post 1004-1,1004-2,1004-3 and
It is equal that quantity of the chip access section 1002 per side is arranged among 1004-4.And positioned at the first side of chip access section 1002
Binding post 1004-1 and 1004-2 points be close to the binding post 1004-1 of the first side of chip access section 1002 and far from chip
The binding post 1004-2 of access section 1002,1004-3 and 1004-4 points of the binding post positioned at the second side of chip access section 1002 are
Close to the binding post 1004-3 of the second side of the chip access section 1002 and binding post 1004-4 of separate chip access section 1002.This
Outside, the lower floor of pcb board 2000 is distributed in binding post 1004-1 shown in Fig. 2 and binding post the 1004-3 lead being connected, with Fig. 2
Shown binding post 1004-2 is distributed in the upper strata of pcb board 2000 with the binding post 1004-4 leads being connected.It should be understood that and Fig. 2
Lead that shown binding post 1004-1 and binding post 1004-3 is connected and with binding post 1004-2 shown in Fig. 2 and binding post
The lead that 1004-4 is connected is distributed in different layers.
The layout from Fig. 2 is it should be understood that arrangement is divided, which to put, can make in binding post 1004-1,1004-2,1004-3 and 1004-4
It is each between distance increase, while make to connect each and chip in binding post 1004-1,1004-2,1004-3 and 1004-4
The distance between wiring of respective pin electrical connection for entering portion 1002 increases as much as possible, and the wire laying mode of different layers more increases
Insulation distance between lead generates so as to avoid electric arc between pin well, in addition, the increase of distance can also make designer
In wiring, overstriking as much as possible connects up, so as to reduce lead resistance.
Fig. 3 is the circuit connection diagram shown according to substrate in an embodiment of the present disclosure 3000 and pcb board.
As shown in the figure, the Blocked portion among figure is pcb board 2000, pcb board 2000 is fixed on 3000 top of substrate.
Substrate 3000 is formed by insulating materials, it is therefore preferable to plank.It should be understood that substrate 3000 can also be by plastics, You Jiju
The insulating materials such as condensation material are formed.In addition, as shown in the figure, in the present embodiment, switch portion 1006 is arranged on substrate, and quantity
It is equal with the number of pin of chip access section 1002, that is, be arranged on pcb board 2000 binding post 1004-1,1004-2,
The quantity of 1004-3 and 1004-4 is equal.For convenience of line, switch portion 1006 relative to PCB position and binding post 1004-1,
1004-2,1004-3 are similar relative to the position of chip access section 1002 with 1004-4.As shown in Figure 3, it is arranged to switch portion
1006-1,1006-2,1006-3 and 1006-4.It should be understood that electric arc generates between such layout avoids pin, lead is reduced
Resistance.
In addition may also include positive and negative anodes interface (not shown) on substrate 3000, with the anode and cathode terminals VCC of external power supply and
GND connections.
In addition, the size of PCB circuit board 2000 depends on the number of chip access section 1002, in the present embodiment, chip
The quantity of access section 1002 is 1, and the distance between two rows of row's needles of chip access section 1002 are 100mil, and size is
2000mil × 640mil, the size of PCB circuit board 2000 is 5200mil × 5420mil, for connecting chip access section 1002
Pin and binding post 1006 between wire widths for 20mil, the distance between adjacent two binding posts are 370mil, two
It arranges between binding post 1004-1 and 1004-2, the distance between binding post 1004-3 and 1004-4 are 790mil.Substrate 3000
Size is 50cm × 40cm.
During practical electrostatic test, there can be three classes test mode：
1st, the power pin of chip to be measured is connect positive voltage, other pins other than GND is all connect negative voltage, started
Electrostatic test, this procedural test is antistatic capacity between power pin and other pins other than GND；Instead
The power pin of chip, is connect negative voltage by it, and other pins other than GND are all connect negative voltage, start electrostatic test.This
Two kinds of tests cover the test of the antistatic effect under two kinds of voltages to power supply.
2nd, the GND pins of chip are connect positive voltage, other pins other than power supply is all connect negative voltage, start electrostatic
Test, this procedural test is antistatic capacity between GND pins and other pins other than power supply；Conversely,
The GND pins of chip are connect negative voltage, other pins other than power supply are all connect negative voltage, start electrostatic test.This two
Kind test covers the test of the antistatic effect under two kinds of voltages to GND.
3rd, one of other pins other than power supply and GND of chip A (with its corresponding binding post mark in figure
A positive voltage) is connect, the pin other than above three pin (power supply, GND, A) is connect negative voltage, starts electrostatic test, this
Procedural test is antistatic effect between A pins and other pins other than power supply and GND；Conversely, the A chip
Pin connects negative voltage, and the pin other than above three pin (power supply, GND, A) is connect positive voltage, starts electrostatic test.This
Two kinds of tests cover the test of the antistatic effect under two kinds of voltages to A pins.Similarly pins other in chip are carried out
Electrostatic test.
Fig. 4 is to schematically show in Fig. 3 two binding posts and switch and positive and negative anodes in the circuit connection diagram of embodiment
The figure of specific connection relation between interface.
As shown in figure 4, switch S1 and S2 during binding post 1 and 2 and switch portion 1006 are schematically shown in figure and with
Specific connection relation between the anode and cathode terminals VCC and GND of external power supply.
Specifically, as shown in the figure, the first terminal of switch S1 is electrically connected with the positive terminal VCC of external power supply, S1 is switched
Second terminal be electrically connected with the positive terminal GND of external power supply, the third terminal for switching S1 is electrically connected with binding post 1.It is similar
Ground, the first terminal for switching S2 be electrically connected with the positive terminal VCC of external power supply, switchs the Second terminal and external power supply of S2
Positive terminal GND is electrically connected, and the third terminal for switching S2 is electrically connected with binding post 2.If user want test with binding post 1 and
Electrostatic damage between the chip pin of the respective pin electrical connection for the chip access section 1002 that binding post 2 connects, then can will switch
S1 and switch S2 are placed in different power supply terminals, make to generate voltage difference between two chip pins, to carry out electrostatic damage test, and
When switching S1 and switch S2 is placed in identical power supply terminal, do not form voltage difference between two chip pins, then it cannot be into
The antistatic damage measure of row, so as to complete circuit selection by switching S1 and switch S2.
It should be understood that the connection relation between the anode and cathode terminals of other binding posts, switch and extraneous power supply is similar.
It should also be understood that switch S1 and S2 can also be the element that can arbitrarily play selection index system.
Obviously, above-described embodiment of the utility model is only intended to clearly illustrate the utility model example, and simultaneously
Non- is the restriction to the embodiment of the utility model, for those of ordinary skill in the art, in above description
On the basis of can also make other variations or changes in different ways, all embodiments can not be exhaustive here, it is all
It is to belong to the guarantor of obvious changes or variations that the technical solution of the utility model extends out still in the utility model
Protect the row of range.
Claims (10)
1. a kind of circuit test plate for antistatic damage measure, including：Chip access section, wire connecting portion and switch portion,
It is characterized in that, chip to be measured accessed the circuit test plate by the chip access section, the wire connecting portion is by institute
Chip access section is stated to be electrically connected with the switch portion, in test, external power supply that the wire connecting portion selects the switch portion
Electric signal be transferred to the chip to be measured, selectively to carry out antistatic test to the pin of the chip to be measured.
2. circuit test plate as described in claim 1, which is characterized in that the wire connecting portion includes binding post and pcb board, wherein
The binding post is arranged on the pcb board.
3. circuit test plate as claimed in claim 2, which is characterized in that the chip access section is arranged on pcb board, and
It is electrically connected by the wiring on the pcb board with the binding post.
4. circuit test plate as claimed in claim 3, which is characterized in that the switch portion be multiple single-pole double-throw switch (SPDT)s, institute
It is heat safe to state switch portion.
5. circuit test plate as claimed in claim 4, which is characterized in that the first terminal of the single-pole double-throw switch (SPDT) with it is described
The anode electrical connection of external power supply, the Second terminal of the single-pole double-throw switch (SPDT) are electrically connected with the cathode of the external power supply, with
And the third terminal of the single-pole double-throw switch (SPDT) is electrically connected with the binding post.
6. circuit test plate as claimed in claim 2, which is characterized in that the quantity of the binding post and the chip access section
Number of pins it is equal.
7. circuit test plate as claimed in claim 6, which is characterized in that the binding post of half quantity is located at the chip
First side of access section and positioned at first side binding post be divided into close to first side and far from first side two
Row, and the binding post of the other half quantity is located at the second side of the chip access section and positioned at the binding post of the second side
It is divided into the two rows close to the second side and the separate the second side.
8. circuit test plate as claimed in claim 7, which is characterized in that in every side of the chip access section, the first cloth
Line and the second wiring are on the different surfaces of the pcb board, wherein first wiring is will be close to the chip access section
The wiring that is electrically connected with the chip access section of the binding post；Second wiring is will be far from the chip access section
The wiring that the binding post is electrically connected with the chip access section.
9. circuit test plate as claimed in claim 2, which is characterized in that further include positive and negative anodes interface, the positive and negative anodes interface
It is connect with the positive and negative anodes of the external power supply.
10. circuit test plate as claimed in claim 9, which is characterized in that substrate is further included, the substrate is insulation,
In, the switch portion, the wire connecting portion and the positive and negative anodes interface are disposed on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721236500.0U CN207557361U (en) | 2017-09-26 | 2017-09-26 | A kind of circuit test plate for antistatic damage measure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721236500.0U CN207557361U (en) | 2017-09-26 | 2017-09-26 | A kind of circuit test plate for antistatic damage measure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207557361U true CN207557361U (en) | 2018-06-29 |
Family
ID=62676682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721236500.0U Active CN207557361U (en) | 2017-09-26 | 2017-09-26 | A kind of circuit test plate for antistatic damage measure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207557361U (en) |
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2017
- 2017-09-26 CN CN201721236500.0U patent/CN207557361U/en active Active
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