CN206147051U - Survey test panel suitable for aassessment of many devices irradiation is experimental - Google Patents
Survey test panel suitable for aassessment of many devices irradiation is experimental Download PDFInfo
- Publication number
- CN206147051U CN206147051U CN201621251651.9U CN201621251651U CN206147051U CN 206147051 U CN206147051 U CN 206147051U CN 201621251651 U CN201621251651 U CN 201621251651U CN 206147051 U CN206147051 U CN 206147051U
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- terminal
- socket
- test board
- dual
- circuit board
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Abstract
The utility model discloses a survey test panel suitable for aassessment of many devices irradiation is experimental, include circuit board (1), be fixed in a plurality of discrete anchor clamps (2) on circuit board (1) and hold anode and cathode interface (3) of (8) including positive terminal (7) that are used for external power supply with the negative pole, each stands separately anchor clamps (2) including dual inline socket (4) and insert (5) and protect resistance (6) rather than the row of each pin one -to -one respectively, each row insert (5) including each other insulating with the first terminal (9) that negative pole end (8) electricity is connected, with second terminal (10) that the corresponding pin of dual inline socket (4) electricity is connected and third terminal (11) be connected with the one end electricity of corresponding protection resistance (6), the protection resistance (6) the other end with it connects to survey positive terminal (7) electricity of test panel, the utility model discloses the irradiation aassessment that can accomplish the electron device of a plurality of different models simultaneously is experimental.
Description
Technical field
This utility model is related to microelectronic testing technical field.Comment suitable for many device irradiation more particularly, to one kind
Estimate the test board of test.
Background technology
The impact of the various rays such as the electronic device being applied in radiation environment, alpha ray, the β rays being vulnerable in environment,
Some radiation effects are produced, and then parameters of electronic device can be caused to change, electronic device can be caused to damage when serious, make electricity
Road is failed, and then prevents electronic equipment from normally working, running.Accordingly, it would be desirable to be applied to radiation environment for these carry out
Irradiation damage evaluation test, so as to obtain some parametric results with regard to IC chip come its capability of resistance to radiation of knowing the real situation, surveys
Test plate (panel) in test as the carrier of electronic device, to the irradiation damage evaluation test of electronic device very important work is played
With.
An existing manufacturing technology test board for being suitable only for itself individually designed to every kind of electronic device, other models
Electronic device can not be general, multiple electronic devices can not be tested simultaneously, manufacture and experimentation cost can be caused high, product testing
The problems such as cycle is long.Accordingly, it would be desirable to design a kind of test board suitable for the test of many device total doses to meet different model
Multiple electronic devices carry out the requirement of total dose test simultaneously, improve Industrial Efficiency.
Utility model content
The purpose of this utility model is that offer is a kind of is available for multiple electronic devices of different model to comment while carrying out irradiation
Estimate the test board of test.
To reach above-mentioned purpose, this utility model adopts following technical proposals:
A kind of test board suitable for the test of many device total doses, it is characterised in that including circuit board, described in being fixed on
Multiple discrete fixture and both positive and negative polarity interface on circuit board;
The discrete fixture include dual-in-line socket, respectively with the one-to-one socket of each pin of dual-in-line socket
And protective resistance;
The both positive and negative polarity interface includes the positive terminal and negative pole end for external power supply;
Each socket includes the first terminal, Second terminal and the third terminal of mutually insulated, wherein,
The first terminal, electrically connects with the negative pole end of the test board;
Second terminal, electrically connects with the respective pin of the dual-in-line socket;
Third terminal, electrically connects with one end of corresponding protective resistance;
The other end of the protective resistance is electrically connected with the positive terminal of the test board.
Preferably, the test board further includes multiple for short circuit the first terminal and Second terminal or for short circuit second
The jumper cap of terminal and third terminal.
Preferably, when the jumper cap short circuit the first terminal and Second terminal, the dual-in-line socket correspondence pin
For electronegative potential;When the jumper cap short circuit Second terminal and third terminal, the dual-in-line socket correspondence pin is high electricity
Position;When jumper cap described in the socket not grafting, the dual-in-line socket correspondence pin is in vacant state.
Preferably, the plurality of discrete fixture is the discrete fixture of the even number being arranged symmetrically on the circuit board.
Preferably, the plurality of discrete fixture is 4,6,8 or 10 discrete fixtures.
Preferably, each protective resistance is located on the first face of the circuit board with the connecting wiring of positive terminal, each row
Slotting the first terminal is located on the first and second faces of the circuit board with the connecting wiring of negative pole end.
Preferably, each socket the first terminal lead-out wire is formed on the second face of circuit board, by being arranged at the circuit
Multiple through holes in plate central authorities are electrically connected to circuit board first face and are routed to the negative pole end.
Preferably, the dual-in-line socket includes 20 pins.
Preferably, the dual-in-line socket is used for chip of the grafting packing forms for DIP types.
Preferably, the resistance of the protective resistance is 10K.
Description of the drawings
Specific embodiment of the present utility model is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 shows the master-plan domain of test board.
Fig. 2 shows the circuit theory diagrams of each discrete fixture.
Specific embodiment
In order to be illustrated more clearly that this utility model, this utility model is done into one with reference to preferred embodiments and drawings
The explanation of step.Similar part is indicated with identical reference in accompanying drawing.It will be appreciated by those skilled in the art that below
Specifically described content is illustrative and be not restrictive, and should not limit protection domain of the present utility model with this.
As shown in figure 1, the utility model discloses a kind of test board suitable for the test of many device total doses, including electricity
Road plate 1, the multiple discrete fixture 2 being fixed on the circuit board 1 and both positive and negative polarity interface 3.Discrete fixture 2 and both positive and negative polarity interface 3
Can be fixed on the circuit board 1 in the form of welding, the both positive and negative polarity interface 3 includes the positive terminal 7 for external power supply
With negative pole end 8, the discrete fixture 2 is to be arranged symmetrically the discrete fixture 2 of even number on the circuit card 1, it is preferred that discrete fixture
2 number can be 4,6 or 8, it is further preferred that the number of discrete fixture 2 is 6.Discrete fixture 2 includes dual-in-line socket 4 and double
The one-to-one socket 5 of each pin of row straight cutting socket 4 and protective resistance 6, the wherein pin of dual-in-line socket 4 can be 20,
Can be used for the chip that grafting packing forms are DIP types, packing forms can be 14,16 or 20 for the chip pin number of DIP types.Each
Socket 5 includes the first terminal 9, Second terminal 10 and the third terminal 11 of mutually insulated, and wherein the first terminal 9 is negative with test board
Extreme 8 electrical connection;Second terminal 10 is electrically connected with the respective pin of dual-in-line socket 4;Third terminal 11 and corresponding protection
One end electrical connection of resistance 6, the other end of protective resistance 6 is electrically connected with the positive terminal 7 of test board, the optional resistance of protective resistance 6
For the resistance of 10K.
It is pluggable for short circuit the first terminal 9 and Second terminal 10 or for the He of short circuit Second terminal 10 in each socket 5
The jumper cap of third terminal 11.As shown in Fig. 2 when the jumper cap short circuit the first terminal 9 and Second terminal 10, the biserial
The correspondence pin of straight cutting socket 4 is electronegative potential;When the jumper cap short circuit Second terminal 10 and third terminal 11, the biserial is straight
The correspondence pin of plug-and-socket 4 is high potential;When not grafting jumper cap in socket 5, the correspondence of dual-in-line socket 4 pin is outstanding
Dummy status.Each protective resistance 6 is located on the first face of the circuit board 1 with the connecting wiring 12 of positive terminal 7, each socket 5
The first terminal 9 is located on the first and second faces of the circuit board 1 with the connecting wiring 13 of negative pole end 8.Specifically, each socket 5
The lead-out wire of the first terminal 9 is formed on the another side of circuit board 1, by the multiple through holes electricity for being arranged at the central authorities of the circuit board 1
It is connected to the face of circuit board 1 first and is routed to the positive terminal 7 on the first face.On the two sides of circuit board 1 with positive terminal 7 and
Vice versa for the routing relations of the electrical connection of negative pole end 8.In a preferred embodiment, three row through holes, each column 32 are provided with test board
It is individual, wherein 15 through holes of the three row through holes per string one end are used to electrically connect the connection cloth of each protective resistance 6 and positive terminal 7
Line 12,15 through holes of the other end are used to electrically connect the connecting wiring 13 of the first terminal 9 of each socket 5 and negative pole end 8.
The size of circuit board 1 depends on the size and number of discrete fixture 2.Size of circuit board 1 is in this
4196mil × 7605mil, the size of dual-in-line socket 4 is 1008mil × 298mil.The position relationship of device on circuit board 1
Rationally arranged according to the size of circuit board 1 and device size.In this instance, positioned at homonymy adjacent position discrete fixture 2 biserial
The distance between straight cutting socket 4 be 1206mil, each pin of each device position dual-in-line socket 4 and corresponding row on test board
It is 287mil to insert the distance between 5, and the distance between socket 5 and corresponding protective resistance 6 are 200mil, positioned at homonymy adjacent position
The distance between the socket 5 of correspondence position of discrete fixture 2 be 1206mil, the distance between protective resistance 6 of correspondence position
For 1052mil.
Obviously, above-described embodiment of the present utility model is only intended to clearly illustrate this utility model example, and
It is not the restriction to embodiment of the present utility model, for those of ordinary skill in the field, in described above
On the basis of can also make other changes in different forms, all of embodiment cannot be exhaustive here,
It is every to belong to the obvious change or change still in of the present utility model that the technical solution of the utility model extends out
The row of protection domain.
Claims (10)
1. it is a kind of suitable for many device total doses test test board, it is characterised in that including circuit board (1), be fixed on institute
State the multiple discrete fixture (2) and both positive and negative polarity interface (3) on circuit board (1);
Each discrete fixture (2) including dual-in-line socket (4), respectively with each pin of dual-in-line socket (4) one by one
Corresponding socket (5) and protective resistance (6);
The both positive and negative polarity interface (3) includes the positive terminal (7) and negative pole end (8) for external power supply;
The first terminal (9) of each socket (5) including mutually insulated, Second terminal (10) and third terminal (11), wherein,
The first terminal (9), electrically connects with the negative pole end (8);
Second terminal (10), electrically connects with the respective pin of the dual-in-line socket (4);
Third terminal (11), electrically connects with one end of corresponding protective resistance (6);
The other end of the protective resistance (6) is electrically connected with the positive terminal (7) of the test board.
2. test board according to claim 1, it is characterised in that the test board further includes multiple for short circuit first end
Sub (9) and Second terminal (10) or for short circuit Second terminal (10) and the jumper cap of third terminal (11).
3. test board according to claim 2, it is characterised in that when the jumper cap short circuit the first terminal (9) and the second end
When sub (10), dual-in-line socket (4) the correspondence pin is electronegative potential;When the jumper cap short circuit Second terminal (10) and
During three terminals (11), dual-in-line socket (4) the correspondence pin is high potential;When wire jumper described in the socket (5) not grafting
During cap, dual-in-line socket (4) the correspondence pin is in vacant state.
4. test board according to claim 1, it is characterised in that the plurality of discrete fixture (2) is described to be arranged symmetrically in
The discrete fixture of even number (2) on circuit board (1).
5. test board according to claim 4, it is characterised in that the plurality of discrete fixture (2) is 4,6,8 or 10 it is discrete
Fixture (2).
6. test board according to claim 1, it is characterised in that the connection cloth of each protective resistance (6) and positive terminal (7)
Line (12) on the first face of the circuit board (1), the connecting wiring of each socket (5) the first terminal (9) and negative pole end (8)
(13) on the first and second faces of the circuit board (1).
7. test board according to claim 6, it is characterised in that each socket (5) the first terminal (9) lead-out wire is formed in circuit
On second face of plate (1), by being arranged at multiple through holes in the circuit board (1) central authorities the face of circuit board (1) first is electrically connected to
And it is routed to the negative pole end (8).
8. test board according to claim 1, it is characterised in that the dual-in-line socket (4) is including 20 pins.
9. test board according to claim 1, it is characterised in that the dual-in-line socket (4) is for grafting packing forms
For the chip of DIP types.
10. test board according to claim 1, it is characterised in that the resistance of the protective resistance (6) is 10K.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201621251651.9U CN206147051U (en) | 2016-11-15 | 2016-11-15 | Survey test panel suitable for aassessment of many devices irradiation is experimental |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201621251651.9U CN206147051U (en) | 2016-11-15 | 2016-11-15 | Survey test panel suitable for aassessment of many devices irradiation is experimental |
Publications (1)
Publication Number | Publication Date |
---|---|
CN206147051U true CN206147051U (en) | 2017-05-03 |
Family
ID=58626164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201621251651.9U Active CN206147051U (en) | 2016-11-15 | 2016-11-15 | Survey test panel suitable for aassessment of many devices irradiation is experimental |
Country Status (1)
Country | Link |
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CN (1) | CN206147051U (en) |
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2016
- 2016-11-15 CN CN201621251651.9U patent/CN206147051U/en active Active
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