CN207517678U - Semiconductor package with antenna module - Google Patents

Semiconductor package with antenna module Download PDF

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Publication number
CN207517678U
CN207517678U CN201721686036.5U CN201721686036U CN207517678U CN 207517678 U CN207517678 U CN 207517678U CN 201721686036 U CN201721686036 U CN 201721686036U CN 207517678 U CN207517678 U CN 207517678U
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CN
China
Prior art keywords
layer
substrate
antenna module
antenna
semiconductor package
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Active
Application number
CN201721686036.5U
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Chinese (zh)
Inventor
陈彦亨
林正忠
吴政达
林章申
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201721686036.5U priority Critical patent/CN207517678U/en
Application granted granted Critical
Publication of CN207517678U publication Critical patent/CN207517678U/en
Priority to US16/211,089 priority patent/US11316247B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Abstract

The utility model provides a kind of semiconductor package with antenna module, including：Substrate has first surface and second surface；Re-wiring layer, on first surface；Metal coupling is electrically connected to side of the re-wiring layer far from substrate；Semiconductor chip is electrically connected to surface of the re-wiring layer far from substrate side；Capsulation material layer surrounds metal coupling and semiconductor chip；Antenna module, on second surface, through the above scheme, the utility model capsulation material layer all coats semiconductor chip, ensure packaged stability, by semiconductor chip and metal coupling plastic packaging simultaneously, improve packaging efficiency and yield, antenna module and re-wiring layer are set to two opposite surfaces of substrate, is conducive to carry out reasonable package layout, selects quartz glass etc. as substrate, heat conductivity is good, it solves the problems, such as fuel factor, since quartz plate is without warpage issues, ensures to be not easy warpage and fracture etc. in subsequent technique chips.

Description

Semiconductor package with antenna module
Technical field
The utility model belongs to technical field of semiconductor encapsulation, more particularly to a kind of semiconductor package with antenna module Assembling structure.
Background technology
As the function of integrated circuit is increasingly stronger, performance and integrated level is higher and higher and novel integrated circuit goes out Existing, encapsulation technology plays an increasingly important role in IC products, shared in the value of entire electronic system Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, it is higher when Clock frequency develops, and encapsulation also develops to more highdensity direction
Since fan-out wafer grade encapsulates (fowlp) technology due to having many advantages, such as miniaturization, low cost and high integration, with And with better performance and higher energy efficiency, fan-out wafer grade encapsulation (fowlp) technology become the movement of high request/ The important packaging method of the electronic equipments such as wireless network is one of encapsulation technology most with prospects at present.In addition, for The considerations of communication efficiency, radio frequency chip can all set antenna when in use.But existing radio-frequency antenna is all developer to penetrating When frequency function module carries out layout designs, layout antennas or the interface of external antenna is reserved directly on pcb board, it is existing to penetrate Frequency antenna layout antennas directly on pcb board mostly, and such method will ensure antenna gain, just must be to sacrifice PCB surface Product is cost.And difficult, warping phenomenon hardly possible is controlled in warpage etc. using the fan-out-type wafer-level packaging of the techniques such as plastic packaging To be eased, and in encapsulation process harmomegathus of material etc. may cause sliding and dislocation the problems such as, it is also difficult to controlled System, heat conductivity is poor, the problem of causing fuel factor etc., in addition, preparation process and selection due to each component, be easy to cause each portion Relative movement between part and the problems such as deposit poor bonding strength between the components.
Therefore, a kind of semiconductor package of the low cost with antenna how is provided to solve in the prior art easily The real category such as fuel factor problem caused by be easy to causeing displacement and poor bonding strength and poor thermal conduction between warpage, each component occurs It is necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of with antenna module Semiconductor package, for solving easily to occur to be easy to cause displacement and bond strength between warpage, each component in the prior art Caused by poor, packaging technology complexity and poor thermal conduction the problem of fuel factor problem.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor package with antenna module Assembling structure, which is characterized in that including：
Substrate, the substrate have opposite first surface and second surface；
Re-wiring layer, on the first surface of the substrate；
Metal coupling is electrically connected positioned at side of the re-wiring layer far from the substrate and with the re-wiring layer It connects；
Semiconductor chip, positioned at surface of the re-wiring layer far from the substrate side, and with the rewiring Layer electrical connection, and there is spacing between the semiconductor chip and the metal coupling；
Capsulation material layer, positioned at surface of the re-wiring layer far from the substrate side, and it is convex to surround the metal Block and the semiconductor chip, and appear the part metal coupling and the part semiconductor chip；And
Antenna module, on the second surface of the substrate.
As a kind of preferred embodiment of the utility model, the capsulation material layer include polyimide layer, layer of silica gel and Any one in epoxy resin layer.
As a kind of preferred embodiment of the utility model, the substrate includes quartz glass substrate or sapphire substrate.
As a kind of preferred embodiment of the utility model, the structure of the re-wiring layer specifically includes：
Dielectric layer is engaged on the first surface of the substrate；
At least one layer of metal line layer, the metal line layer are located at the inside of the dielectric layer；
Underbump metallization layer positioned at surface of the dielectric layer far from the substrate side, and extends to the dielectric layer Inside be electrically connected with the metal line layer, wherein, the metal coupling is set on the Underbump metallization layer.
As a kind of preferred embodiment of the utility model, the concrete structure of the metal coupling includes：Copper post, positioned at described The nickel layer of copper post upper surface and the solder bump on the nickel layer.
As a kind of preferred embodiment of the utility model, the antenna module includes several antenna elements, and each institute Antenna element is stated with identical outer profile.
As a kind of preferred embodiment of the utility model, each antenna element is on the second surface of the substrate and being in Array arrangement, annular arrangement random are intervally arranged.
As a kind of preferred embodiment of the utility model, each antenna element on the second surface of the substrate be in six The cellular arrangement of side shape, and there is gap between each antenna element.
As a kind of preferred embodiment of the utility model, cross sectional shape of the antenna element along the substrate surface direction Including regular hexagon.
As a kind of preferred embodiment of the utility model, the antenna module includes at least two layers of antenna module elementary layer, Each layer antenna module elementary layer includes at least an antenna element.
As described above, the semiconductor package with antenna module of the utility model, has the advantages that：
The utility model is all coated semiconductor chip, ensure that in its encapsulation process by the setting of capsulation material layer Stability, and by semiconductor chip and metal coupling plastic packaging simultaneously, ensure that and be not easy to deviate between each component, further improve Packaging efficiency and yield；The semiconductor structure with antenna module of the utility model is by by antenna module and cloth again Line layer is set to two opposite surfaces of substrate, so as to be conducive to carry out rational package layout design；This practicality is new Type selects quartz glass etc., and as substrate, heat conductivity is good, has got well nearly ten to hundred times than encapsulating material, has solved fuel factor The problem of；Simultaneously as quartz plate is also further ensured that without warpage issues and is not easy warpage and fracture in subsequent technique chips Deng, and easy to manufacture, yield improve；The features simple structure of the utility model, it is at low cost, suitable for batch production.
Description of the drawings
Fig. 1 is shown as providing the structure diagram of substrate in the semiconductor package preparation of the utility model.
Fig. 2 is shown as forming the structure diagram after rewiring in the semiconductor package preparation of the utility model.
Fig. 3 is shown as being formed the structure diagram of metal coupling in the semiconductor package preparation of the utility model.
Fig. 4 is shown as being formed the structure diagram of semiconductor chip in the semiconductor package preparation of the utility model.
Fig. 5 is shown as being formed the structure diagram of capsulation material layer in the semiconductor package preparation of the utility model.
Fig. 6 is shown as being formed the structure diagram of antenna module in the semiconductor package preparation of the utility model.
Fig. 7 is shown as schematic top plan view of the semiconductor package of the utility model along antenna module one side.
Component label instructions
11 substrates
111 first surfaces
112 second surfaces
21 re-wiring layers
211 Underbump metallization layers
212 dielectric layers
213 metal line layers
31 metal couplings
41 semiconductor chips
51 capsulation material layers
61 antenna modules
611 antenna elements
Specific embodiment
Illustrate the embodiment of the utility model by particular specific embodiment below, those skilled in the art can be by this Content disclosed by specification understands other advantages and effect of the utility model easily.
It please refers to Fig.1 to Fig. 7.It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., only to Coordinate the revealed content of specification, so that those skilled in the art understands and reads, be not limited to the utility model Enforceable qualifications, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or size Adjustment, in the case where not influencing the effect of the utility model can be generated and the purpose that can reach, should all still fall in the utility model Revealed technology contents are obtained in the range of covering.Meanwhile in this specification it is cited as " on ", " under ", " left side ", The term on " right side ", " centre " and " one " etc. is merely convenient to the clear rather than enforceable to limit the utility model of narration Range, relativeness are altered or modified, enforceable when being also considered as the utility model in the case where changing technology contents without essence Scope.
As shown in the figure shown in 1~7, the utility model provides a kind of semiconductor package with antenna module, including：
Substrate 11, the substrate 11 have opposite first surface 111 and second surface 112；
Re-wiring layer 21, on the first surface 111 of the substrate 11；
Metal coupling 31, positioned at side of the re-wiring layer 21 far from the substrate 11 and with the re-wiring layer 21 electrical connections；
Semiconductor chip 41, positioned at surface of the re-wiring layer 21 far from 11 side of substrate, and with it is described heavy New route layer 21 is electrically connected, and has spacing between the semiconductor chip 41 and the metal coupling 31；
Capsulation material layer 51, positioned at surface of the re-wiring layer 21 far from 11 side of substrate, and described in encirclement Metal convex 31 pieces and the semiconductor chip 41, and appear the part metal coupling 31 and the part semiconductor chip 41； And
Antenna module 61, on the second surface 112 of the substrate 11.
As an example, the substrate 11 includes quartz glass substrate or sapphire substrate.
Specifically, the utility model provides a kind of semiconductor package, wherein, the substrate 11 is preferably quartz base plate Or sapphire substrate, on the one hand, the problem of due to quartz plate without warpage, so as to prevent semiconductor in subsequent preparation process The problems such as rupture, warpage and fracture, occurs for chip；On the other hand, quartzy heat transfer has got well nearly ten to hundred times than MC, has Good heat conductivity, so as to solve the problems, such as the fuel factor of encapsulation process.In addition, in other examples, the substrate may be used also With selected as others glass substrate, herein and it is not particularly limited.
In addition, the shape of the substrate 11 can be set according to actual needs, the shape of the substrate 11 can be Rectangle, circle, hexagon, triangle or trapezoidal etc., do not limit herein.
Specifically, the semiconductor chip 41 can be any one semiconductor functional chip, and the semiconductor chip 41 front is also formed with the connection pad for drawing inside function device electricity, and the connection pad is exposed to the semiconductor The front of chip, it is preferable that the upper surface of the connection pad and the upper surface flush of the semiconductor chip.It is described partly to lead Refer between body chip 41 and the metal coupling 31 with spacing, in table of the metal wiring layer far from the substrate side Face protrudes from the position of the metal wiring layer, has spacing between the semiconductor chip and the metal coupling, i.e., Exposed outside is not turned on.
In addition, the utility model is by the antenna module and the re-wiring layer, the metal coupling and described half The structure settings such as conductor chip are on two opposite sides of the substrate, so as to reasonably carry out setting for antenna structure Meter, and be conducive to reduce the volume of entire semiconductor package.
As an example, the capsulation material layer 51 is including arbitrary in polyimide layer, layer of silica gel and epoxy resin layer It is a kind of.
Specifically, encapsulating the semiconductor chip 41 using the capsulation material layer 51, use compression forming, transmit mould It is moulded into any one in type, fluid-tight molding, vacuum lamination and spin coating, the capsulation material layer 51 is by the semiconductor chip 41 surround completely, only manifest the one sides that the semiconductor chip electricity is drawn, i.e., described semiconductor chip in addition to electricity is drawn All surface is all in contact with the capsulation material layer, on the one hand can ensure stability of the chip in encapsulation process, separately On the one hand it can also ensure that chip is not easily susceptible to pollute and destroy in encapsulation process, without having to worry about chip and other materials layer Bond strength, step of preparation process simple optimization, in addition, the capsulation material layer coat simultaneously it is outer with the metal coupling It encloses, exposing needs the part that connects, further ensures the packaged stability of metal coupling and (described by same material layer Capsulation material layer) cladding, and participated in without other materials layer, it ensure that and be less prone to relative displacement therebetween, between guarantee the two Away from.
In addition, the capsulation material layer 51 can be also selected from above-mentioned selected from any one in above-mentioned material layer The laminated material bed of material that the laminated material bed of material of arbitrary two layers of composition in material layer or three are formed, this is selected according to actual demand, It is, of course, also possible to select any materials layer well known in the art, it is not limited with above-mentioned material layer.
As an example, the structure of the re-wiring layer 21 specifically includes：
Dielectric layer 212 is engaged on the first surface 111 of the substrate；
At least one layer of metal line layer 213, the metal line layer 213 are located at the inside of the dielectric layer 212；
Underbump metallization layer 211 positioned at surface of the dielectric layer 212 far from 11 side of substrate, and extends to institute The inside for stating dielectric layer 212 is electrically connected with the metal line layer 213, wherein, the metal coupling 31 is set under the convex block On metal layer 211.
Specifically, in one example, the re-wiring layer 21 include one layer of metal line layer, 213, one layers of dielectric layer 212 with And one layer of Underbump metallization layer 211, in one example its manufacturing process include：It is formed described in one layer prior to one surface of substrate Metal line layer forms one layer of dielectric layer then at the surface, and the dielectric layer coats the metal line layer, alternatively, it is also possible to be One layer of dielectric layer is initially formed, then performs etching the techniques such as filling；Then, opening is formed in dielectric layer, so as to prepare The Underbump metallization layer.Certainly, the re-wiring layer can be arbitrary re-wiring layer structure commonly used in the art, also may be used Being prepared using other techniques can arbitrarily realize that the re-wiring layer of function is drawn in electrical connection.
In addition, in other examples, or the dielectric layer and the two or more layers gold of two or more layers Belong to line layer, such as：Insulating layer described in first layer is formed in the surface of the substrate；In insulating layer described in first layer far from the substrate Surface form the metal line layer；Insulating layer described in the second layer, the second layer are formed in the upper surface of insulating layer described in first layer The metal line layer is completely covered in the insulating layer；In forming opening described in the second layer in insulating layer, the opening exposes institute State metal line layer；In forming the Underbump metallization layer in the opening.
Specifically, the material of the metal line layer 213 can be but be not limited only to copper, aluminium, nickel, only, silver or titanium in one The laminated material bed of material of kind material or two or more materials.The material of the dielectric layer 212 can be low k dielectric, specifically, It can include any one in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass.
As an example, the concrete structure of the metal coupling 31 includes：Copper post, positioned at the copper post upper surface nickel layer with And the solder bump on the nickel layer.
Specifically, the metal coupling 31 can be combination of metal column, solder ball or copper post and solder metal etc.. In the present embodiment, a kind of metal coupling 31 is provided, preparation includes：In making Underbump metallization layer on the re-wiring layer； Copper post is formed in the Underbump metallization layer surface；Metal barrier is formed in the copper post surface；In the metal barrier Surface forms solder metal, and forms solder bump in the metal barrier layer surface using high temperature reflow processes.
Wherein, the metal barrier includes nickel layer, the material of the solder bump include one kind in lead, tin and silver or Include the alloy of any one above-mentioned solder metal.
As an example, the antenna module 61 includes several antenna elements 611, and each antenna element 611 has There is identical outer profile.
Specifically, the antenna module 61 includes at least an antenna element 611, the shape of the antenna element can be Blocky or helical form, certainly, the quantity of the antenna element 611 can also be multiple, such as 10~100, according to actual demand It is fixed.When the quantity of the antenna element is more than two, the shape of different antenna elements 611 can be the same or different. In addition, when the antenna element 611 is patch antenna, the patch antenna can be metal derby；The antenna element 611 is spiral shell When revolving shape antenna, the helical antenna can be formed for metal wire coiling is spiral.Preferably, each antenna element Outer profile it is identical, so as to realize equal control, convenient for press actual demand carry out rational deployment.
In addition, the material of the antenna element include but not limited to it is any one in copper, aluminium, nickel, gold, silver, tin and titanium Kind or two kinds and more than above-mentioned material layer form the laminated material bed of material, can by physical gas-phase deposition (PVD), Any one in chemical vapor deposition method (CVD), sputtering, plating and chemical plating is prepared.
As an example, each antenna element 611 is on the second surface 112 of the substrate 11 and being arranged in array, ring Shape arranges or random is intervally arranged.
As an example, each antenna element 611 is in cellular row hexagonal on the second surface 112 of the substrate 11 Cloth, and there is gap between each antenna element 611.
As an example, the antenna element 611 includes regular hexagon along the cross sectional shape of 11 surface direction of substrate.
Specifically, a kind of layout type of each antenna element 611 is provided in this example, as shown in fig. 7, each day Line unit is uniformly arranged, and hexagonal cellular arrangement, has gap, this design side between each antenna element 611 Formula is simple for process, and the antenna element of identical outer profile need not carry out other additional techniques, and suitable for batch production, and antenna is interrogated Number uniformly, loss it is smaller.In addition, the gap between the adjacent antenna element is set with actual conditions, as in the substrate In plane where surface, along longitudinal direction or in the transverse direction perpendicular with it, the distance between center of adjacent antenna units can be with Arbitrarily setting, the size of each antenna element also can be selected arbitrarily.
Certainly, the arrangement mode of each antenna element can with and demand arbitrarily set, can set at the desired position The larger antenna element of density is put, can irregularly arrange, be not particularly limited herein.
As an example, the antenna module 61 includes at least two layers of antenna module elementary layer, each layer antenna module Elementary layer includes at least an antenna element 611.
Specifically, the antenna module 61 can be the second surface for having several antenna elements 611 in the substrate 11 112 individual layers arrange what is formed, it is of course also possible to be multilayer arrangement, including two layers or more than two layers of antenna element layer, so Afterwards, the design of fair amount and the antenna element of shape is carried out on each described antenna element layer again, wherein, adjacent two layers institute It states and is separated via dielectric layer between antenna element layer, and the conductive plug by being formed in dielectric layer realizes the electricity between different layers Connection, so as to carry out and specific demand carries out flexible antenna arrangement design.
In conclusion the utility model provides a kind of semiconductor package with antenna module, including：Substrate, institute Substrate is stated with opposite first surface and second surface；Re-wiring layer, on the first surface of the substrate；Metal is convex Block is electrically connected positioned at side of the re-wiring layer far from the substrate and with the re-wiring layer；Semiconductor chip, position In surface of the re-wiring layer far from the substrate side, and it is electrically connected with the re-wiring layer, and the semiconductor There is spacing between chip and the metal coupling；Capsulation material layer, positioned at the re-wiring layer far from the substrate side Surface, and surround the metal coupling and the semiconductor chip, and appear the part metal coupling and part described half Conductor chip；And antenna module, on the second surface of the substrate, through the above scheme, the utility model passes through modeling The setting of closure material layer all coats semiconductor chips, ensure that the stability in its encapsulation process, and by semiconductor chip with Metal coupling plastic packaging simultaneously, ensure that and be not easy to deviate between each component, further improve packaging efficiency and yield；This practicality The novel semiconductor structure with antenna module by by antenna module and re-wiring layer be set to two of substrate it is opposite Surface, so as to be conducive to carry out rational package layout design；The utility model selects quartz glass etc. as substrate, Its heat conductivity is good, has got well nearly ten to hundred times than encapsulating material, has solved the problems, such as fuel factor；Simultaneously as quartz plate without Warpage issues are also further ensured that and are not easy warpage and fracture etc., and easy to manufacture in subsequent technique chips, yield improves； The features simple structure of the utility model, it is at low cost, suitable for batch production.So the utility model effectively overcomes in the prior art Various shortcoming and have high industrial utilization.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.

Claims (10)

1. a kind of semiconductor package with antenna module, which is characterized in that including：
Substrate, the substrate have opposite first surface and second surface；
Re-wiring layer, on the first surface of the substrate；
Metal coupling is electrically connected positioned at side of the re-wiring layer far from the substrate and with the re-wiring layer；
Semiconductor chip, positioned at surface of the re-wiring layer far from the substrate side, and it is electric with the re-wiring layer Connection, and there is spacing between the semiconductor chip and the metal coupling；
Capsulation material layer, positioned at surface of the re-wiring layer far from the substrate side, and surround the metal coupling and The semiconductor chip, and appear the part metal coupling and the part semiconductor chip；And
Antenna module, on the second surface of the substrate.
2. the semiconductor package according to claim 1 with antenna module, which is characterized in that the capsulation material Layer includes any one in polyimide layer, layer of silica gel and epoxy resin layer.
3. the semiconductor package according to claim 1 with antenna module, which is characterized in that the substrate includes Quartz glass substrate or sapphire substrate.
4. the semiconductor package according to claim 1 with antenna module, which is characterized in that the rewiring The structure of layer specifically includes：
Dielectric layer is engaged on the first surface of the substrate；
At least one layer of metal line layer, the metal line layer are located at the inside of the dielectric layer；
Underbump metallization layer positioned at surface of the dielectric layer far from the substrate side, and extends to the interior of the dielectric layer Portion is electrically connected with the metal line layer, wherein, the metal coupling is set on the Underbump metallization layer.
5. the semiconductor package according to claim 1 with antenna module, which is characterized in that the metal coupling Concrete structure include：Copper post, the nickel layer positioned at the copper post upper surface and the solder bump on the nickel layer.
6. the semiconductor package with antenna module according to any one in Claims 1 to 5, feature exist In the antenna module includes several antenna elements, and each antenna element has identical outer profile.
7. the semiconductor package according to claim 6 with antenna module, which is characterized in that each antenna list Member is on the second surface of the substrate and being arranged in array, annular arrangement or random be intervally arranged.
8. the semiconductor package according to claim 6 with antenna module, which is characterized in that each antenna list Member has gap in cellular arrangement hexagonal on the second surface of the substrate between each antenna element.
9. the semiconductor package according to claim 8 with antenna module, which is characterized in that the antenna element Include regular hexagon along the cross sectional shape in the substrate surface direction.
10. the semiconductor package according to claim 6 with antenna module, which is characterized in that the antenna sets Part includes at least two layers of antenna module elementary layer, and each layer antenna module elementary layer includes at least an antenna list Member.
CN201721686036.5U 2017-12-07 2017-12-07 Semiconductor package with antenna module Active CN207517678U (en)

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KR100925665B1 (en) * 2007-12-10 2009-11-06 주식회사 네패스 System in package and fabrication method thereof
CN103985683B (en) * 2013-02-08 2017-04-12 精材科技股份有限公司 Chip package
TWI655719B (en) * 2015-08-12 2019-04-01 矽品精密工業股份有限公司 Electronic module
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