CN207489857U - Chip cloth wire encapsulation construction again - Google Patents
Chip cloth wire encapsulation construction again Download PDFInfo
- Publication number
- CN207489857U CN207489857U CN201721407174.5U CN201721407174U CN207489857U CN 207489857 U CN207489857 U CN 207489857U CN 201721407174 U CN201721407174 U CN 201721407174U CN 207489857 U CN207489857 U CN 207489857U
- Authority
- CN
- China
- Prior art keywords
- chip
- matrix
- wiring layer
- metal
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The utility model provides a kind of chip cloth wire encapsulation construction again, including matrix, mainly thes improvement is that：One surface of described matrix is equipped with cavity, and being made in a surface of matrix and cavity has metal wiring layer again；Chip welding metal again on the metal line of wiring layer in the cavity；Metal line of the contact downwards with chamber in-vivo metal wiring layer again that be electrically connected of chip is connect；Surface coating is equipped on a surface of matrix, covers a surface of described matrix, and chip is nuzzled surface coating completely；Correspond to the position opening for needing to set input/output port on surface coating, the input/output port being connect with metal wiring layer is equipped in opening.Wire structures are compact again for final multi-chip, can realize Ultrathin packaging, and encapsulation more cost performance is fanned out to than most of at present；It avoids and is bonded and tears open bonding complicated technology temporarily.
Description
Technical field
The utility model is related to system in package field, more particularly, to the wafer scale wire bond again of multi-chip wiring layer again
Structure.
Background technology
As chip functions become to become increasingly complex, I/O numbers are more and more, Fan-in（Fan-in）Encapsulation has been unable to meet I/
The requirement that O is fanned out to.Fan-out（It is fanned out to）Encapsulation technology is the supplement to fan-in encapsulation technologies, by way of structure disk again
Chip I/O port is drawn.Fan-out techniques began to apply in 2008, mainly the wireless eWLB of Infineon
(Embedded Wafer Level BGA) technology.As technology is gradually ripe, cost constantly reduces, while plus chip
The continuous promotion of technique, application are likely to occur explosive growth.
The Fan-out technological processes of Infineon are as follows：First chip is temporarily placed on wafer slide glass；Then it uses
Wafer level Shooting Technique, by chip buried in moulding compound, curing mold plastics, then remove wafer slide glass.Later to being embedded with chip
Moulding compound disk carry out wafer scale technique（Passivation, metal connect up and plant ball again）, finally slice completion encapsulation.
There are three major defects for the prior art：1, technological process is complicated（Introducing is bonded and tears open bonding temporarily）, need to put into
Technique and device resource are more；2, it is relatively low by first caused product cost；3, it is EMC materials using package main body, institute
All it is a big difficulty in production process with silicon wafer warpage and thicker product thickness.
Invention content
The purpose of the utility model is to overcome the deficiencies in the prior art, provide a kind of low cost, high yield, can
The chip cloth wire encapsulation construction again of multi-chip cloth wire encapsulation construction again is realized simultaneously.The technical solution adopted in the utility model is：
The realization technique of a kind of chip cloth wire encapsulation construction again, which is characterized in that include the following steps：
Step S1, provides matrix, cavity is formed in a surface etch of matrix, in a surface of matrix and cavity
It is middle to make metal wiring layer again；
Step S2, by chip welding metal again on the metal line of wiring layer in the cavity；The contact that is electrically connected of chip is downward
It is connect with the metal line of chamber in-vivo metal wiring layer again；
Step S3 is nuzzled chip surface coating by gluing or injection on a surface of matrix completely；
Step S4 is thinned to matrix required thickness to surface coating and/or by another surface of matrix；
Step S5 corresponds to the position opening for needing to set input/output port, then by opening on surface coating
Mouth makes and the metal input/output port that wiring layer is connect again.
Further, it is further included after step S5：
Step S6 increases layer protective layer on another surface of matrix.
Further, in step S1, a dielectric layer is set between matrix and metal again wiring layer, is made with playing isolation
With；It is initially formed dielectric layer and makes metal wiring layer again again.
Further, the material of matrix is silicon, glass, sapphire, ceramics or the mixing material based on above-mentioned material.
Further, wiring layer is one or more layers to metal again.
A kind of chip cloth wire encapsulation construction again, including matrix, mainly thes improvement is that：
One surface of described matrix is equipped with cavity, and being made in a surface of matrix and cavity has metal to connect up again
Layer；
Chip welding metal again on the metal line of wiring layer in the cavity；Chip be electrically connected contact downwards with it is golden in cavity
Belong to again the metal line connection of wiring layer；
Surface coating is equipped on a surface of matrix, covers a surface of described matrix, and chip is buried completely
Into surface coating；
Correspond to the position opening for needing to set input/output port on surface coating, be equipped with and metal in opening
The input/output port of wiring layer connection again.
Further, it is equipped with layer protective layer on another surface of matrix.
Further, wiring layer is one or more layers to metal again.
Further, a dielectric layer is equipped between matrix and metal again wiring layer.
The utility model has the advantage of：The utility model can realize low cost, height by the improvement of structure and technique
The multi-chip pin of yield wiring technique again；Wire structures are compact again for final multi-chip, Ultrathin packaging can be realized, than current
Most of to be fanned out to encapsulation more cost performance, while promote product yield, final products are safe and reliable.
Solve it is existing be fanned out to encapsulation using silicon or glass slide bring it is interim be bonded and tear open bonding complicated technology and
Cost problem, while avoid developing using the matching of new moulding material, it in addition also avoids wafer and is largely caused using plastic packaging material
Warpage issues.
Description of the drawings
Fig. 1 is that one surface of matrix of the utility model makes cavity and metal wiring layer schematic diagram again.
Fig. 2 is that the chip of the utility model welds schematic diagram in the cavity.
Fig. 3 is that the gluing of the utility model or injection form surface coating schematic diagram.
Fig. 4 is the reduction process schematic diagram of the utility model.
Fig. 5 is the making input/output port schematic diagram of the utility model.
Specific embodiment
With reference to specific drawings and examples, the utility model is described in further detail.
Chip cloth wire encapsulation construction again, is made by following processing step：
Step S1, as shown in Figure 1, matrix 1 is provided, on a surface 101 of matrix 1（A surface is in the present embodiment
Front）Etching forms cavity 2, and metal wiring layer 3 again are made in a surface of matrix 1 and cavity 2；
The material of matrix 1 can be silicon, glass, sapphire, ceramics or the mixing material based on above-mentioned material；Etching
The method of cavity 2 can be wet etching, dry etching or Mechanical lithography method；
If the material of matrix 1 is silicon, need to set a dielectric layer between matrix 1 and metal again wiring layer 3, with
Play buffer action；It is initially formed dielectric layer and makes metal wiring layer 3 again again；
Cavity 2 can be one or more, depending on number of chips；Multi-chip can be achieved at the same time again in the technique of the present embodiment
Cloth wire encapsulation construction；
Wiring layer 3 can be one or more layers to metal again；
Step S2, as shown in Fig. 2, chip 4 is welded in cavity 2 metal again on the metal line of wiring layer 3；Chip 4
Metal line of the contact 401 downwards with the wiring layer 3 again of metal in cavity 2 that be electrically connected connect；
The height of chip 4 can be higher by 2 upper edge of cavity or be flushed less than 2 upper edge of cavity or with 2 upper edge of cavity；
Step S3, as shown in figure 3, chip 4 is nuzzled surface completely by gluing or injection on a surface of matrix 1
Coating 5；
Step S4, as shown in figure 4, to surface coating 5 and/or by another surface 102 of matrix 1 to matrix 1（This
Another surface is the back side in embodiment）It is thinned to required thickness；
Step S5, as shown in figure 5, correspond to the position opening for needing to set input/output port on surface coating 5,
Then it is made and the metal input/output port 6 that wiring layer 3 is connect again by being open；
Soldered ball typically can be used in input/output port 6；
Optionally, step S6 increases layer protective layer, to improve the reliable of encapsulating structure on another surface 102 of matrix 1
Property.
Claims (4)
1. a kind of chip cloth wire encapsulation construction again, including matrix (1), it is characterised in that：
One surface of described matrix (1) is equipped with cavity (2), and being made in a surface (101) of matrix and cavity (2) has gold
Belong to wiring layer (3) again；
Chip (4) is welded on cavity (2) interior metal again on the metal line of wiring layer (3)；The contact that is electrically connected (401) of chip (4)
The metal line with cavity (2) interior metal wiring layer (3) again is connect downwards；
It is equipped with surface coating (5) on a surface of matrix (1), a surface of covering described matrix (1), and by chip
(4) it nuzzles completely surface coating (5)；
Correspond to the position opening for needing to set input/output port on surface coating (5), be equipped with and metal in opening
The input/output port (6) of wiring layer (3) connection again.
2. chip as described in claim 1 cloth wire encapsulation construction again, it is characterised in that：
On another surface (102) of matrix (1) equipped with layer protective layer.
3. chip as claimed in claim 1 or 2 cloth wire encapsulation construction again, it is characterised in that：
Wiring layer (3) is one or more layers to metal again.
4. chip as claimed in claim 1 or 2 cloth wire encapsulation construction again, it is characterised in that：
A dielectric layer is equipped between matrix (1) and metal again wiring layer (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721407174.5U CN207489857U (en) | 2017-10-27 | 2017-10-27 | Chip cloth wire encapsulation construction again |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721407174.5U CN207489857U (en) | 2017-10-27 | 2017-10-27 | Chip cloth wire encapsulation construction again |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207489857U true CN207489857U (en) | 2018-06-12 |
Family
ID=62477819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721407174.5U Active CN207489857U (en) | 2017-10-27 | 2017-10-27 | Chip cloth wire encapsulation construction again |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207489857U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110335852A (en) * | 2019-07-18 | 2019-10-15 | 上海先方半导体有限公司 | A kind of fan-out packaging structure and packaging method |
-
2017
- 2017-10-27 CN CN201721407174.5U patent/CN207489857U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110335852A (en) * | 2019-07-18 | 2019-10-15 | 上海先方半导体有限公司 | A kind of fan-out packaging structure and packaging method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200615 Address after: Room 987, Room 1303, 99 South Second Road, Songyu, Xiamen China (Fujian) Free Trade Experimental Zone, 361000 Patentee after: Xiamen Yun Tian Semiconductor Technology Co.,Ltd. Address before: Xishan Jing Hong Lu 214116 Jiangsu city of Wuxi province No. 58 East Industrial Park No. 45 Patentee before: WUXI GMAX MICROELECTRONICS Co.,Ltd. |