CN207425853U - A kind of electric resistance structure of ESD device series resistance - Google Patents
A kind of electric resistance structure of ESD device series resistance Download PDFInfo
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- CN207425853U CN207425853U CN201721552287.4U CN201721552287U CN207425853U CN 207425853 U CN207425853 U CN 207425853U CN 201721552287 U CN201721552287 U CN 201721552287U CN 207425853 U CN207425853 U CN 207425853U
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Abstract
The utility model provides a kind of electric resistance structure of ESD device series resistance, and polysilicon resistance is divided into N number of fraction, and upper metallization layer is connected to by corresponding Contact per sub-fraction；Per the Contact corresponding to sub-fraction and it is connected to upper metallization layer and constitutes a separate unit；The upper metallization layer uses metallic aluminum material；The Contact uses metallic aluminum material or aluminum alloy materials；It is ingenious to utilize existing structure using the thermal capacitance characteristic of metallic aluminium, adstante febre is being caused by same ESD electric currents, resistance will not caused to be damaged, meanwhile, circuit overall dimensions where ESD device can be substantially reduced.
Description
Technical field
The utility model is related to a kind of electric resistance structure of ESD device series resistance, more particularly to a kind of semiconductor chip
The electric resistance structure of ESD series resistances in circuit.
Background technology
In semiconductor circuit chip, sometimes, it would be desirable to one 10 ohm to 200 ohm of the string before ESD device
ploy（Polysilicon）Resistance, the effect of this resistance is to increase immunity of the ESD structures to chip exterior noise, in ground noise
It is more difficult to make ESD by positively biased in the environment of power supply noise.Since this poly resistance is connected in ESD paths, institute
With when ESD occurs, the electric current for having ampere grade passes through it.Therefore, in order to ensure that resistance is not damaged when ESD occurs
Bad, the area of this poly resistance usually requires to be designed to be quite big, to sponge the heat sent when ESD occurs, from
And prevent the damage of resistance device.
When ESD occurs, the main reason for damaging resistance device is to cause electrical resistance overheats because instantaneous power is excessive.It is right
For poly resistance, its thickness is often than relatively thin（Probably it is 0.2um ~ 0.3um thickness for example, in .18 techniques）.Therefore
With under homalographic it thermal capacitance it is limited.If its area is not big enough, ESD electric currents, which flow through the energy sent when it, can make it
Fast heating causes to damage more than its fusing point, therefore, largely constrains the layout size of the resistance circuit.
Utility model content
The technical problem to be solved by the present invention is to provide a kind of circuit overall dimensions where being substantially reduced ESD device
ESD device series resistance electric resistance structure, and can ensure that, when ESD occurs, the series resistance of ESD device is not damaged
It is bad.
The technical solution adopted in the utility model is as follows：
Polysilicon resistance, is divided into N number of fraction by a kind of electric resistance structure of ESD device series resistance, equal per sub-fraction
Upper metallization layer is connected to by corresponding Contact；Per the Contact corresponding to sub-fraction and it is connected to top gold
Belong to layer and constitute a separate unit；The upper metallization layer uses metallic aluminum material；The Contact uses metallic aluminum material
Or aluminum alloy materials；The N is approximately equal to 2 natural number.
Via structures are further included, upper metallization layer is connected to by corresponding Contact and Via per sub-fraction；
Per the Contact corresponding to sub-fraction and Via and it is connected to upper metallization layer and constitutes a separate unit；The Via and
Upper metallization layer uses metallic aluminum material；The Contact uses metallic aluminum material or aluminum alloy materials；The N is about etc.
In 2 natural number.
The upper metallization layer includes the first metal layer and metal layer at top, and Contact is connected to by the first metal layer
Via, and Via is connected to top layer metallic layer.
Between the adjacent separate unit, the Edge Distance between Contact is between 4um ~ 8um.
Edge Distance between the Contact is 6um.
The flat shape of the upper metallization layer is square or rectangular.
Compared with prior art, the beneficial effects of the utility model are：It is ingenious using existing using the thermal capacitance characteristic of metallic aluminium
There is structure, when ensureing that ESD occurs, resistance is not impaired simultaneously, greatly reduces circuit overall dimensions where ESD device.
Description of the drawings
Fig. 1 is the process structure diagrammatic cross-section of the utility model wherein embodiment.
Fig. 2 is the top-level metallic floor map of embodiment illustrated in fig. 1.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, is further elaborated the utility model.It should be appreciated that specific embodiment described herein is only explaining this
Utility model is not used to limit the utility model.
This specification（Including any summary and attached drawing）Disclosed in any feature, unless specifically stated, can be by other
Equivalent or with similar purpose alternative features are replaced.I.e., unless specifically stated, each feature is a series of equivalent
An or example in similar characteristics.
Specific embodiment 1
Polysilicon resistance, is divided into N number of fraction by a kind of electric resistance structure of ESD device series resistance, equal per sub-fraction
Upper metallization layer is connected to by corresponding Contact；Per the Contact corresponding to sub-fraction and it is connected to top gold
Belong to layer and constitute a separate unit；The upper metallization layer uses metallic aluminum material；The Contact uses metallic aluminum material
Or aluminum alloy materials；The N is approximately equal to 2 natural number.
Specific embodiment 2
On the basis of specific embodiment 1, as shown in Figure 1, further including Via structures, polysilicon resistance 1 is divided into N number of small
Part is connected to upper metallization layer per sub-fraction by corresponding Contact 2 and Via 3；Per sub-fraction institute
It corresponding Contact and Via and is connected to upper metallization layer and constitutes a separate unit；The Via and upper metallization layer are adopted
Use metallic aluminum material；The Contact uses metallic aluminum material or aluminum alloy materials；The N is the natural number more than or equal to 2.
880 J/ of thermal capacitance (kg DEG C) of metallic aluminium, 700 J/ (kg DEG C) suitable with polysilicon.And common
In technique, the thickness of metal can accomplish 3um thickness, and polysilicon thickness is only thick 1/10th of metal.Therefore identical face
Under product, the big magnitude of the heat capacity ratio polysilicon of metal.It the fact that utilization, can be polysilicon and metallic combination one
It rises, under smaller area, obtains suitable resistance and suitable thermal capacitance.
In this embodiment, using existing metal layer, polysilicon resistance is divided into many small parts, Mei Yi little
The thicker metal of a fritter, that is, existing aluminum metal layer are carried on the back in part by Contact and Via, utilize the heat of metallic aluminium
Hold characteristic, it is ingenious using existing structure, adstante febre is being caused by same ESD electric currents, resistance will not caused to be damaged, together
When, circuit overall dimensions where ESD device can be substantially reduced.
Specific embodiment 3
On the basis of specific embodiment 2, as shown in Figure 1, in this embodiment, the upper metallization layer includes the
One metal layer 4 and metal layer at top 5, Contact is connected to Via by the first metal layer, and Via is connected to top layer metallic layer.
It can be specifically configured according to actual conditions process condition, it is similary suitable when there is more than two layers Via or three layer or more metal layer
With.
Specific embodiment 4
On the basis of one of specific embodiment 1 to 3, between the adjacent separate unit, the edge between Contact
Distance is between 4um ~ 8um.
The density that metal is set in principle is to be the bigger the better.Certain area can be occupied yet with Contact, it is too close
Metal can cause area requirements bigger.If density is too sparse, but can cause poly between metal and metal fever when
Waiting heat can not disperse.Through calculating, in this embodiment, the Edge Distance between Contact be arranged on 4um ~ 8um it
Between.
Specific embodiment 5
On the basis of specific embodiment 4, in this embodiment, the Edge Distance between the Contact is
6um。
Specific embodiment 6
On the basis of one of specific embodiment 1 to 5, the flat shape of the upper metallization layer is square or rectangular
Shape.In the embodiment depicted in figure 2, top-level metallic is positive direction, however may be set to be square or strip.
Claims (6)
1. a kind of electric resistance structure of ESD device series resistance, it is characterised in that：Polysilicon resistance is divided into N number of fraction, it is each
Fraction is connected to upper metallization layer by corresponding Contact；Contact and connection corresponding to per sub-fraction
A separate unit is constituted to upper metallization layer；The upper metallization layer uses metallic aluminum material；The Contact is using gold
Belong to aluminum material or aluminum alloy materials；The N is the natural number more than or equal to 2.
2. the electric resistance structure of ESD device series resistance according to claim 1, it is characterised in that：Via structures are further included,
Upper metallization layer is connected to by corresponding Contact and Via per sub-fraction；Corresponding to per sub-fraction
It Contact and Via and is connected to upper metallization layer and constitutes a separate unit；The Via and upper metallization layer use metal
Aluminum material；The Contact uses metallic aluminum material or aluminum alloy materials；The N is the natural number more than or equal to 2.
3. the electric resistance structure of ESD device series resistance according to claim 2, it is characterised in that：The upper metallization layer
Including the first metal layer and metal layer at top, Contact is connected to Via by the first metal layer, and Via is connected to top-level metallic
Layer.
4. the electric resistance structure of the ESD device series resistance according to one of Claim 1-3, it is characterised in that：Adjacent institute
Between stating separate unit, the Edge Distance between Contact is between 4um ~ 8um.
5. the electric resistance structure of ESD device series resistance according to claim 4, it is characterised in that：The Contact it
Between Edge Distance be 6um.
6. the electric resistance structure of the ESD device series resistance according to one of Claim 1-3, it is characterised in that：The top
The flat shape of metal layer is square or rectangular.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721552287.4U CN207425853U (en) | 2017-11-20 | 2017-11-20 | A kind of electric resistance structure of ESD device series resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721552287.4U CN207425853U (en) | 2017-11-20 | 2017-11-20 | A kind of electric resistance structure of ESD device series resistance |
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| Publication Number | Publication Date |
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| CN207425853U true CN207425853U (en) | 2018-05-29 |
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| CN201721552287.4U Active CN207425853U (en) | 2017-11-20 | 2017-11-20 | A kind of electric resistance structure of ESD device series resistance |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731795A (en) * | 2017-11-20 | 2018-02-23 | 清华四川能源互联网研究院 | A kind of electric resistance structure of ESD device series resistance |
-
2017
- 2017-11-20 CN CN201721552287.4U patent/CN207425853U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731795A (en) * | 2017-11-20 | 2018-02-23 | 清华四川能源互联网研究院 | A kind of electric resistance structure of ESD device series resistance |
| CN107731795B (en) * | 2017-11-20 | 2019-10-25 | 清华四川能源互联网研究院 | A kind of electric resistance structure of ESD device series resistance |
| US11127677B2 (en) | 2017-11-20 | 2021-09-21 | Sichuan Energy Internet Research Institute, Tsinghua University | Resistor structure of series resistor of ESD device |
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