CN207410328U - A kind of Pipeline SAR-ADC circuits - Google Patents
A kind of Pipeline SAR-ADC circuits Download PDFInfo
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- CN207410328U CN207410328U CN201721636359.3U CN201721636359U CN207410328U CN 207410328 U CN207410328 U CN 207410328U CN 201721636359 U CN201721636359 U CN 201721636359U CN 207410328 U CN207410328 U CN 207410328U
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Abstract
The utility model discloses a kind of Pipeline SAR adc circuits, including prime sampling comparison circuit, rear class sampling comparison circuit, Digital Logic control module and two register modules, wherein, prime sampling comparison circuit includes first comparator, first switch, second switch, m prime anode compares branch and m prime negative terminal compares branch.Rear class sampling comparison circuit include the second comparator, the 3rd switch, the 4th switch, n articles of rear class anode compares branch and n articles of rear class negative terminal compares branch.Preceding m input interfaces of the output terminal connection Digital Logic control module of first comparator, rear n input interfaces of the output terminal connection Digital Logic control module of the second comparator.The input interface of one register module is connected with the preceding m bit digitals interface of Digital Logic control module, and the input interface of another register module is connected with the rear n bit digitals interface of Digital Logic control module.The utility model is few using component, is easy to implement, can promote output speed and resolution ratio.
Description
Technical field
The utility model is related to technical field of integrated circuits, are specifically a kind of Pipeline SAR-ADC circuits.
Background technology
Analog-digital converter (ADC) is as the Primary Component for converting analog signals into digital signal, in aerospace with preventing
The fields such as business, automobile application, software radio, consumer electronics, video monitoring and Image Acquisition, radar communication play heavy to closing
The effect wanted.With the continuous development of modern technologies, requirement of these fields to speed and resolution ratio is constantly promoted, and modulus is turned
The requirement of parallel operation is also higher and higher.
Traditional analog-digital converter usually uses two kinds of structures of Pipeline-ADC and SAR-ADC, wherein, Pipeline-
ADC structures have the following disadvantages when applying：Firstth, Pipeline-ADC is affected by capacitance mismatch, this causes
Pipeline-ADC resolution ratio is very restricted；Second, Pipeline-ADC need to be equipped with error correction module, this can increase
Add the power consumption and area of ADC, limit its application in fields such as Industry Controls.SAR-ADC structures have the following disadvantages when applying：
Because SAR-ADC uses the voltage comparative approach of successive approximation type, cause it that can not be used in the environment of high speed, i.e. SAR-ADC
Sampling rate it is low.
Utility model content
The purpose of this utility model is that solve the problems, such as that traditional analog-digital converter is low low with sampling rate there are resolution ratio,
A kind of Pipeline SAR-ADC circuits are provided, there is the combination of Pipeline and SAR-ADC structures, can be promoted defeated
Go out rate and resolution ratio.
The utility model, which solves the above problems, to be achieved through the following technical solutions：A kind of Pipeline SAR-ADC electricity
Road samples comparison circuit, Digital Logic control module and register module, before described including prime sampling comparison circuit, rear class
Grade sampling comparison circuit includes first comparator, first switch, second switch, m prime anode compares branch and m prime is born
Branch is compared at end, and described first switch one end is used for input difference voltage, and the other end connects with first comparator in-phase input end
It connects；Described second switch one end is used for input difference voltage, and the other end is connected with first comparator inverting input；
The rear class sampling comparison circuit includes the second comparator, the 3rd switch, the 4th switch, n articles of rear class anode and compares
Branch and n rear class negative terminal compare branch, and described 3rd switch one end is connected to first comparator in-phase input end and is opened with first
On circuit between pass, for input difference formula residual error voltage, the other end is connected with the second comparator in-phase input end；It is described
4th switch one end is connected on the circuit between first comparator inverting input and second switch, residual for input difference formula
Potential difference, the other end are connected with the second comparator inverting input；
Preceding m input interfaces of the output terminal connection Digital Logic control module of the first comparator, second ratio
Compared with rear n input interfaces of the output terminal connection Digital Logic control module of device；The quantity of the register module be two, one
The input interface of a register module is connected with the preceding m bit digitals interface of Digital Logic control module, another register module
Input interface be connected with the rear n bit digitals interface of Digital Logic control module；Wherein, m and n is more than or equal to 1 just
Integer；
The prime anode compares branch, prime negative terminal compares branch, rear class anode compares branch and rear class negative terminal compares
Three switches that branch includes a capacitance and is connected with the capacitance the same end, the switch described in three connect capacitance terminal relatively
The other end be respectively used to input high reference voltage, low reference voltage, the common-mode voltage of height reference voltage；Before described in m items
Grade anode compares in branch capacitance and is connected to first comparator in-phase input end with respect to the other end at connecting valve end, described in m items
Prime negative terminal compare capacitance in branch and be connected to first comparator inverting input, n items with respect to the other end at connecting valve end
The rear class anode compares capacitance in branch and is connected to the second comparator in-phase input end with respect to the other end at connecting valve end,
Rear class negative terminal described in n items compares capacitance in branch and is connected to the second comparator anti-phase input with respect to the other end at connecting valve end
End.
Further, the rear class sampling comparison circuit further includes voltage amplifier circuit, and the voltage amplifier circuit is equipped with
Two input terminals and two output terminals, one input terminal are connected between first comparator in-phase input end and first switch
On circuit, another input terminal is connected on the circuit between first comparator inverting input and second switch；Described 3rd
The other end of both switch and the 4th switch the second comparator terminal of opposite connection and two output terminals of voltage amplifier circuit are one by one
It is correspondingly connected with.In this way, the utility model the 3rd switch especially by be connected on voltage amplifier circuit output terminal and first ratio
Compared with the connection between device in-phase input end and first switch, the 4th switch is exported especially by voltage amplifier circuit is connected to
Connection on end between first comparator inverting input and second switch.The utility model is in application, rear class samples
The differential type residual error voltage that comparison circuit receives output difference fraction voltage after voltage amplifier circuit amplifies.
In conclusion the utility model has the advantages that：(1) the utility model overall structure is simple, uses member
Device is few, is easy to implement, at low cost, and the utility model is combined using SAR-ADC circuit structures and Pipeline function modes,
The output speed of ADC can effectively be improved.
(2) the utility model uses the structure of full differential, can reduce the interference of noise and capacitance mismatch to circuit.
(3) progressively range is carried out when the utility model is applied to divide, it can be gamut from maximum m positions to minimum n positions
It is divided, then every grade of conversion for all carrying out SAR-ADC forms the restructuring output of Pipeline (assembly line) form so that most
The resolution ratio exported eventually is greatly promoted.
Description of the drawings
Attached drawing described herein is used for providing further understanding the utility model embodiment, forms the one of the application
Part does not form the restriction to the utility model embodiment.In the accompanying drawings：
Fig. 1 is the circuit diagram of one specific embodiment of the utility model；
Fig. 2 is the global voltage simulation result schematic diagram of one specific embodiment of the utility model；
Fig. 3 is the local voltage simulation result schematic diagram of one specific embodiment of the utility model.
Specific embodiment
For the purpose of this utility model, technical solution and advantage is more clearly understood, with reference to embodiment and attached drawing,
The utility model is described in further detail, and the exemplary embodiment and its explanation of the utility model are only used for explaining this
Utility model is not intended to limit the scope of the present invention.
Embodiment：
As shown in Figure 1, a kind of Pipeline SAR-ADC circuits, compare including prime sampling comparison circuit, rear class sampling
Circuit, Digital Logic control module and register module, prime sampling comparison circuit include first comparator CMP1, first switch
S1, second switch S2, m prime anode compares branch and m prime negative terminal compares branch, wherein, m is more than or equal to 1 just
Integer.First switch S1One end is used for input difference voltage Vip, the other end and first comparator CMP1In-phase input end connects.
Second switch S2One end is used for input difference voltage Vin, the other end and first comparator CMP1Inverting input connects.
The rear class sampling comparison circuit of the present embodiment includes the second comparator CMP2, voltage amplifier circuit, the 3rd switch S3、
4th switch S4, n rear class anode compares branch and n rear class negative terminal compares branch, wherein, n is just whole more than or equal to 1
Number.Voltage amplifier circuit sets to be connected to first comparator CMP there are two input terminal and two output terminals, one input terminal1Together
Phase input terminal and first switch S1Between circuit on, for input difference formula residual error voltage Vp1, another input terminal is connected to
First comparator CMP1Inverting input and second switch S2Between circuit on, for input difference formula residual error voltage Vn1.Electricity
Amplifying circuit is pressed to distinguish output difference fraction voltage V by two output terminal by after differential type residual error voltage amplificationp2、Vn2.This reality
Apply the 3rd switch S of example3One output terminal of one end and voltage amplifier circuit connects, for input difference formula voltage Vp2, it is another
One end and the second comparator CMP2In-phase input end connects.The 4th switch S of the present embodiment4One end and the one of voltage amplifier circuit
A output terminal connection, for input difference formula voltage Vn2, the other end and the second comparator CMP2Inverting input connects.
The first comparator CMP of the present embodiment1Output terminal connection Digital Logic control module preceding m input interfaces,
Second comparator CMP2Output terminal connection Digital Logic control module rear n input interfaces.Register mould in the present embodiment
The quantity of block is two, and the input interface of a register module is connected with the preceding m bit digitals interface of Digital Logic control module,
The input interface of another register module is connected with the rear n bit digitals interface of Digital Logic control module.
The prime anode of the present embodiment compares branch, prime negative terminal compares branch, rear class anode compares branch and rear class is born
Three switches that branch includes a capacitance and is connected with the capacitance the same end are compared at end, and three switches are opposite in every branch
The other end of connection capacitance terminal is respectively used to input high reference voltage Vrp, low reference voltage Vrn, height reference voltage common mode electricity
Press Vcm。
M prime anode compares capacitance in branch and is connected to the first ratio with respect to the other end at connecting valve end in the present embodiment
Compared with device CMP1In-phase input end, wherein, the capacitance that first prime anode compares in branch is Ca, for controlling high reference voltage
VrpThe switch whether accessed is SMpH(1), for controlling low reference voltage VrnThe switch whether accessed is SMnL(1), for controlling height
The common-mode voltage V of low reference voltagecmThe switch whether accessed is SMca(1)；The capacitance that the m-1 articles prime anode compares in branch is
2m-1Ca, for controlling high reference voltage VrpThe switch whether accessed is SMpH(m-1), for controlling low reference voltage VrnWhether connect
The switch entered is SMnL(m-1), for controlling the common-mode voltage V of height reference voltagecmThe switch whether accessed is SMca(m-1)；M
The capacitance that prime anode compares in branch is 2mCa, for controlling high reference voltage VrpThe switch whether accessed is SMpH(m), use
In the low reference voltage V of controlrnThe switch whether accessed is SMnL(m), for controlling the common-mode voltage V of height reference voltagecmWhether
The switch of access is SMca(m)。
M prime negative terminal compares capacitance in branch and is connected to the first ratio with respect to the other end at connecting valve end in the present embodiment
Compared with device CMP1Inverting input, wherein, the capacitance that first prime negative terminal compares in branch is Cb, for controlling high reference voltage
VrpThe switch whether accessed is SMpL(1), for controlling low reference voltage VrnThe switch whether accessed is SMnH(1), for controlling height
The common-mode voltage V of low reference voltagecmThe switch whether accessed is SMcb(1)；The capacitance that the m-1 articles prime negative terminal compares in branch is
2m-1Cb, for controlling high reference voltage VrpThe switch whether accessed is SMpL(m-1), for controlling low reference voltage VrnWhether connect
The switch entered is SMnH(m-1), for controlling the common-mode voltage V of height reference voltagecmThe switch whether accessed is SMcb(m-1)；M
The capacitance that prime negative terminal compares in branch is 2mCb, for controlling high reference voltage VrpThe switch whether accessed is SMpL(m), use
In the low reference voltage V of controlrnThe switch whether accessed is SMnH(m), for controlling the common-mode voltage V of height reference voltagecmWhether
The switch of access is SMcb(m)。
N rear class anode compares capacitance in branch and is connected to the second ratio with respect to the other end at connecting valve end in the present embodiment
Compared with device CMP2In-phase input end, wherein, the capacitance that first rear class anode compares in branch is Cc, for controlling high reference voltage
VrpThe switch whether accessed is SLpH(1), for controlling low reference voltage VrnThe switch whether accessed is SLnL(1), for controlling height
The common-mode voltage V of low reference voltagecmThe switch whether accessed is SLcc(1)；The capacitance that (n-1)th rear class anode compares in branch is
2n-1Cc, for controlling high reference voltage VrpThe switch whether accessed is SLpH(n-1), for controlling low reference voltage VrnWhether connect
The switch entered is SLnL(n-1), for controlling the common-mode voltage V of height reference voltagecmThe switch whether accessed is SLcc(n-1)；N-th
The capacitance that rear class anode compares in branch is 2nCc, for controlling high reference voltage VrpThe switch whether accessed is SLpH(n), use
In the low reference voltage V of controlrnThe switch whether accessed is SLnL(n), for controlling the common-mode voltage V of height reference voltagecmWhether
The switch of access is SLcc(n)。
N rear class negative terminal compares capacitance in branch and is connected to the second ratio with respect to the other end at connecting valve end in the present embodiment
Compared with device CMP2Inverting input, wherein, the capacitance that first rear class anode compares in branch is Cd, for controlling high reference voltage
VrpThe switch whether accessed is SLpL(1), for controlling low reference voltage VrnThe switch whether accessed is SLnH(1), for controlling height
The common-mode voltage V of low reference voltagecmThe switch whether accessed is SLcd(1)；The capacitance that (n-1)th rear class anode compares in branch is
2n-1Cd, for controlling high reference voltage VrpThe switch whether accessed is SLpL(n-1), for controlling low reference voltage VrnWhether connect
The switch entered is SLnH(n-1), for controlling the common-mode voltage V of height reference voltagecmThe switch whether accessed is SLcd(n-1)；N-th
The capacitance that rear class anode compares in branch is 2nCd, for controlling high reference voltage VrpThe switch whether accessed is SLpL(n), use
In the low reference voltage V of controlrnThe switch whether accessed is SLnH(n), for controlling the common-mode voltage V of height reference voltagecmWhether
The switch of access is SLcd(n)。
The present embodiment is in application, in sample phase m first, first switch S1, second switch S2It is closed, the simulation of input
Signal Vip、VinBy switching S1And S2Into the capacitor array of m.All connection VcmSwitch SMca(1)…SMca(m), SMcb(1)…
SMcb(m), SLcc(1)…SLcc(n), SLcd(1)…SLcd(n)It is all closed, rest switch SMpH(1)…SMpH(m),SMpL(1)…SMpL(n),
SMnH(1)…SMnH(m), SMnL(1)…SMnL(m),SLpH(1)…SLpH(n),SLpL(1)…SLpL(n),SLnH(1)…SLnH(n),SLnL(1)…SLnL(n)
It is all off.In the preceding m bit comparisons stage, S is switched1, S2It disconnects.In m bit comparisons, if first comparator CMP1Anode electricity
Pressure is more than negative terminal voltage, first comparator CMP1High level is exported, then switchs SMpH(m), SMnH(m)It is closed, switchs SMpL(m), SMnL(m)
It disconnects, while S will be switchedMca(m),SMcb(m)It disconnects so that 2mCaBy VrpIt recharges, 2mCbBy VrnIt recharges, eliminates sampling
Stage, input signal was 2mCaWith 2mCbThe m positions charge filled, then Digital Logic control module just lock highest order DmFor logic
' 1 ' arrives output register module.If comparator CMP1Positive terminal voltage be less than negative terminal voltage, comparator CMP1Low level is exported, then
Switch SMpL(m), SMnL(m)It is closed, switchs SMpH(m), SMnH(m)It disconnects, while S will be switchedMca(m),SMcb(m)It disconnects so that 2mCaQuilt
VrnIt recharges, 2mCbBy VrpIt recharges, eliminates sample phase input signal 2mCaWith 2mCbThe m positions charge filled, then
Digital Logic control module just locks highest order DmOutput register module is arrived for logic ' 0 '.After the charge of m is eliminated, than
Compared with device CMP1The voltage of positive and negative terminal just carries out (m-1) bit comparison rank of next step according to the voltage of (m-1) position of input signal
Section.In (m-1) bit comparison, if comparator CMP1Positive terminal voltage be more than negative terminal voltage, comparator CMP1Export high level,
Then switch SMpH(m-1), SMnH(m-1)It is closed, switchs SMpL(m-1),SMnL(m-1)It disconnects, while S will be switchedMca(m-1),SMcb(m-1)It disconnects,
So that 2m-1CaBy VrpIt recharges, 2m-1CbBy VrnIt recharges, eliminates sample phase input signal 2m-1CaWith 2m-1CbIt is filled
(m-1) position charge, then Digital Logic control module just lock highest order Dm-1Output register module is arrived for logic ' 1 '.If
Comparator CMP1Positive terminal voltage be less than negative terminal voltage, comparator CMP1Low level is exported, then switchs SMpL(m-1), SMnL(m-1)It closes
It closes, switchs SMpH(m-1),SMnH(m-1)It disconnects, while S will be switchedMca(m-1),SMcb(m-1)It disconnects so that 2m-1CaBy VrnIt recharges,
2m-1CbBy VrpIt recharges, eliminates sample phase input signal 2m-1CaWith 2m-1Cb(m-1) position charge filled, then logic
Control just locks highest order Dm-1Output register module is arrived for logic ' 0 '.(m-1) after the charge of position is eliminated, and then with regard to carrying out
(m-2) bit comparison stage of next step, and so on, (1) position to the last.It is completeer it is m first after, system is posted
Numeric results D in buffer modulem…D1With the residual error voltage V of last positionp1,Vn1。
In rear n sample phase, S is switched3,S4It is closed, the analog signal V of inputp2, Vn2By switching S3, S4Into n
The capacitor array of position.In the preceding n bit comparisons stage, S is switched3, S4It disconnects.In the n-th bit comparison, if comparator CMP2Anode electricity
Pressure is more than negative terminal voltage, comparator CMP2High level is exported, then switchs SLpH(n), SLnH(n)It is closed, switchs SLpL(n), SLnL(n)It is disconnected
It opens, while S will be switchedLcc(n),SLcd(n)It disconnects so that 2nCcBy VrpIt recharges, 2nCdBy VrnIt recharges, eliminates sampling rank
Section input signal is 2nCcWith 2nCdThe n positions charge filled, then Digital Logic control module just lock highest order DnFor logic ' 1 '
To output register module.If comparator CMP2Positive terminal voltage be less than negative terminal voltage, comparator CMP2Low level is exported, then is opened
Close SLpL(n), SLnL(n)It is closed, switchs SLpH(n), SLnH(n)It disconnects, while S will be switchedLcc(n),SLcd(n)It disconnects so that 2nCcBy Vrn
It recharges, 2nCdBy VrpIt recharges, eliminates sample phase input signal 2nCcWith 2nCdThe n positions charge filled, is then patrolled
Collect control just locking highest order DnOutput register module is arrived for logic ' 0 '.After the charge of n is eliminated, comparator CMP2It is positive and negative
The voltage at end just carries out (n-1) bit comparison stage of next step according to the voltage of (n-1) position of input signal.At (n-1)
During bit comparison, if comparator CMP2Positive terminal voltage be more than negative terminal voltage, comparator CMP2High level is exported, then is switched
SLpH(n-1), SLnH(n-1)It is closed, switchs SLpL(n-1),SLnL(n-1)It disconnects, while S will be switchedLcc(n-1),SLcd(n-1)It disconnects so that 2n- 1CcBy VrpIt recharges, 2n-1CdBy VrnIt recharges, eliminates sample phase input signal 2n-1CcWith 2n-1Cd(the n- filled
1) position charge, then Digital Logic control module just lock highest order Dn-1Output register module is arrived for logic ' 1 '.If compare
Device CMP2Positive terminal voltage be less than negative terminal voltage, comparator CMP2Low level is exported, then switchs SLpL(n-1), SLnL(n-1)It is closed, opens
Close SLpH(n-1),SLnH(n-1)It disconnects, while S will be switchedLcc(n-1),SLcd(n-1)It disconnects so that 2n-1CcBy VrnIt recharges, 2n-1Cd
By VrpIt recharges, eliminates sample phase input signal 2n-1CcWith 2n-1Cd(n-1) position charge filled, then logic control
With regard to locking highest order Dn-1Output register module is arrived for logic ' 0 '.(n-1) after the charge of position is eliminated, and then just carry out next
(n-2) bit comparison stage of step, and so on, (1) position to the last.After completeer after n, system obtains register
Mould numeric results D in the blockn…D1。
Finally by two register modules in the form of Pipeline (assembly line) by first m and the final number of rear n bit combinations
Word signal results.
The present embodiment is applied and realizes 16 Pipeline SAR-ADC circuit structures, and sampling rate is
33kHz, reference voltage 2.5V, input signal are changed to 2.5V from 0V.Output result reaches 16 for number of significant digit (ENOB),
Integral nonlinearity (INL) is less than 0.5LSB, and differential nonlinearity (DNL) is less than 0.5LSB.Fig. 2 and Fig. 3 is a reality of the circuit
Example application simulation figure.Emulation mode is that the output digit signals of 16 Pipeline SAR-ADC circuit structures are passed through a reason
The DAC thought, by the analog signal of DAC outputs compared with the analog signal inputted.Top wherein in coordinate system shown in Fig. 2
Lines are the voltage input signals that 2.5V is changed to from 0V, and the lines of lower section are the moulds that the circuit is converted by output digit signals
Intend signal.As can be seen from Figure 2, the voltage output signal of the circuit is changed linearly and is consistent substantially with voltage input signal.Fig. 3
For local voltage simulation result figure, more smooth lines are the analog signals of input, and more zigzag is by exporting
The analog signal that digital signal is converted into.By Tu Ke get, rank is presented in the analog signal being converted by the digital signal exported substantially
Scalariform meets expection.
Above-described specific embodiment, the purpose of this utility model, technical solution and advantageous effect have been carried out into
One step is described in detail, it should be understood that the foregoing is merely specific embodiment of the present utility model, is not used to limit
Determine the scope of protection of the utility model, within the spirit and principle of the utility model, any modification for being made equally is replaced
It changes, improve, should be included within the scope of protection of this utility model.
Claims (2)
1. a kind of Pipeline SAR-ADC circuits, which is characterized in that more electric including prime sampling comparison circuit, rear class sampling
Road, Digital Logic control module and register module, the prime sampling comparison circuit include first comparator (CMP1), first
Switch (S1), second switch (S2), m prime anode compares branch and m prime negative terminal compares branch, the first switch
(S1) one end is for input difference voltage, the other end and first comparator (CMP1) in-phase input end connection；The second switch
(S2) one end is for input difference voltage, the other end and first comparator (CMP1) inverting input connection；
The rear class sampling comparison circuit includes the second comparator (CMP2), the 3rd switch (S3), the 4th switch (S4), n rear class
Anode compares branch and n rear class negative terminal compares branch, the 3rd switch (S3) one end is connected to first comparator (CMP1) same
Phase input terminal and first switch (S1) between circuit on, for input difference formula residual error voltage, the other end is compared with second
Device (CMP2) in-phase input end connection；4th switch (the S4) one end is connected to first comparator (CMP1) inverting input with
Second switch (S2) between circuit on, for input difference formula residual error voltage, the other end and the second comparator (CMP2) reverse phase
Input terminal connects；
First comparator (the CMP1) output terminal connection Digital Logic control module preceding m input interfaces, it is described second compare
Compared with device (CMP2) output terminal connection Digital Logic control module rear n input interfaces；The quantity of the register module is
Two, the input interface of a register module is connected with the preceding m bit digitals interface of Digital Logic control module, another deposit
The input interface of device module is connected with the rear n bit digitals interface of Digital Logic control module；Wherein, m and n is to be greater than or equal to
1 positive integer；
The prime anode compares branch, prime negative terminal compares branch, rear class anode compares branch and rear class negative terminal compares branch
Three switches for including a capacitance and being connected with the capacitance the same end, the switch described in three connect the another of capacitance terminal relatively
One end is respectively used to input high reference voltage, low reference voltage, the common-mode voltage of height reference voltage；Prime described in m items is just
Compare capacitance in branch and be connected to first comparator (CMP with respect to the other end at connecting valve end in end1) in-phase input end, m items institute
The prime negative terminal stated compares capacitance in branch and is connected to first comparator (CMP with respect to the other end at connecting valve end1) reverse phase is defeated
Enter end, the rear class anode described in n items compares capacitance in branch and is connected to the second comparator with respect to the other end at connecting valve end
(CMP2) in-phase input end, the rear class negative terminal described in n items compares capacitance in branch and is connected to respect to the other end at connecting valve end
Second comparator (CMP2) inverting input.
2. a kind of Pipeline SAR-ADC circuits according to claim 1, which is characterized in that the rear class sampling is compared
Circuit further includes voltage amplifier circuit, and the voltage amplifier circuit is set there are two input terminal and two output terminals, one input
End is connected to first comparator (CMP1) in-phase input end and first switch (S1) between circuit on, another input terminal connection
In first comparator (CMP1) inverting input and second switch (S2) between circuit on；3rd switch (the S3) and the 4th
Switch (S4) the second comparator (CMP of the opposite connection of the two2) end the other end and voltage amplifier circuit two output terminals one it is a pair of
It should connect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721636359.3U CN207410328U (en) | 2017-11-29 | 2017-11-29 | A kind of Pipeline SAR-ADC circuits |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721636359.3U CN207410328U (en) | 2017-11-29 | 2017-11-29 | A kind of Pipeline SAR-ADC circuits |
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|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108075778A (en) * | 2017-11-29 | 2018-05-25 | 四川知微传感技术有限公司 | A kind of Pipeline SAR-ADC circuit structures |
-
2017
- 2017-11-29 CN CN201721636359.3U patent/CN207410328U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108075778A (en) * | 2017-11-29 | 2018-05-25 | 四川知微传感技术有限公司 | A kind of Pipeline SAR-ADC circuit structures |
| CN108075778B (en) * | 2017-11-29 | 2023-10-27 | 四川知微传感技术有限公司 | Pipeline SAR-ADC circuit structure |
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