CN2073169U - Grid protector of power mos device - Google Patents
Grid protector of power mos device Download PDFInfo
- Publication number
- CN2073169U CN2073169U CN 90216873 CN90216873U CN2073169U CN 2073169 U CN2073169 U CN 2073169U CN 90216873 CN90216873 CN 90216873 CN 90216873 U CN90216873 U CN 90216873U CN 2073169 U CN2073169 U CN 2073169U
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- Prior art keywords
- protection tube
- grid
- power mos
- metal oxide
- oxide semiconductor
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Abstract
The utility model relates to a grid protector of a power MOS device which belongs to the technical field of the semi-conductor device. The utility model is characterized in that in the terminal, the substrate of the silicon single crystal is manufactured with a protection tube, and the one pole of the protection tube is connected with the grid pole of the power MOS device by an aluminum bar.
Description
The utility model relates to a kind of grid protection tube of power MOS (Metal Oxide Semiconductor) device, belongs to field of semiconductor devices.
Power MOS (Metal Oxide Semiconductor) device comprises pure power MOS (Metal Oxide Semiconductor) device and MOS---bipolar device such as VVMOS, VDMOS, IGBT, MCT, DCT, MOS---GTO or the like makes separately usually, and the input protection pipe with grid is not integrated in the chip simultaneously.The input pipe of grid also is independent making, links to each other with power MOS pipe with outer lead then.Because the grid region of power MOS (Metal Oxide Semiconductor) device is tightly surrounded by source region and termination environment, does not have the space to add protection tube, so the protection tube and the power MOS (Metal Oxide Semiconductor) device of grid are not integrated on the same chip usually.Because power MOS (Metal Oxide Semiconductor) device does not add the grid protection tube, the grid ratio is easier to be caused component failure by electrostatic breakdown.Japan new product 2SK557(belongs to the VDMOS pipe) adopt polysilicon to make PN junction protection diode.Because the diffusion coefficient of impurity is than much bigger in monocrystalline silicon in polysilicon; just be difficult to manufacturing process compatibility so make the PN junction protection tube with power MOS (Metal Oxide Semiconductor) device with polysilicon; need to increase the ion injecting process of twice cost costliness; and to increase corresponding cleaning operation, photo-mask process and activated at operation; make the manufacturing process flow lengthening, cost improves.
The purpose of this utility model is to provide a kind of power MOS (Metal Oxide Semiconductor) device grid protection tube of making of simple and easy method, to improve the reliability of power MOS (Metal Oxide Semiconductor) device.
Basic design of the present utility model is at the corresponding operation stage of making power MOS (Metal Oxide Semiconductor) device; the termination environment is hollowed out some with interior polysilicon; monocrystalline substrate below the polysilicon is come out; directly on monocrystalline substrate, make the grid protection tube, and the grid of utmost point of protection tube and power MOS (Metal Oxide Semiconductor) device is coupled together with aluminum strip.Another utmost point of protection tube links to each other with the source electrode of power MOS (Metal Oxide Semiconductor) device.To enhanced power MOS device, the negative electrode of grid protection tube links to each other with the grid of power MOS (Metal Oxide Semiconductor) device, and the anode of grid protection tube links to each other with the source electrode of power MOS (Metal Oxide Semiconductor) device.To the depletion type power MOS (Metal Oxide Semiconductor) device, the anode of grid protection tube links to each other with the grid of power MOS (Metal Oxide Semiconductor) device, and the negative electrode of grid protection tube links to each other with the source electrode of power MOS (Metal Oxide Semiconductor) device.
Feature of the present utility model is:
1, the grid protection tube is done within the termination environment of power MOS (Metal Oxide Semiconductor) device;
2, the grid protection tube is produced on the silicon monocrystalline substrate;
3, the grid protection tube utmost point directly links to each other with the grid of power MOS (Metal Oxide Semiconductor) device by aluminum strip.
Specifically introduce making step of the present utility model below in conjunction with embodiment:
1, growth oxide layer 2(Fig. 1 on silicon monocrystalline substrate 1);
2, photoetching oxide layer 2 expands boron and advances, and forms P on substrate 1
-District 3.P
+District 3 has the effect of the basic emitter-base bandgap grading short-circuit resistance that reduces parasitic transistor in the unit of power MOS (Metal Oxide Semiconductor) device, in the peripheral field limiting ring termination environment (Fig. 2) that forms of power MOS (Metal Oxide Semiconductor) device;
3, photoetching oxide layer 2, growth gate oxide 4 is followed deposit polysilicon 5, forms the grid (Fig. 3) of power MOS (Metal Oxide Semiconductor) device;
4, the photoetching polysilicon 5, annotate boron, float gate oxide 4, advance to form P
-District 6 as the channel region of power MOS (Metal Oxide Semiconductor) device, and forms the anode 11 of grid protection tube simultaneously, growth oxide layer 7, P
+District 3 also enlarges (Fig. 4) simultaneously;
5, photoetching oxide layer 7 expands phosphorus, forms N
+District 8, N
+District 8 is source regions of power MOS (Metal Oxide Semiconductor) device, forms negative electrode 12(Fig. 5 of grid protection tube simultaneously);
6, growth suboxides layer 9, evaporation of aluminum 10 after the photoetching, carve aluminium (Fig. 6);
Like this, when making power MOS (Metal Oxide Semiconductor) device, a PN junction gate protection diode has also been made simultaneously.The negative electrode of diode is received by aluminum strip on the grid of power MOS (Metal Oxide Semiconductor) device, and its anode passes through P
-District 11, P
+District 3 receives the source electrode of power MOS (Metal Oxide Semiconductor) device again by aluminum strip, form one when grid voltage is too high, the grid protection tube that can shield.
The grid protection tube of power MOS (Metal Oxide Semiconductor) device can adopt single, also can adopt a plurality of.Overcurrent capability when protecting for increasing can be got parallel form (Fig. 7) between each protection tube.Gate voltage value during for the raising voltage stabilizing, desirable series connection form (Fig. 8) between each protection tube.Overcurrent capability in the time of should increasing protection, the gate voltage value when improving voltage stabilizing again can be got series-parallel connection form (Fig. 9) between each protection tube.For the gate source voltage that makes power MOS (Metal Oxide Semiconductor) device forward or oppositely can both be stabilized to certain numerical value no matter, the orientation between each protection tube is (Figure 10) on the contrary.
The utility model is compared with existing power MOS (Metal Oxide Semiconductor) device grid protection tube, and technology is simple, and is easy to make, and is fully compatible with the power MOS (Metal Oxide Semiconductor) device manufacture craft, need not increase new process, greatly reduces cost.
Claims (5)
1, the grid protection tube of a kind of power MOS (Metal Oxide Semiconductor) device (both comprised pure power MOS (Metal Oxide Semiconductor) device, and also comprised MOS-bipolar device) is characterized in that:
1), the grid protection tube is produced in the termination environment of power MOS (Metal Oxide Semiconductor) device;
2), the grid protection tube is produced on the silicon monocrystalline substrate;
3), the grid protection tube utmost point directly links to each other with the grid of power MOS (Metal Oxide Semiconductor) device by aluminum strip.
2, grid protection tube according to claim 1 is characterized in that: adopt a plurality of protection tubes, get the series connection form between each protection tube.
3, grid protection tube according to claim 1 is characterized in that: adopt a plurality of protection tubes, get parallel form between each protection tube.
4, grid protection tube according to claim 1 is characterized in that: adopt a plurality of protection tubes, get the series-parallel connection form between each protection tube.
5, grid protection tube according to claim 1 is characterized in that: adopt a plurality of protection tubes, the orientation between each protection tube can be opposite.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 90216873 CN2073169U (en) | 1990-07-30 | 1990-07-30 | Grid protector of power mos device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 90216873 CN2073169U (en) | 1990-07-30 | 1990-07-30 | Grid protector of power mos device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN2073169U true CN2073169U (en) | 1991-03-13 |
Family
ID=4895962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 90216873 Withdrawn CN2073169U (en) | 1990-07-30 | 1990-07-30 | Grid protector of power mos device |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN2073169U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1664683B (en) * | 1992-12-09 | 2011-06-15 | 株式会社半导体能源研究所 | Electronic circuit |
-
1990
- 1990-07-30 CN CN 90216873 patent/CN2073169U/en not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1664683B (en) * | 1992-12-09 | 2011-06-15 | 株式会社半导体能源研究所 | Electronic circuit |
CN1607875B (en) * | 1992-12-09 | 2011-07-06 | 株式会社半导体能源研究所 | Display device and method for manufacturing same |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C19 | Lapse of patent right due to non-payment of the annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |