CN207233366U - A kind of ultrahigh resolution figure signal generator - Google Patents
A kind of ultrahigh resolution figure signal generator Download PDFInfo
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- CN207233366U CN207233366U CN201721051873.0U CN201721051873U CN207233366U CN 207233366 U CN207233366 U CN 207233366U CN 201721051873 U CN201721051873 U CN 201721051873U CN 207233366 U CN207233366 U CN 207233366U
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Abstract
The utility model discloses a kind of ultrahigh resolution figure signal generator, including main signal card, backboard subcard, one or more signal subcards；Main signal card carry backboard subcard, backboard subcard carry one or more signal subcard, forms three-level structure；Pass through the control of high speed EMIF bus transfers and configuration information between main signal card and backboard subcard；Backboard subcard is used for realization the upgrading loading of the EMIF bus extensions of main signal card, main signal card and each signal subcard, and provides physical layer channel for main signal card and each signal subcard；Main signal card and each signal subspace card are inserted on backboard subcard by connector；The transmission of main signal card control signal and configuration information is realized between backboard subcard and each signal subcard by EMIF expansion bus, interface transmission configuration signal is configured by FPP；Each signal subcard is used for the extension of VbyOne signals；Signal subcard can be configured according to actual test demand, be adapted to the module of a variety of high-resolution and refresh rate.
Description
Technical field
The utility model belongs to signal generator design field, more particularly, to a kind of ultrahigh resolution figure
Signal generator.
Background technology
With the development of liquid crystal module technology, the resolution ratio of liquid crystal module obtains fast lifting, occurs 8K, 10K in succession
Etc. high-resolution large scale liquid crystal module.With the development of high-resolution large scale liquid crystal module, to realize to such liquid
Research and development, production and the test of brilliant module, have demand to the figure signal generator for supporting these high-resolution liquid crystal modules.
At present, the interface for supporting the signal generator of the high refresh rate liquid crystal module of high-resolution on the market is mostly DP, HDMI
And VbyOne interfaces.But for the high-resolution module such as 8K, 10K, due to DP and HDMI bandwidth limitation, it is necessary to using
Up to the figure model generator of 64lane VbyOne interfaces, existing signal generator cannot support this.
Utility model content
For the disadvantages described above or Improvement requirement of the prior art, the utility model provides a kind of ultrahigh resolution figure letter
Number generator, its object is to realize high-speed transfer and the distribution of signal based on FPGA, to meet high-resolution, high refresh rate liquid
The test of brilliant module and production requirement.
To achieve the above object, according to the one side of the utility model, there is provided a kind of ultrahigh resolution figure signal
Generator, including main signal card, backboard subcard, one or more signal subcards；Main signal card carry backboard subcard, backboard subcard
Carry one or more signal subcard, thus cascades the three-level structure of composition；Main signal card, backboard subcard and signal subcard are equal
Realized based on FPGA；
Wherein, main signal card is as global control unit and main signal generation unit, for controlling the ultrahigh resolution
Shape signal generator is synchronous with signal subcard with the communication, configuration, backboard subcard of host computer, switch is electric, cuts figure processing, and
The generation and distribution of picture signal；
Pass through high speed EMIF (External Memory Interface, external storage between main signal card and backboard subcard
Device interface) bus transfer control and configuration information, the FPGA of backboard subcard by FPP (Fast Passive Parallel, soon
It is fast passive parallel) configure the quick startup that interface completes main signal card FPGA；
The upgrading that backboard subcard is used for realization the EMIF bus extensions of main signal card, main signal card and each signal subcard adds
Carry, and physical layer channel is provided for main signal card and each signal subcard；Main signal card and each signal subspace card are inserted by connector
On backboard subcard.
Between backboard subcard and each signal subcard by EMIF expansion bus realize control signal that main signal card issues and
The transmission of configuration information, configures interface by FPP and transmits FPGA configuration signals；
Each signal subcard is used for the output of VbyOne signals.
Preferably, above-mentioned ultrahigh resolution figure signal generator, each signal subcard are received and dispatched by the high speed of 8lane
Device carries out signal interaction through the connector on backboard subcard and main signal card.
Preferably, above-mentioned ultrahigh resolution figure signal generator, when ultrahigh resolution figure signal generator receives
Electric order is opened, view data and configuration data are sent to signal subcard by main signal card by high-speed transceiver, and signal subcard will
It is stored in after the image data decoding that main signal card is sent in the plug-in memory of signal subcard, and sent using main signal card
Configuration data completes the configuration of signal subcard, then according to configuration data that the view data being stored in plug-in memory is defeated
Go out, the point screen for module to be measured；Wherein, configuration data includes sequential, refresh rate, output lane numbers.
Preferably, above-mentioned ultrahigh resolution figure signal generator, each equal flexibly configurable of signal subcard for 4lane,
The VbyOne signal output interfaces of 8lane, 16lane, by the way that multiple signal daughter card combinations are formed 32lane's or 64lane
VbyOne signal output interfaces, so as to be adapted to the module of high-resolution and high refresh rate；Main signal card then needs point according to module
Screen mode and interface lane numbers carry out signal distribution to each signal subspace card；Wherein, the split screen mode of module includes but not limited to field
Word split screen, left and right split screen, upper and lower split screen.
Preferably, above-mentioned ultrahigh resolution figure signal generator, its main signal card will according to the split screen mode of module
The view data that module respectively shields is read out according to the configuration that upper layer software (applications) issues from plug-in memory, and is exported to connection
The signal subcard of module to be measured, support to configure by upper layer software (applications) realize signal subcard output image Data Position match somebody with somebody work(
Energy；For example, for the word split screen of field, main signal card can by upper left, upper right, lower-left, bottom right any four position view data
Read out, and exported to corresponding signal subcard from plug-in DDR4 according to the configuration that upper layer software (applications) issues.
Preferably, above-mentioned ultrahigh resolution figure signal generator, main signal card pass through EMIF buses and outside VDD electricity
Source plate, VBL power supply board communications；Wherein, VDD power panels are used to provide working power for module to be measured, and VBL power panels are used for treat
Survey module and backlight electric power is provided；The configuration information of power supply is issued VDD power panels, VBL power supplys by main signal card by EMIF buses
Plate；
After VDD power panels, VBL power panels receive configuration information, the configuration of power supply is completed, and waits the life of main signal card
Order；When receiving after opening electric, powered-down order of main signal card transmission, VDD power panels, VBL power panels are completed each according to timing requirements
The output or closing of power supply；The configuration information of power supply includes power supply output, over-current over-voltage protection, undercurrent under-voltage protection and/or opens
Electric sequential.
Preferably, above-mentioned ultrahigh resolution figure signal generator, its main signal fixture are useful for what is communicated with host computer
Ethernet interface, the USB interface for Keyboard Control, and for storing eMMC the or DDR4 memories of test module file.
Preferably, above-mentioned ultrahigh resolution figure signal generator, its backboard subcard have SPI interface, I2C interface,
GPIO interface；The read-write of Initial code and register, the adjusting of EDID/VCOM are respectively used to, the function of module to be measured is matched somebody with somebody
Put.
Preferably, above-mentioned ultrahigh resolution figure signal generator, its backboard subcard connecing equipped with plug-in SPI flash
The interface of mouth and plug-in Nand Flash；Backboard subcard FPGA programs are stored by SPI flash, are deposited by Nand Flash
Store up main signal card FPGA programs and the program of signal subcard FPGA.
Preferably, above-mentioned ultrahigh resolution figure signal generator, upon power-up of the system, first by main signal card with
Host computer completes handshake communication；Then image data, power configuration parameter and module timing information are obtained from host computer, and
Store in its plug-in DDR4 or eMMC.
Preferably, above-mentioned ultrahigh resolution figure signal generator, directly can be from it certainly using low cost and FPGA
The SPI Flash of startup complete the self-starting of backboard subcard FPGA as storage medium；
In order to quickly upgrade and load, main signal card and signal subcard are stored using NandFlash.
Preferably, above-mentioned ultrahigh resolution figure signal generator, the plug-in storage module that is useful for of its signal subcard are surveyed
Try the DDR4 of file.
In general, by the contemplated above technical scheme of the utility model compared with prior art, can obtain down
Row beneficial effect：
(1) the ultrahigh resolution figure signal generator provided by the utility model based on FPGA, using self-defined high speed
Transceiver communication protocols, on the basis of the three-level interconnection architecture being made of main signal card, backboard subcard, signal subcard
Realize the transceiver interconnected communications per lane highests 12Gbps, the total bandwidth that highest is supported is 576Gbps (48lane),
Remote bandwidth demand of super 8K, 10K liquid crystal module in the case of 120Hz refresh rates；
(2) the ultrahigh resolution figure signal generator provided by the utility model based on FPGA, it is real by EMIF buses
Existing control of the main signal card to each signal subcard, the bandwidth of EMIF buses can reach 1Gbps (synchronised clock of 125MHz), realize
The Synchronization Control of quick low delay；
(3) the ultrahigh resolution figure signal generator provided by the utility model based on FPGA, interface is configured by FPP
The quick startup of main signal card and signal subcard is realized, and realizes quick each signal subcard, synchronous averaging and upgrading, is opened
Dynamic time and update time, can improve work on the spot efficiency；
(4) the ultrahigh resolution figure signal generator provided by the utility model based on FPGA, is provided high using FPGA
The interface of fast transceiver realizes signal extension, and can configure signal subcard quantity according to demand simultaneously can be to several signals
Subcard is combined, therefore dynamically configurable is 4/8/16/32/64lane VbyOne interfaces, can be adapted to different resolution and brush
The liquid crystal module of new rate；On the other hand, since signal subcard quantity can be configured according to actual test demand, signal subspace can be saved
Card, and then save cost.
Brief description of the drawings
Fig. 1 is the functional block diagram for the ultrahigh resolution figure signal generator based on FPGA that embodiment provides.
Embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, is further elaborated the utility model.It should be appreciated that specific embodiment described herein is only explaining
The utility model, is not used to limit the utility model.In addition, institute in each embodiment of the utility model disclosed below
As long as the technical characteristic being related to does not form conflict and is mutually combined each other.
The ultrahigh resolution figure signal generator based on FPGA that embodiment provides, its framework as schematically shown in Figure 1, bag
Include main signal card, backboard subcard, one or more signal subcards；Main signal card carry backboard subcard, backboard subcard carry one
Or multiple signal subcards, thus cascade the three-level structure of composition；Main signal card, backboard subcard and signal subcard are based on FPGA
Realize；
Wherein, main signal card is as global control unit and main signal generation unit, for controlling the ultrahigh resolution
Shape signal generator is synchronous with signal subcard with the communication, configuration, backboard subcard of host computer, switch is electric, cuts figure processing, and
The generation and distribution of picture signal；
Led between main signal card and backboard subcard by the control of high speed EMIF bus transfers and configuration information, the FPGA of daughter board
Cross the quick startup that FPP configuration interfaces realize main signal card FPGA；
Wherein, backboard subcard is used for realization the liter of the EMIF bus extensions of main signal card, main signal card and each signal subcard
Level loading, and provide physical layer channel for main signal card and each signal subcard；Main signal card and each signal subspace card pass through connection
Device is inserted on backboard subcard.Between backboard subcard and each signal subcard by EMIF expansion bus complete main signal card control and
The transmission of configuration information, the transmission of all FPGA configurations signals of interface completion is configured by FPP；
Wherein, signal subcard is used for the output of VbyOne signals；In Fig. 1, Vx1 refers to VbyOne signals all the way.
The ultrahigh resolution figure signal generator based on FPGA that embodiment provides can support 4 VbyOne signal subspaces
Card；Each signal subcard is sticked into by the high speed transceiver of the FPGA 8lane realized through back panel connector and main signal
Row interconnection.
When ultrahigh resolution figure signal generator receives out electric order, main signal card is by view data and configuration data
(including sequential, refresh rate, output lane numbers) is sent to signal subcard by high-speed transceiver, and signal subcard sends out main signal card
It is stored in after the image data decoding sent in the plug-in DDR4 of signal subcard, and the configuration data sent using main signal card is completed
The configuration of signal subcard, then exports the view data for being stored in DDR4 according to configuration data, the point screen for module to be measured.
Each equal flexibly configurable of signal subcard be 4lane, 8lane, 16lane VbyOne signal output interfaces, pass through by
Multiple signal daughter card combinations form the VbyOne signal output interfaces of 32lane or 64lane, so as to be adapted to high-resolution and high brush
The module of new rate；Main signal card is then used to carry out signal distribution to each signal subspace card according to the lane numbers of module.
For example, module to be measured is 64lane VbyOne signaling interfaces, and image output is field word split screen, according to main signal card
Distribution, the image of 16lane upper left corners a quarter is exported by the first signal subcard 1, secondary signal subcard 2 exports the upper right corner
The image of a quarter, the 3rd signal subcard 3 export the image of lower left corner a quarter, the 4th signal subcard 4 output lower right corner
The image of a quarter.The ultrahigh resolution figure signal generator that embodiment provides supports signal subcard output image data bit
That puts matches somebody with somebody.
Main signal card passes through EMIF buses and VDD power panels, VBL power supply board communications；Wherein, it is liquid that VDD power panels, which are used for,
Brilliant module provides working power, and VBL power panels are used to provide backlight electric power for liquid crystal module；Main signal card will by EMIF buses
The configuration information (including power supply output, over-current over-voltage protection, undercurrent under-voltage protection, open electric sequential etc.) of power supply issues VDD, VBL
Power panel, after power panel receives configuration information, completes the configuration of each power supply, and waits the order of main signal card；When receiving main letter
Number card send open electric, powered-down order after, power panel completes the output or closing of each power supply according to timing requirements.
The above-mentioned ultrahigh resolution figure signal generator that embodiment provides, its main signal fixture are useful for leading to host computer
The Ethernet interface of letter, for the USB interface of Keyboard Control, and for storing eMMC, DDR4 of test module file.
The above-mentioned ultrahigh resolution figure signal generator that embodiment provides, its backboard subcard have SPI interface, I2C connects
Mouthful, GPIO interface；The read-write of Initial code and register, the adjusting of EDID/VCOM are respectively used to, the function of module is matched somebody with somebody
Put.
The above-mentioned ultrahigh resolution figure signal generator that embodiment provides, its backboard subcard are equipped with plug-in SPI flash
Interface and plug-in Nand Flash interface；Backboard FPGA programs are stored by SPI flash, are deposited by Nand Flash
Store up the program of main signal card FPGA and signal subcard FPGA.
Since the FPGA program codes of backboard subcard are smaller, optional cost is relatively low and FPGA directly can be from its self-starting
SPI Flash as storage medium, complete the self-starting of backboard subcard FPGA.But due to main signal card and signal subcard
Program code it is larger, function is more, and there are multiple programs mirror image, in order to quickly upgrade and load, main signal card and
Signal subcard is stored using NandFlash.After backboard subcard completes self-starting, main signal is read from Nandflash
Block the program of FPGA, the startup of interface completion main signal card FPGA is configured by FPP.After main signal card FPGA start completions, the back of the body
Board daughter card FPGA then from Nandflash read output signal subcard FPGA programs, pass through the signal that has been inserted into of ID pins detection
The position of subcard and quantity, then pass through the logic copy of backboard FPGA to all insertion signal subcards by FPAG routine datas
FPP configures port, completes parallel starting while all signal subcards, shortens and starts the time.
Above-mentioned ultrahigh resolution figure signal generator, its signal subcard is plug-in to be useful for storing module test file
DDR4.When signal subcard needs upgrading, main signal card is stored in main letter after obtaining upgrade file from host computer by Ethernet
In number plug-in DDR4 of card；Then the upgrade file in DDR4 is sent to by backboard subcard by EMIF buses；Backboard subcard connects
Receive upgrade file and store into its plug-in NandFlash.
After device power, backboard subcard obtains backboard program from plug-in SPI Flash by AS patterns and open certainly
Dynamic, the upgrade file in NandFlash after completing self-starting that its is plug-in configures interface by FPP and is loaded into signal subspace
Card, the upgrade file of the added load of each signal subcard are consistent.
Ultrahigh resolution figure signal generator completes handshake communication from host computer after the power is turned on, by main signal card, then
Image data, power configuration parameter and module timing information are obtained, and is stored into its plug-in DDR4 or eMMC.
As it will be easily appreciated by one skilled in the art that the above is only the preferred embodiment of the utility model only, not
To limit the utility model, any modification for being made where within the spirit and principles of the present invention, equivalent substitution and change
Into etc., it should be included within the scope of protection of this utility model.
Claims (8)
- A kind of 1. ultrahigh resolution figure signal generator, it is characterised in that including main signal card, backboard subcard, one or more A signal subcard；The main signal card carry backboard subcard, backboard subcard carry one or more signal subcard, thus cascades structure Into three-level structure；The main signal card, backboard subcard and signal subcard are based on FPGA realizations；Main signal card and each signal Subcard is inserted on backboard subcard by connector；The main signal card is as global control unit and main signal generation unit, for controlling ultrahigh resolution figure signal to send out Raw device is synchronous with signal subcard with the communication, configuration, backboard subcard of host computer, switch is electric, cuts figure processing, and picture signal Generation and distribution；Control and configuration information, the back of the body are transmitted by high speed outer memory interface bus between the main signal card and backboard subcard The FPGA of board daughter card completes the quick of main signal card FPGA by quick passive parallel deployment interface and starts；The backboard subcard is used for realization the external memory interface bus extension, main signal card and each signal subcard of main signal card Upgrade procedure loading, and provide physical layer channel for main signal card and each signal subcard；Backboard subcard and each signal subcard Between the transmission of control signal that main signal card issues and configuration information is realized by external memory interface expansion bus, pass through Quick passive parallel deployment interface transmission FPGA configuration signals；Each signal subcard is used for the output of VbyOne signals.
- 2. ultrahigh resolution figure signal generator as claimed in claim 1, it is characterised in that each signal subspace cartoon The high-speed transceiver for crossing the 2N lane of FPGA realizations carries out signal interaction through the connector on backboard subcard and main signal card；Its In, N is natural number.
- 3. ultrahigh resolution figure signal generator as claimed in claim 1 or 2, it is characterised in that work as ultrahigh resolution Shape signal generator receives out electric order, and the main signal card receives the high speed that view data and configuration data are realized by FPGA Hair device is sent to signal subcard, and signal subspace clamping receives described image data and is stored in the plug-in memory of signal subcard after decoding In, and utilize the configuration data to complete the configuration of signal subcard, the view data being stored in plug-in memory is exported, Point screen for module to be measured；Wherein, configuration data includes sequential, refresh rate, output lane numbers.
- 4. ultrahigh resolution figure signal generator as claimed in claim 1, it is characterised in that each signal subcard is equal Flexibly configurable is the VbyOne signal output interfaces of 4lane, 8lane or 16lane；By by multiple signal daughter card combinations shapes Into the VbyOne signal output interfaces of 32lane or 64lane, so as to be adapted to the module of high-resolution and high refresh rate；Main signal Card then carries out signal distribution according to the split screen mode of module and interface lane numbers to each signal subspace card；The split screen mode include but It is not limited to field word split screen, left and right split screen, upper and lower split screen.
- 5. ultrahigh resolution figure signal generator as claimed in claim 1, it is characterised in that the main signal card is according to mould The split screen mode of group, the view data that module respectively shields is read out according to the configuration that upper layer software (applications) issues from plug-in memory Come, and distribute to the signal subcard for connecting module to be measured, to support to realize signal subcard output image by upper layer software (applications) configuration Data Position matches somebody with somebody function.
- 6. ultrahigh resolution figure signal generator as claimed in claim 1, it is characterised in that the main signal card passes through outer Portion's memory interface bus and outside VDD power panels, VBL power supply board communications；The VDD power panels are used to provide for module to be measured Working power, VBL power panels are used to provide backlight electric power for module to be measured；Main signal card will by external memory interface bus Power configuration information issues VDD power panels, VBL power panels.
- 7. ultrahigh resolution figure signal generator as claimed in claim 1, it is characterised in that the main signal fixture is useful In the Ethernet interface to communicate with host computer, the USB interface for Keyboard Control, and for storing depositing for test module file Reservoir；The backboard subcard has SPI interface, I2C interface, GPIO interface.
- 8. ultrahigh resolution figure signal generator as claimed in claim 1, it is characterised in that the backboard subcard is equipped with outer Hang the interface of SPI flash and the interface of plug-in Nand Flash；Backboard subcard FPGA is stored by plug-in SPI flash Program, main signal card FPGA programs and the program of signal subcard FPGA are stored by plug-in Nand Flash；The backboard subcard can be used as storage medium, completion backboard subcard using FPGA from the SPI Flash of its self-starting The self-starting of FPGA；The main signal card and signal subcard are using NandFlash storage FPGA programs；The signal subcard is plug-in It is useful for the DDR4 of storage module test file.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721051873.0U CN207233366U (en) | 2017-08-21 | 2017-08-21 | A kind of ultrahigh resolution figure signal generator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107358928A (en) * | 2017-08-21 | 2017-11-17 | 武汉精测电子技术股份有限公司 | A kind of ultrahigh resolution figure signal generator and its startup, upgrade method |
| CN111538469A (en) * | 2020-04-09 | 2020-08-14 | 苏州佳智彩光电科技有限公司 | Module signal generator based on multi-FPGA parallel output super-multipath signals |
-
2017
- 2017-08-21 CN CN201721051873.0U patent/CN207233366U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107358928A (en) * | 2017-08-21 | 2017-11-17 | 武汉精测电子技术股份有限公司 | A kind of ultrahigh resolution figure signal generator and its startup, upgrade method |
| CN107358928B (en) * | 2017-08-21 | 2022-12-23 | 武汉精测电子集团股份有限公司 | Ultrahigh resolution graphics signal generator and starting and upgrading method thereof |
| CN111538469A (en) * | 2020-04-09 | 2020-08-14 | 苏州佳智彩光电科技有限公司 | Module signal generator based on multi-FPGA parallel output super-multipath signals |
| CN111538469B (en) * | 2020-04-09 | 2023-08-29 | 苏州佳智彩光电科技有限公司 | Module signal generator based on multi-FPGA parallel output ultra-multipath signals |
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