CN109548236B - Main controller of LED lighting system and layout design thereof on PCB - Google Patents

Main controller of LED lighting system and layout design thereof on PCB Download PDF

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Publication number
CN109548236B
CN109548236B CN201811477492.8A CN201811477492A CN109548236B CN 109548236 B CN109548236 B CN 109548236B CN 201811477492 A CN201811477492 A CN 201811477492A CN 109548236 B CN109548236 B CN 109548236B
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controller
pin
image data
network card
video image
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CN109548236A (en
Inventor
张家瑞
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Grand Canyon Lighting System Suzhou Co ltd
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Strongled Lighting Systems Suzhou Co ltd
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Priority to CN201811477492.8A priority Critical patent/CN109548236B/en
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Priority to PCT/CN2019/117163 priority patent/WO2020114206A1/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00Circuit arrangements for operating light-emitting diodes [LED]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

The invention provides a main controller of an LED lighting system, which expands the application range of a lamp from an LED display screen to any shape of building inner and outer walls, has excellent performance and wide application scene, comprises a controller and also comprises: the LED lighting system comprises a decoding chip, an SRAM memory, a network card chip and a network transformer, wherein a video signal is decoded by the decoding chip and then input into a controller, the controller stores video image data in a video into the SRAM memory, synchronously reads the video image data stored in the SRAM memory and forwards the video image data through the network card chip, the network card chip sends the data signal to the network transformer in a differential signal mode, and the network transformer is used for signal amplification and isolation protection.

Description

Main controller of LED lighting system and layout design thereof on PCB
Technical Field
The invention relates to the technical field of lighting control systems, in particular to a main controller of an LED lighting system and a layout design of the main controller on a PCB.
Background
Urban lighting is bloomed all the time in China, and buildings and landscapes express emotion which is transmitted to people at night by the buildings and the landscapes through artistic lighting design of lighting, or brand positioning, advertising, different light colors and different lighting design expressions, and all represent image positioning of buildings, owner units or government units; the method is derived from aesthetic control of designers, on one hand, building beauty is known, on the other hand, the method is well known to light beauty, and on the other hand, the method is good at displaying building beauty and landscape beauty by using light, and shows the texture at night and beauty which cannot be formed by sunlight in the daytime, but the forming of the beauty does not depart from the development and progress of the modern light technology, and simultaneously, higher requirements are provided for an LED lighting system, most of the existing LED lighting systems can only project videos onto LEDs of a display type, and the performance of the existing LED lighting systems cannot meet the requirements of current users.
Disclosure of Invention
The present invention aims to provide a main controller of an LED lighting system to solve the above problems, and also provides a layout design of the main controller of the LED lighting system on a PCB.
The technical scheme is as follows: a master controller for an LED lighting system, comprising: including the controller, still include with the automatically controlled connection of controller:
the decoding chip is used for decoding the input video coding and outputting video image data;
the SRAM memory is used for storing the video image data input by the decoding chip;
the network card chip is used for transmitting video image data;
the network transformer is used for signal level coupling and isolation of external interference to realize impedance matching;
the video signal is decoded by the decoding chip and then input into the controller, the controller stores video image data in a video into the SRAM memory, simultaneously reads the video image data stored in the SRAM memory, and forwards the video image data through the network card chip, and the network card chip sends the video image data to the network transformer in a differential signal mode and outputs the video image data to the sub-controllers of the LED lighting system through the network transformer.
Further, the decoding chip adopts AD9882, the controller is FPGA, and the FPGA adopts SPATAN6 series chips of XILINX company in USA; the network card chip adopts RTL-8208C, the network card chip adopts RMII hundred mega network card protocol, and the network transformer adopts PM 4G.
Further, the decoding chip is connected with the controller through a PC104 port, and the decoding chip inputs videos through a DVI interface;
further, the controller adopts a crystal oscillator of 50MHZ, and the crystal oscillator of 50MHZ is distributed to the crystal oscillator of 25MHZ of the network card chip through the controller, so that the controller is synchronous with the clock of the network card chip.
Further, the SRAM memories include a first SRAM memory, a second SRAM memory, and a third SRAM memory, where the first SRAM memory, the second SRAM memory, and the third SRAM memory each include two pieces of SRAM for performing a ping-pong operation, so that the SRAM memories can synchronously read data while storing data.
Furthermore, the main controller is further connected with an EEPROM (electrically erasable programmable read-only memory) for data backup, and is further connected with a FLASH memory for initialization configuration of the controller, and the initialization configuration mode adopts an SPI (serial peripheral interface) mode.
Furthermore, the controller is connected with a key and an LED lamp and used for judging the working state of the main controller through the on and off of the LED.
Furthermore, the controller is connected with four test pins for subsequent upgrading of the main controller.
Further, the controller is connected with a JTAG downloader interface for programming the controller.
Furthermore, the port of the PC104 is connected to a 65MHZ clock line inside the controller, and the global reset signal line is connected to a global clock IO port.
The layout design of the main controller on the PCB is characterized in that: the decoding chip, the PC104 port, the controller, the network card chip and the network transformer of the LED lighting system are integrated on a PCB circuit board, and the distances from each pin connected with the PC104 port and the controller to the corresponding pin of the controller are equal on the PCB circuit board.
Furthermore, pins of the PC104 port connected to the controller include 24 data pins of RGB, a pin of a horizontal synchronization signal hsyn, a pin of a vertical synchronization signal vsyn, a pin of a data valid signal DE, and a pin of a synchronization clock signal dclk, where pin numbers of the controllers corresponding to 8 data pins corresponding to red R are E6, E7, E8, D8, B8, C12, F12, and G11, pin numbers of the controllers corresponding to 8 data pins corresponding to green G are C13, a14, B14, a15, C14, a16, B16, and C15, pin numbers of the controllers corresponding to 8 data pins corresponding to blue B are D12, E12, D14, E14, B14, a14, C14, a14 corresponding to the pin number of the controller corresponding to horizontal synchronization signal hsyn, and pin number of the controller corresponding to vertical clock signal dclk is C14, and pin number of the controller corresponding to the control pin number of the vertical synchronization signal dclk 72 is C14, the data valid signal DE is given the pin number D9 to the controller.
According to the main controller of the LED lighting system, after a video signal enters a decoding chip through a DVI interface, the decoding chip sends video image data to the controller in parallel through a PC104 bus, then the controller stores the received image data by using a 50-megacrystal oscillator, simultaneously reads the video image data stored in an SRAM memory, and forwards the video image data through a network card chip, the network card chip sends the video image data to a network transformer in a differential signal mode and outputs the video image data to a sub-controller of the LED lighting system through the network transformer, and the network transformer is used for preventing misoperation such as static electricity from burning the network card chip; the DVI line is used for connecting the computer, so that the video output on the computer can be converted into the data with the functions of grabbing, reading and adjusting colors, and then the data correspond to the LED lamp through the sub-controllers, namely, the visible video signal of the main controller of the LED lighting system is output to the LED of any non-display type, and can be a pixel point, also can be any pixel point, even can be any curved screen and any special-shaped structure body, so that the application range of the lamp is expanded to the inner wall and the outer wall of a mansion with any shape from the LED display screen, the performance is excellent, and the application scene is wide.
In the layout design of the main controller of the LED lighting system on the PCB, a decoding chip, a PC104 port, a controller, a network card chip and a network transformer of the LED lighting system are integrated on the PCB, and the distances from each pin connected with the PC104 port and the controller to the corresponding pin of the manufactured device on the PCB are equal, so that the problem that the stored video data flickers due to the fact that the time sequence is not synchronous from the sampling signal output parallel 27bit data of the decoding chip to the controller and the time error is 3-5ns, the line loss and the transmission time are mutually synchronous, and the high-speed signal synchronization is guaranteed.
Drawings
Fig. 1 is a system block diagram of a master controller of the LED lighting system of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Referring to fig. 1, the main controller of an LED lighting system of the present invention includes a controller 1, where the controller 1 is an FPGA, and the controller 1 employs a SPATAN6 series chip from XILINX corporation, usa, and further includes:
the decoding chip 2, the decoding chip 2 adopts AD9882, the decoding chip 2 is connected with the controller 1 through the port 3 of PC104, the decoding chip 2 inputs the video through DVI interface, is used for decoding the code of the input video, output the video image data;
an SRAM memory 4 for storing video image data inputted from the decoding chip 2;
the network card chip 5, the network card chip 5 adopts RTL-8208C, the network card chip 5 adopts RMII hundred mega network card protocol, used for transmitting video image data;
the network transformer 6 adopts PM4G, is used for signal level coupling and external interference isolation, and realizes impedance matching;
the video signal is decoded by the decoding chip 2 and then input into the controller 1, the controller 1 stores video image data in the video into the SRAM memory 4, simultaneously reads the video image data stored in the SRAM memory 4, and forwards the video image data through the network card chip 5, the network card chip 5 sends the video image data to the network transformer 6 in a differential signal mode, and the video image data is output to the sub-controllers of the LED lighting system through the network transformer 6.
Specifically, the SRAM memory 4 includes a first SRAM memory, a second SRAM memory, and a third SRAM memory, where the first SRAM memory, the second SRAM memory, and the third SRAM memory include two pieces of SRAMs respectively for performing ping-pong operation, so that the SRAM memory 4 can synchronously read data while storing data, and ping-pong switching time of the two pieces of SRAM memories is less than 20 ns, thereby strictly ensuring real-time video playing.
Specifically, the controller 1 adopts a 50MHZ crystal oscillator 7, the 50MHZ crystal oscillator 7 is distributed to a 25MHZ crystal oscillator 8 of the network card chip through the controller 1, so that clocks of the controller 1 and the network card chip 5 are synchronized, time errors between any two of the controller 1, the network card chip 5 and the SRAM memory 4 are controlled, unstable phase differences caused by the fact that the controller 1 and the network card chip 5 use two different crystal oscillators are avoided, and stable crystal oscillator output is guaranteed.
Specifically, the main controller is further connected with an EEPROM 14 for data backup, and is further connected with a FLASH memory 9 for initialization configuration of the controller 1, where the initialization configuration mode is an SPI mode.
Specifically, the controller 1 is connected with a key 10 and an LED lamp 11 for judging the working state of the main controller through the on/off of the LED.
Specifically, the controller 1 is connected with four test pins 12 for subsequent upgrading of the main controller.
Specifically, the controller 1 is connected to a JTAG downloader interface 13 for programming the controller 1.
Specifically, port 3 of PC104 is connected to a 65MHZ clock line inside controller 1, and the global reset signal line is connected to a global clock IO port.
In addition, the main controller of the LED lighting system of the present invention is powered by the power supply module 15.
According to the main controller of the LED lighting system, after a video signal enters a decoding chip through a DVI interface, the decoding chip sends video image data to the controller in parallel through a PC104 bus, then the controller stores the received image data by using a 50-megacrystal oscillator, simultaneously reads the video image data stored in an SRAM memory, and forwards the video image data through a network card chip, the network card chip sends the video image data to a network transformer in a differential signal mode and outputs the video image data to a sub-controller of the LED lighting system through the network transformer, and the network transformer is used for preventing misoperation such as static electricity from burning the network card chip; the DVI line is used for connecting the computer, so that the video output on the computer can be converted into the data with the functions of grabbing, reading and adjusting colors, and then the data correspond to the LED lamp through the sub-controllers, namely, the visible video signal of the main controller of the LED lighting system is output to the LED of any non-display type, and can be a pixel point, also can be any pixel point, even can be any curved screen and any special-shaped structure body, so that the application range of the lamp is expanded to the inner wall and the outer wall of a mansion with any shape from the LED display screen, the performance is excellent, and the application scene is wide.
In the layout design of the main controller of the LED lighting system on the PCB, a decoding chip, a PC104 port, a controller, a network card chip and a network transformer of the LED lighting system are integrated on the PCB, and the distances from each pin connected with the PC104 port and the controller to the corresponding pin of the manufactured device on the PCB are equal, so that the problem that the stored video data flickers due to the fact that the time sequence is not synchronous from the sampling signal output parallel 27bit data of the decoding chip to the controller and the time error is 3-5ns, the line loss and the transmission time are mutually synchronous, and the high-speed signal synchronization is guaranteed.
Wherein, the pins of the PC104 port connected with the controller include 24 data pins of RGB, a pin of a horizontal synchronizing signal hsyn, a pin of a vertical synchronizing signal vsyn, a pin of a data valid signal DE, a pin of a synchronous clock signal dclk, the pin bit numbers of the controllers corresponding to the 8 data pins corresponding to the red R are E6, E7, E8, D8, B8, C12, F12 and G11, the pin bit numbers of the controllers corresponding to the 8 data pins corresponding to the green G are C13, a14, B14, a15, C14, a16, B16 and C15, the pin bit numbers of the controllers corresponding to the 8 data pins corresponding to the blue B are D12, E12, D14, E13, B4, a4, C5 and a5, the pin bit number of the controller corresponding to the horizontal synchronization signal hsyn is C10, the pin number of the controller corresponding to the vertical synchronization signal vsyn is D11, the pin number of the controller corresponding to the synchronization clock signal dclk is E11, and the bit number of the data valid signal to the controller is D9.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (3)

1. A master controller for an LED lighting system, comprising: including the controller, still include with the automatically controlled connection of controller:
the decoding chip is used for decoding the input video coding and outputting video image data;
the SRAM memory is used for storing the video image data input by the decoding chip;
the network card chip is used for transmitting video image data;
the network transformer is used for signal amplification and isolation protection;
the video signal is decoded by the decoding chip and then input into the controller, the controller stores video image data in a video into the SRAM memory, simultaneously reads the video image data stored in the SRAM memory, and forwards the video image data through the network card chip, and the network card chip sends the video image data to the network transformer in a differential signal mode and outputs the video image data to the sub-controller of the LED lighting system through the network transformer;
the decoding chip adopts AD9882, the controller is FPGA, and SPATAN6 series chips of XILINX company in USA are adopted; the network card chip adopts RTL-8208C, the network card chip adopts RMII hundred mega network card protocol, and the network transformer adopts PM 4G;
the decoding chip is connected with the controller through a PC104 port, and the decoding chip inputs videos through a DVI interface; the controller adopts a crystal oscillator of 50MHZ, and the crystal oscillator of 50MHZ is distributed to the crystal oscillator of 25MHZ of the network card chip through the controller, so that the controller is synchronous with the clock of the network card chip;
the SRAM memories comprise a first SRAM memory, a second SRAM memory and a third SRAM memory, wherein the first SRAM memory, the second SRAM memory and the third SRAM memory respectively comprise two pieces of SRAM for performing ping-pong operation, so that the SRAM memories can synchronously read data while storing the data;
the main controller is also connected with an EEPROM (electrically erasable programmable read-only memory) for data backup, and is also connected with a FLASH memory for carrying out initialization configuration on the controller, and the initialization configuration mode adopts an SPI (serial peripheral interface) mode;
the controller is connected with a key and an LED lamp and is used for judging the working state of the main controller through the on and off of the LED; the controller is connected with four test pins and is used for subsequent upgrading of the main controller; the controller is connected with a JTAG downloader interface and is used for programming the controller;
the port of the PC104 is connected to a 65MHZ clock line in the controller, and the global reset signal line is connected to a global clock IO port.
2. A layout design of a master controller according to claim 1 on a PCB, characterized in that: the decoding chip, the PC104 port, the controller, the network card chip and the network transformer of the LED lighting system are integrated on a PCB circuit board, and the distances from each pin connected with the PC104 port and the controller to the corresponding pin of the controller are equal on the PCB circuit board.
3. The layout design of a master controller on a PCB of claim 2, wherein: the pins of the port of the PC104 connected with the controller comprise 24 data pins of RGB, a pin of a horizontal synchronizing signal hsyn, a pin of a vertical synchronizing signal vsyn, a pin of a data valid signal DE, a pin of a synchronous clock signal dclk, the pin bit numbers of the controllers corresponding to the 8 data pins corresponding to the red R are E6, E7, E8, D8, B8, C12, F12 and G11, the pin bit numbers of the controllers corresponding to the 8 data pins corresponding to the green G are C13, a14, B14, a15, C14, a16, B16 and C15, the pin bit numbers of the controllers corresponding to the 8 data pins corresponding to the blue B are D12, E12, D14, E13, B4, a4, C5 and a5, the pin bit number of the controller corresponding to the horizontal synchronization signal hsyn is C10, the pin number of the controller corresponding to the vertical synchronization signal vsyn is D11, the pin number of the controller corresponding to the synchronization clock signal dclk is E11, and the bit number of the data valid signal to the controller is D9.
CN201811477492.8A 2018-12-05 2018-12-05 Main controller of LED lighting system and layout design thereof on PCB Active CN109548236B (en)

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CN201811477492.8A CN109548236B (en) 2018-12-05 2018-12-05 Main controller of LED lighting system and layout design thereof on PCB
PCT/CN2019/117163 WO2020114206A1 (en) 2018-12-05 2019-11-11 Master controller for led lighting system, and design for layout of same on pcb

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CN109548236B (en) * 2018-12-05 2021-04-13 大峡谷照明系统(苏州)股份有限公司 Main controller of LED lighting system and layout design thereof on PCB
CN112967666B (en) * 2021-02-24 2022-07-15 南京磊积科技有限公司 LED display screen control device and control method capable of realizing random pixel arrangement

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US20070171158A1 (en) * 2006-01-22 2007-07-26 Shalabh Kumar Low power led-based marquee systems
CN201234381Y (en) * 2008-07-31 2009-05-06 华南理工大学 Lamp decorative video processing system based on PCI bus
CN101426316B (en) * 2008-12-05 2012-10-31 华南理工大学 Irregular LED array displaying message frame sending controller and method
CN103686186B (en) * 2013-12-27 2017-01-18 龙迅半导体(合肥)股份有限公司 Data transmission platform
CN104658486B (en) * 2015-03-25 2018-04-17 何书专 A kind of high compatibility LED display controller
CN105261328A (en) * 2015-11-20 2016-01-20 青岛中科软件股份有限公司 ARM and FPGA-based LED display screen control system
CN206260018U (en) * 2016-12-06 2017-06-16 山东高云半导体科技有限公司 A kind of LED reception card hardware circuit platform based on domestic fpga chip
CN207938293U (en) * 2018-03-19 2018-10-02 南京信息工程大学 A kind of all-colour LED array drive device based on FPGA
CN109548236B (en) * 2018-12-05 2021-04-13 大峡谷照明系统(苏州)股份有限公司 Main controller of LED lighting system and layout design thereof on PCB

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Address after: 215211 north of Linhu Avenue, FenHu high tech Industrial Development Zone, Wujiang District, Suzhou City, Jiangsu Province

Patentee after: Grand Canyon Lighting System (Suzhou) Co.,Ltd.

Address before: 215211 north of Linhu Avenue, FenHu high tech Industrial Development Zone, Wujiang District, Suzhou City, Jiangsu Province

Patentee before: STRONGLED LIGHTING SYSTEMS (SUZHOU) Co.,Ltd.