CN215121002U

CN215121002U - Dual-path VGA automatic switching circuit based on BMC

Info

Publication number: CN215121002U
Application number: CN202121382549.3U
Authority: CN
Inventors: 崔玲; 段晓峰; 门乐飞; 姚陆晟; 周洁; 姬叶华; 张佩; 邹志强
Original assignee: CETC 32 Research Institute
Current assignee: CETC 32 Research Institute
Priority date: 2021-06-21
Filing date: 2021-06-21
Publication date: 2021-12-10
Anticipated expiration: 2031-06-21

Abstract

The utility model provides a double-circuit VGA automatic switch-over circuit based on BMC, a serial communication port, include: multichannel analog video switch chip, BMC chip, level conversion chip, AD conversion chip and VGA socket, the BMC chip passes through the VGA signal and is connected with multichannel analog video switch chip electricity, the level conversion chip is connected with multichannel analog video switch chip and BMC chip electricity respectively, multichannel analog video switch chip includes two output ends, and every output homogeneous electricity is connected with a VGA socket and an AD conversion chip electricity and is connected, and is a plurality of AD conversion chip is connected with the BMC chip electricity. The utility model discloses a display and arbitrary VGA interface connection, BMC chip control video switch's channel selection makes signal output to display for the staff need not carry out the switching of VGA interface, has improved the efficiency of software testing to the server.

Description

Dual-path VGA automatic switching circuit based on BMC

Technical Field

The utility model relates to an automatic switch-over circuit specifically relates to a double-circuit VGA automatic switch-over circuit based on BMC.

Background

The VGA (video Graphics array) interface is generally an interface for outputting analog signals on a display card, and is also called a D-Sub interface. Although the lcd can receive digital signals directly, many low-end products use VGA interfaces in order to match the VGA interface cards. The VGA interface is a D-type interface, the upper surface of the VGA interface is totally 15 pins empty, the VGA interface is divided into three rows, and each row is five.

The VGA interface is the most widely used interface type on the video card, and most video cards have such an interface. At present, most computers are connected with external display equipment through an analog VGA interface, display image information generated in a digital mode in the computers is converted into R, G, B three primary color signals and line and field synchronous signals by a digital/analog converter in a display card, and the signals are transmitted into the display equipment through the VGA interface and a connecting cable thereof. For analog display devices, such as analog CRT displays, the signals are fed directly to corresponding processing circuitry which drives and controls the picture tube to produce the image. For digital display devices such as LCD and DLP, a corresponding a/D (analog/digital) converter is required to convert the analog signal into a digital signal.

The VGA interface in the server is usually placed in a backboard, VGA signals are derived from a CPU mainboard, VGA display is not needed when the CPU mainboard is tested independently, and the test is inconvenient. VGA interface signals are always reserved on a mainboard in system design, and interfaces need to be switched during testing, so that the workload is increased.

In the chinese utility model patent document with publication number CN208806891U, a two-way VGA video switching module is disclosed, which comprises a VGA signal selection chip, a signal selection switch and a video processing chip; the output end of the signal selection switch is in communication connection with the signal selection end of the VGA signal selection chip; two signal input ends of the VGA signal selection chip are used for respectively receiving two paths of VGA signals; the output end circuit of the VGA signal selection chip is connected with the VGA signal input end of the video processing chip, and the output end of the video processing chip is used for outputting TTL signals to a display screen; the video processing chip circuit is connected with a logic control chip. The utility model has the advantages of less components, no need of software support for all hardware processing, small video switching delay and small module integration; can realize double-circuit VGA video signal switching input, TTL level signal output is all the way and the TFT LCD screen is lighted, the utility model discloses the module has extensive application space.

SUMMERY OF THE UTILITY MODEL

To the defect among the prior art, the utility model aims at providing a double-circuit VGA automatic switch-over circuit based on BMC.

According to the utility model provides a pair of double-circuit VGA automatic switch-over circuit based on BMC, include: multichannel analog video switch chip, BMC chip, level conversion chip, AD conversion chip and VGA socket, the BMC chip passes through the VGA signal and is connected with multichannel analog video switch chip electricity, the level conversion chip is connected with multichannel analog video switch chip and BMC chip electricity respectively, multichannel analog video switch chip includes two output ends, and every output homogeneous electricity is connected with a VGA socket and an AD conversion chip electricity and is connected, and is a plurality of AD conversion chip is connected with the BMC chip electricity.

Preferably, the BMC chip is AST2500, the multichannel analog video switch chip is PI3V713, the level conversion chip is SN74LVC2T45, and the AD conversion chip is AD 9883.

Preferably, the J4 pin on the BMC chip is electrically connected to the 1 pin on the multi-channel analog video switch chip, the J3 pin on the BMC chip is electrically connected to the 2 pin on the multi-channel analog video switch chip, the J2 pin on the BMC chip is electrically connected to the 5 pin on the multi-channel analog video switch chip, the R4 pin on the BMC chip is electrically connected to the 7 pin on the multi-channel analog video switch chip, and the N5 pin on the BMC chip is electrically connected to the 6 pin on the multi-channel analog video switch chip.

Preferably, the 64 pins on the AD conversion chip are electrically connected with the L19 pins on the BMC chip, and the 31 pins on the AD conversion chip are electrically connected with the 18 pins on the multi-channel analog video switch chip.

Preferably, the 2 pin on the level conversion chip is electrically connected with the K18 pin on the BMC chip, and the 7 pin on the level conversion chip is electrically connected with the 30 pin on the multi-channel analog video switch chip.

Preferably, the BMC chip includes a peripheral circuit, the peripheral circuit includes an active crystal oscillator, a working indicator light, an SPI FLASH, a serial port module, and DDR3 memory particles, and the active crystal oscillator, the working indicator light, the SPI FLASH, the serial port module, and the DDR3 memory particles are electrically connected to the BMC chip.

Preferably, the frequency of the active crystal oscillator is 24Mhz, and the active crystal oscillator is electrically connected with a CLKIN pin on the BMC chip.

Preferably, the serial port module is converted by a MAX3232 chip, and pins 11 and 12 on the MAX3232 chip are electrically connected with pins K1 and K2 on the BMC chip respectively.

Preferably, the DDR3 memory particles adopt MT41K256M1 chips.

Preferably, the DDR3 memory particles operate with a double data rate architecture.

Compared with the prior art, the utility model discloses following beneficial effect has:

1. the display is connected with any VGA interface, the BMC chip controls the channel selection of the video switch to output signals to the display, so that workers do not need to switch VGA interfaces, and the testing efficiency of the server is improved.

2. The utility model provides a switching circuit has that the switching completion time is shorter, and the integrated level is high, advantage that the design is simple.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a circuit structure diagram of a dual-path VGA automatic switching circuit based on BMC according to an embodiment of the present invention;

fig. 2 is a peripheral circuit diagram of the BMC chip according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to the following embodiments. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that various changes and modifications can be made by one skilled in the art without departing from the spirit of the invention. These all belong to the protection scope of the present invention.

The utility model discloses a VGA switching circuit, as shown in FIG. 1, this circuit adopts at least one multichannel analog video switch chip, a BMC chip and a level transition chip, and wherein multichannel analog video switch is seven passageway analog video switches, is arranged in R, G, B, Hsync, Vsync, DDC Data, DDC CLK in the switching VGA signal respectively. The BMC chip is used for switching VGA signals, acquiring signal levels of different interfaces of the VGA through the BMC chip, and judging which interface is connected with the display, so that channel selection of the video switch is controlled.

The BMC chip is electrically connected with the multichannel analog video switch chip through VGA signals, the level conversion chip is electrically connected with the multichannel analog video switch chip and the BMC chip respectively, the multichannel analog video switch chip comprises two output ends, each output end is electrically connected with a VGA socket and an AD conversion chip, and the AD conversion chips are electrically connected with the BMC chip.

The BMC chip outputs DAC R and G, B signals, the signals enter a channel video switch chip, a video switch is provided with a channel selection pin for configuring channel 1 or channel 2 to output, and VGA signals output by the two channels are connected with a VGA socket and an AD conversion chip.

The BMC chip selects AST2500, AST2500 is a 6 th generation integrated remote management controller produced by ASPEED, the controller is a widely integrated SOC device and is used as a server to support various functions required by a high management server platform, the AST2500 does not support a PCI bus, and a PCIE Gen 21 x bus interface is specially designed and supported, so that the PCB layout is simpler. The VGA display controller is one of key modules of AST2500 integration, and a system bus interface VGA adopts a 32-bit PCI bus interface and can work at 33 MHz. The VGA built in AST2500 is an in-band device and is independent of an ARM SOC system. Thus, it can only be reset when the PCI bus is reset or the system is powered on reset.

The VGA shares a portion of the SDRAM memory for video frame buffering. The size of the shared frame buffer is determined by the configuration resistor, which occupies the highest portion of the SDRAM memory. The ARM SOC system completes the initialization of the SDRAM, which should be completed before the host platform starts accessing the video buffer. The built-in VGA of AST2500 is completely compatible with IBM VGA, the maximum display resolution is 1920x1200@60Hz and 165MHz video clocks, and a snap ring which can be directly closed by an ARM CPU is integrated to generate the power-saving video clock and RGB analog output.

The channel analog video switch chip selects PI3V713, and the analog switch PI3V713 is a 7-channel video distributor used for switching a plurality of VGA video sources. In server application, two video port positions are required to be switched, the bandwidth can reach 1.7GHz, ESD protection is provided between VDD and GND, up to 12kv HBM ESD is supported, and video signals can be protected from high electrostatic discharge.

The level conversion chip is SN74LVC2T45, and the chip is a two-position non-inverting bus transceiver and comprises two independent supply rails. The port B is provided with VCCB, the set voltage is 5V, the port A is provided with VCCA, the set voltage is 3.3V, and the design voltage is from 3.3V to 5V. Control circuit DIR is powered by VCCA, pulling up a resistor to VCCA. In this new application only one level shifted signal is used, so a2 is tied to GND. Preventing excessive current flow.

The VGA video AD conversion chip selects AD 9883. The AD9883 is a complete 8-bit, 140MSPS, monolithic analog interface optimized for capturing RGB graphics signals for personal computers and workstations. Its 140MSPS coding rate capability and 300MHz full power analog bandwidth support resolution up to SXGA (1280x1024@75 Hz). The AD9883 includes a 140MHz triple ADC, phase locked loop, programmable gain, offset and clamp control. Only the 3.3V power supply, analog input, Hsync, and COAST signals need be provided.

The J4 pin on the BMC chip is electrically connected with the 1 pin on the multichannel analog video switch chip, the J3 pin on the BMC chip is electrically connected with the 2 pin on the multichannel analog video switch chip, the J2 pin on the BMC chip is electrically connected with the 5 pin on the multichannel analog video switch chip, the R4 pin on the BMC chip is electrically connected with the 7 pin on the multichannel analog video switch chip, and the N5 pin on the BMC chip is electrically connected with the 6 pin on the multichannel analog video switch chip.

The analog video switch chip is externally connected with two VGA sockets, pins 17 and 18 are respectively connected to 31 pins of the two AD9883, the output Vsync pin is connected to a GPIO (general purpose input/output) on the BMC, and a signal is confirmed on which VGA socket is through judging the Vsync signal, so that the SEL pin is controlled to switch a VGA channel.

And a 64 pin on the AD conversion chip is electrically connected with an L19 pin on the BMC chip, and a 31 pin on the AD conversion chip is electrically connected with an 18 pin on the multi-channel analog video switch chip. The 2 pin on the level conversion chip is electrically connected with the K18 pin on the BMC chip, and the 7 pin on the level conversion chip is electrically connected with the 30 pin on the multi-channel analog video switch chip.

The AST2500 peripheral circuit of the main control module is shown in FIG. 2 and comprises an active crystal oscillator, a working indicator lamp, an SPI FLASH, a serial port module and DDR3 memory particles. The crystal oscillator is 24 MHz.

The drive clock employs a 24MHz active crystal oscillator connected to the CLKIN pin of AST 2500. One end of the working state indicator lamp is connected to 3.3V through a resistor and the indicator lamp, and the other end of the working state indicator lamp is connected to the HBLED, so that the software and hardware working state of the AST2500 is represented. The SPI FLASH is a firmware SPI memory chip. AST2500 defines an auto-load command format for hardware identification of band setup code regions. The client can edit the required power-on preload setting command and store the command in the designated SPI flash area. The hardware will search for the code before the CPU starts fetching the code. The effective flash memory with code storage is 8KB in WSPICS0# in the lowest and highest full SPI flash memory. The band code can be stored anywhere in the 8KB range, but must follow a 4 byte address alignment. And all tape commands must be stored continuously and end with an end code. The maximum SPI flash size supported by software band functionality is 128MB (1 Gbits). When using an SPI flash of size greater than 16MB (32MB or greater), starting with 24 bit ad in dressing mode, the firmware strap code can only be placed in the beginning region of 8 KB. This is because for such flash types, it may be configured to access patterns via either 24-bit or 32-bit addresses, depending on firmware selection. If a stripe code is placed in a region of 8KB high, it should be placed in 2 locations, except for the actual highest 8KB region, it still has to copy another set and 24-bit addressing (up to 16MB) of the highest 8KB position. Otherwise, if it is, it will lose the coded fetch error address pattern.

The serial port module adopts MAX3232 chip conversion, and the MAX3232 device comprises two line drivers, two line receivers and a double-charge pump circuit with a +/-15 kVESD protection terminal. The device meets the requirements of TIA/EIA-232-F, and provides an electronic interface between the asynchronous communication controller and the serial port connector. The charge pump and four small external capacitors allow 3V to 3.5V supply. The data communication rate of the device can reach 250kbit/s and 30V/us at most to drive the output rotating speed. The 11 and 12 pins on the MAX3232 chip are electrically connected with the K1 and K2 pins on the BMC chip respectively.

DDR3 memory particles adopt MT41K256M16 chips. DDR3 SDRAM employs a double data rate architecture for high speed operation. The double data rate architecture is an 8n prefetch architecture, with the interface designed to transfer two data words per clock cycle at the I/O pins. A read or write operation of the DDR3 SDRAM effectively consists of a single 8n bit wide, 4 clock cycle data transfer on the internal DRAM core and a half clock cycle data transfer on eight corresponding n bit wide, I/O pins. Differential data pulses (DQS, DQS #) are transmitted externally with the data for data capture by the DDR3 SDRAM input receiver. The DQS is aligned with the write data. The read data is transferred through the DDR3 SDRAM and edge aligned to the data burst.

The AST2500 working device detects AD9883 which chip has voltage, the VGA interface corresponding to the chip which detects the voltage is connected to a display, and the AST2500 is tested to output high level or low level to SEL so as to open the corresponding VGA channel.

In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

The foregoing description of the specific embodiments of the invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. A dual-path VGA automatic switching circuit based on BMC comprises: multichannel analog video switch chip, BMC chip, level conversion chip, AD conversion chip and VGA socket, the BMC chip passes through the VGA signal and is connected with multichannel analog video switch chip electricity, the level conversion chip is connected with multichannel analog video switch chip and BMC chip electricity respectively, multichannel analog video switch chip includes two output ends, and every output homogeneous electricity is connected with a VGA socket and an AD conversion chip electricity and is connected, and is a plurality of AD conversion chip is connected with the BMC chip electricity.

2. The dual-path VGA automatic switching circuit based on BMC of claim 1, wherein: the BMC chip is AST2500, the multichannel analog video switch chip is PI3V713, the level conversion chip is SN74LVC2T45, and the AD conversion chip is AD 9883.

3. The dual-path VGA automatic switching circuit based on BMC of claim 2, wherein: the J4 pin on the BMC chip is electrically connected with the 1 pin on the multichannel analog video switch chip, the J3 pin on the BMC chip is electrically connected with the 2 pin on the multichannel analog video switch chip, the J2 pin on the BMC chip is electrically connected with the 5 pin on the multichannel analog video switch chip, the R4 pin on the BMC chip is electrically connected with the 7 pin on the multichannel analog video switch chip, and the N5 pin on the BMC chip is electrically connected with the 6 pin on the multichannel analog video switch chip.

4. The dual-path VGA automatic switching circuit based on BMC of claim 2, wherein: and a 64 pin on the AD conversion chip is electrically connected with an L19 pin on the BMC chip, and a 31 pin on the AD conversion chip is electrically connected with an 18 pin on the multi-channel analog video switch chip.

5. The dual-path VGA automatic switching circuit based on BMC of claim 2, wherein: and the 2 pin on the level conversion chip is electrically connected with the K18 pin on the BMC chip, and the 7 pin on the level conversion chip is electrically connected with the 30 pin on the multi-channel analog video switch chip.

6. The dual-path VGA automatic switching circuit based on BMC of claim 1, wherein: the BMC chip comprises a peripheral circuit, the peripheral circuit comprises an active crystal oscillator, a working indicator lamp, an SPI FLASH, a serial port module and DDR3 memory particles, and the active crystal oscillator, the working indicator lamp, the SPI FLASH, the serial port module and the DDR3 memory particles are electrically connected with the BMC chip.

7. The dual-path VGA automatic switching circuit based on BMC of claim 6, wherein: the frequency of the active crystal oscillator is 24Mhz, and the active crystal oscillator is electrically connected with a CLKIN pin on the BMC chip.

8. The dual-path VGA automatic switching circuit based on BMC of claim 6, wherein: the serial port module is converted by a MAX3232 chip, and pins 11 and 12 on the MAX3232 chip are respectively and electrically connected with pins K1 and K2 on the BMC chip.

9. The dual-path VGA automatic switching circuit based on BMC of claim 6, wherein: the DDR3 memory particle adopts an MT41K256M1 chip.

10. The dual-path VGA automatic switching circuit based on BMC of claim 9, wherein: the DDR3 memory particles operate with a double data rate architecture.