CN207200759U - A kind of coder transitions device of EPA interface - Google Patents
A kind of coder transitions device of EPA interface Download PDFInfo
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- CN207200759U CN207200759U CN201721148112.7U CN201721148112U CN207200759U CN 207200759 U CN207200759 U CN 207200759U CN 201721148112 U CN201721148112 U CN 201721148112U CN 207200759 U CN207200759 U CN 207200759U
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Abstract
The utility model discloses a kind of coder transitions device of EPA interface, including at least FPGA module, ARM modules, EPA physical layer block and encoder interfaces module；The encoder interfaces module comprises at least TTL incremental encoders interface, sine and cosine incremental encoder interface, absolute type encoder interface, and the FPGA module comprises at least increment type TTL interface controllers, increment type sine and cosine interface controller, absolute type encoder interface controller；The FPGA module is communicated through the encoder interfaces module with encoder, and the serial data that encoder is sent is decoded, while encoder position information is converted into EPA message, is sent to EPA physical layer block.The output interface of the unified a variety of encoders of the utility model, serial data is exported, TTL outputs, sine and cosine output are uniformly converted to EPA message, is supported a variety of industrial ethernet protocols, be disclosure satisfy that the use demand under different motion control occasion.
Description
Technical field
It the utility model is related to a kind of encoder network makeup to put, in particular relate to a kind of coding of EPA interface
Device conversion equipment.
Background technology
At present the whole world be in new technology, NPD projects innovation enliven period, the U.S. using EPA as realize elder generation
Enter the important carrier of manufacture, Germany is using industry 4.0 as the strategic choice for strengthening national advantage.Develop on a large scale with reference to current manufacturing industry
Concrete condition, China also propose in succession intelligent plant, intelligence equipment, it is advanced manufacture and made in China 2025 core think
Road, how with Internet of Things, the advanced generation information science and technology reconstruct traditional manufacture for being fabricated to representative, break through digitlization and set
Meter, optimization scheduling, in real time polynary isomeric data, the key technology such as integrated, have become the core main idea of industry innovation.Wherein such as
General sensing equipment access industrial Ethernet is made industrial internet of things equipment by what, be realize based on work internet+, work
The key of the intelligence manufacture of industry 4.0.
Photoelectric encoder be it is a kind of integrate light, mechanical, electrical digitized positions detection means, have that precision is high, volume
Small, the advantages that stability is good, it is widely used in the fields such as Digit Control Machine Tool, high accuracy servo system, robot control, while can be with
It is applied to as position, angular transducer in manufacturing industry.According to operation principle different coding device can be divided into incremental encoder and
Absolute type encoder.Incremental encoder can export one group of periodic voltage signal when rotating, and use internal pulses counting device
To determine its particular location and the direction of motion, and during absolute type encoder rotates a circle, each mechanical angle and one
Individual unique absolute data coding is corresponding.General incremental encoder has two kinds of interface types of sine and cosine pulse and TTL pulse；
And absolute type encoder has the private communication protocol of oneself, such as Heidenhain companies EnDat2.2 agreements, Danaher companies
BiSS agreements, SICK | HIPERFACE agreements of STEGMANN companies etc..Each producer is mostly its encoder interfaces agreement
Corresponding interface chip is devised, for converting serial data to parallel data, is advantageous to the read operation of controller, still
Problems be present：
Interface chip poor compatibility, the dedicated serial agreement that can only be had by oneself to producer decode, can not other compatible factories
Family's model encoder；
Supporting decoding chip or board is expensive, constitutes about a quarter of encoder price, improve product into
This.
Solve the above problems, it is necessary to the encoder of multiple interfaces type is carried out to the unification of agreement, and then plays industry
The advantages that Ethernet real-time is high, delay is low, high-speed high capacity communication, by general encoder access industrial Ethernet, makes
Common serial bus interface encoder is changed into equipment in EPA, namely industrial internet of things equipment.
The content of the invention
In view of insufficient existing for prior art, the purpose of this utility model is to provide for one kind being capable of compatible multiplex roles class
Type, the conversion equipment by the smooth access industrial Ethernet of conventional coders.
To achieve these goals, technical solution of the present invention is as follows：
A kind of coder transitions device of EPA interface, including at least FPGA module, ARM modules, industrial ether
Net physical layer block and encoder interfaces module, it is characterised in that：
The encoder interfaces module comprise at least TTL incremental encoders interface, sine and cosine incremental encoder interface,
Absolute type encoder interface, to realize FPGA and encoder communication connection, and according to corresponding serial encoder agreement, pass
The output signal of defeated corresponding encoded device；
The FPGA module comprises at least the increment type TTL Interface Controllers being connected with the TTL incremental encoders interface
Device, the increment type sine and cosine interface controller being connected with the sine and cosine incremental encoder interface and the absolute encoding
The absolute type encoder interface controller of device interface connection；The FPGA module is entered through the encoder interfaces module with encoder
Row communication, is decoded, while encoder position information is converted into EPA report to the serial data that encoder is sent
Text, it is sent to EPA physical layer block；
The ARM circuit modules comprise at least FSMC bus control units, can pass through FSMC buses and FPGA circuitry module
Communicated, realize that the control to FPGA module and register are read；
The EPA physical layer block, including at least dedicated ethernet physics transceiver, to realize FPGA moulds
The connection of block and EPA.
Further, the FPGA module also includes EPA MAC layer module, the EPA MAC layer mould
Block comprises at least message receiving module, physical chip control and access modules, message analysis and processing module, cpu data and connect
Mouth mold block and message sending module.
Further, the TTL incremental encoders interface comprises at least TTL differential drive circuits, and encoder is exported
TTL standard signals differential conversion be single sided pulse signal, enter row data communication with fpga chip.
Further, the TTL incremental encoders interface passes through FPGA I/O pin and FPGA increment type TTL interfaces
The TTL pulse counting module connection of controller, the TTL pulse counting module to the pulse for being input to FPGA based on carrying out
Number.
Further, the sine and cosine incremental encoder interface comprises at least preamplifier, a/d converter, to coding
Device output signal carries out preposition amplification, analog-to-digital conversion process, enters row data communication by USB and fpga chip.
Further, the increment type sine and cosine interface controller of the sine and cosine incremental encoder interface and FPGA connects
Connect, the increment type sine and cosine interface controller comprises at least ADC controllers, sine and cosine subdividing module, wherein the ADC is controlled
Device is by the sine and cosine encoder data transfer collected to sine and cosine subdividing module, and the sine and cosine subdividing module from ADC to controlling
The data that device processed receives are finely divided processing；
Further, the absolute type encoder interface comprises at least RS485 serial protocol conversion chips, and encoder is passed
Defeated dedicated serial data protocol signal carries out differential-to-single-ended conversion, and semiduplex data communication is carried out with fpga chip.
Further, the absolute type encoder interface controller connection of the absolute type encoder interface and FPGA, it is described
Absolute type encoder interface controller comprises at least Endat interface modules, BISS interface modules, rub river interface module, SSI connect more
Mouth mold block, wherein, Endat interface modules are used for the SOD serial output data for reading Endat protocol interface encoders, BISS interface moulds
Block is used for the SOD serial output data for reading BISS protocol interface encoders, and river interface module of rubbing more connects more for reading river agreements of rubbing
The SOD serial output data of mouth encoder, SSI interface modules are used for the SOD serial output data for reading SSI protocol interface encoders.
Compared with prior art, the beneficial effects of the utility model：
The encoder of multiple interfaces type is carried out agreement unification by the utility model, utilizes EPA to the full extent
The advantages that real-time is high, delay is low, high-speed high capacity communication, by general encoder access industrial Ethernet, makes common
Serial bus interface encoder is integrated into EPA, and has unified the output interface of a variety of encoders, by serial data
Output, TTL outputs, sine and cosine output are unified for EPA message so that encoder for servo module, unitized,
Meet the use demand of different user, enable in particular to meet under different motion control occasion to system reliability and real-time compared with
High request, make manufacturing Internet of Things.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are this hairs
Some bright embodiments, for those of ordinary skill in the art, without having to pay creative labor, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the utility model coder transitions structure drawing of device；
Fig. 2 is the utility model EPA MAC layer principle assumption diagram；
Fig. 3 is the utility model increment type TTL interface controller schematic diagrames；
Fig. 4 is the utility model increment type sine and cosine interface controller schematic diagram；
Fig. 5 is the utility model absolute type encoder interface controller schematic diagram.
Embodiment
To make the purpose, technical scheme and advantage of the utility model embodiment clearer, below in conjunction with of the invention real
The accompanying drawing in example is applied, the technical scheme in the embodiment of the utility model is clearly and completely described, it is clear that be described
Embodiment is the utility model part of the embodiment, rather than whole embodiments.Based on the embodiment in the present invention, this area
Those of ordinary skill is obtained under the premise of creative work is not made
Below in conjunction with the accompanying drawings and specific embodiment further illustrates the technical solution of the utility model：
It is as shown in Figure 1 a kind of coder transitions device of EPA interface, including at least FPGA module, ARM moulds
Block, EPA physical layer block and encoder interfaces module, wherein the encoder interfaces module increases including at least TTL
Amount formula encoder interfaces, sine and cosine incremental encoder interface, absolute type encoder interface, to realize FPGA and encoder
Communication connection, and according to corresponding serial encoder agreement, the output signal of transmission corresponding encoded device；The FPGA module is at least
Encoded including the increment type TTL interface controllers being connected with the TTL incremental encoders interface and the sine and cosine increment type
The increment type sine and cosine interface controller of device interface connection, the absolute type encoder being connected with the absolute type encoder interface connect
Mouth controller；The FPGA module is communicated through the encoder interfaces module with encoder, and what encoder was sent is serial
Data are decoded, while encoder position information is converted into EPA message, are sent to EPA physical layer
Module；The ARM circuit modules comprise at least FSMC bus control units, can be carried out by FSMC buses and FPGA circuitry module
Communication, realize that the control to FPGA module and register are read；The EPA physical layer block, including at least it is special with
Too net physics transceiver, to realize the connection of FPGA module and EPA.As the preferable embodiment party of the utility model
Formula, EPA physical layer block are connected by MII buses with FPGA, and TTL encoder interfaces modules, sine and cosine encoder connects
Mouth mold block, absolute type encoder interface module are connected by FPGA I/O pin with FPGA.
The Max10 10M16SC chips of the preferred altera corp of fpga chip, the preferred ST of arm processor in the utility model
The STM32F103 chips of company.Arm processor is the core processor of the present apparatus.Arm processor by FSMC buses respectively with
Increment type TTL interface controllers, increment type sine and cosine interface controller, absolute type encoder interface controller, ethernet mac control
Device processed is connected.STM32F103 is 32 ARM microcontrollers that ST Microelectronics produces, and belongs to world-leading ARM
Cortex-M microprocessors, have a first-class peripheral hardware, low-power consumption, high-performance, the advantages of high integration.The utility model utilizes
FPGA programmable features, increment type TTL interface controllers, increment type sine and cosine Interface Controller are integrated with fpga chip
Device, absolute type encoder interface controller, ethernet mac layer module, form the high embedded system of an integrated level.Industry with
Too net physical layer block, realized by dedicated ethernet physics transceiver, namely PHY chip.PHY chip can be by EPA
The parallel data that MAC layer module is sent, is converted into serial data stream, while enter according to the coding rule of EPA physical layer
Row coding, then data signal is changed into analog signal and sent, receive the flow of data in contrast.Ethernet physics is received and dispatched
Device realizes the Precision Time Protocol transceiver DP83640 of preferred TI companies.
Further, the FPGA module is also integrated with EPA MAC layer module, as shown in Fig. 2 EPA
In FPGA envelop of function, i.e., the fpga chip being made up of five big main modulars will be completed each functional module of MAC layer module
The repertoire of EPA MAC layer：Message receiving module, physical chip control module, MAC layer control module, CPU numbers
According to interface module and message sending module.
Message receiving module：EPA MAC layer chip is carried out with physical chip using standard ethernet MII interfaces
Data transfer.After transmitting procedure starts, receiving module receives the nibble data on data wire first, half then will received
Byte data is assembled into single byte of data, and the network data of reception is verified, and the errorless data of terminal check are stored
To reception data buffer.
Physical chip control module, EPA MAC layer are completed to ether by two signal wires (MDC and MDIO)
Net physical chip, namely the control of PHY chip and the access of register.MDC, MDIO are drawn by FPGA IO, wherein MDC numbers
According to management clock line, as the reference clock of serial data bus, MDIO is bidirectional serial data lines, and MAC layer passes through this signal
Line completes the register read-write operation to PHY chip.
Cpu data interface module：Using 16 bit data bus and the FSMC bus structures of 8 bit address buses, change can mould
Block realizes the control operation of read-write capability between CPU and FPGA data buffering area and CPU to FPGA.
Message sending module：MAC layer module sends message frame to physical chip in units of nibble.MAC layer with
MII GMIIs are used between physical chip.Sending MII interface signals includes：Send data/address bus TXD [3:0], send
Clock TXD_CLK, enable signal TX_EN is sent, above signal is connected by FPGA IO with physical chip respectively.It is special
It is rising edge synch with tranmitting data register that transmission process between chip and PHY chip is same, with the nibble on data/address bus
Data are that unit sends whole network message data stream to PHY chip.MAC layer chip first will before data flow transmission
Transmission enable signal TX_EN, which is set to high level, makes it effectively, after PHY chip detects the change of the signal, prepares receiving and comes from
The nibble data of MAC layer chip.The transmission data buffer zone of MAC layer chip uses the similar table tennis for receiving data buffer zone
Ram mechanism.The transmission mechanism can effectively lift data-forwarding rate, reduce intra-node hardware delay.
MAC layer control module：The Initial message type sent including in initial phase, judging main frame, improves inquiry
The every terms of information of message and response message (such as present apparatus total counter, present apparatus MAC Address value information etc.).It is real-time in the cycle
In the communication stage, the responsible extraction present apparatus should command information, addition present apparatus feedback information be medium to network message accordingly.
As shown in figure 3, TTL incremental encoders interface comprises at least TTL differential drive circuits, by encoder output
TTL standard signals differential conversion is single sided pulse signal, enters row data communication with fpga chip.The TTL incremental encoders
Interface is connected by the TTL pulse counting module of FPGA I/O pin and FPGA increment type TTL interface controllers, the TTL
Pulse counter module is used to count the pulse for being input to FPGA.TTL encoder interfaces module includes differential conversion chip,
It is preferred that the AM26LV32 differential received chips using TI companies.
As shown in figure 4, the sine and cosine incremental encoder interface comprises at least preamplifier, a/d converter, to compiling
Code device output signal carries out preposition amplification, filtering, analog-to-digital conversion process, and data are carried out by USB and fpga chip
Communication.The increment type sine and cosine interface controller connection of the sine and cosine incremental encoder interface and FPGA, the increment type
Sine and cosine interface controller comprises at least ADC controllers, sine and cosine subdividing module, wherein the ADC controllers will collect
Sine and cosine encoder data transfer is to sine and cosine subdividing module, and the sine and cosine subdividing module from ADC controllers to receiving
Data are finely divided processing, mainly include：Table look-up, it is determined that current sampled value is which position in the sine and cosine cycle；Ask
With, by encoder rotation number of full circle with do not complete the number of turns be added, obtain final exact position.
As the preferable embodiment of the utility model, sine and cosine encoder interface module connects the increasing of sine and cosine interface class
Amount formula encoder, the differential signal of incremental encoder output is subjected to preposition amplification and filtering, then entered by ADC conversion chips
Row analog-to-digital conversion, converts analog signals into data signal, is connected by universal serial bus with FPGA, carries out follow-up processing.Just
Cosine encoder interfaces module includes pre-amplification circuit and ADC change-over circuits.Pre-amplification circuit belongs in present embodiment
Differential amplifier circuit, the ADA4940 chips of the preferred ADI companies of difference amplifier, the AD4003 of the preferred ADI companies of ADC conversion chips
Chip.
Further, the absolute type encoder interface comprises at least RS485 serial protocol conversion chips, and encoder is passed
Defeated dedicated serial data protocol signal carries out differential-to-single-ended conversion, and semiduplex data communication is carried out with fpga chip.
The S65C1168 two-way differential drivers of the preferred TI companies of conversion chip of present embodiment.The absolute type encoder interface with
FPGA absolute type encoder interface controller connection, as shown in figure 5, the absolute type encoder interface controller comprises at least
Endat interface modules, BISS interface modules, river interface module of rubbing more, SSI interface modules, wherein, Endat interface modules are used for
The SOD serial output data of Endat protocol interface encoders is read, BISS interface modules are used to read BISS protocol interface encoders
SOD serial output data, river interface module of rubbing more is used for the SOD serial output data for reading the river protocol interface encoders that rub more, and SSI connects
Mouth mold block is used for the SOD serial output data for reading SSI protocol interface encoders.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, either which part or all technical characteristic are entered
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (8)
- A kind of 1. coder transitions device of EPA interface, including at least FPGA module, ARM modules, EPA Physical layer block and encoder interfaces module, it is characterised in that：The encoder interfaces module comprise at least TTL incremental encoders interface, sine and cosine incremental encoder interface, definitely Formula encoder interfaces, to realize FPGA and encoder communication connection, and according to corresponding serial encoder agreement, transmit phase Answer the output signal of encoder；The FPGA module comprise at least be connected with the TTL incremental encoders interface increment type TTL interface controllers, and The increment type sine and cosine interface controller and the absolute type encoder interface of the sine and cosine incremental encoder interface connection The absolute type encoder interface controller of connection；The FPGA module is led to through the encoder interfaces module with encoder News, are decoded to the serial data that encoder is sent, while encoder position information is converted into EPA message, are sent out Give EPA physical layer block；The ARM circuit modules comprise at least FSMC bus control units, can be carried out by FSMC buses and FPGA circuitry module Communication, realize that the control to FPGA module and register are read；The EPA physical layer block, including at least dedicated ethernet physics transceiver, to realize FPGA module with The connection of EPA.
- 2. the coder transitions device of EPA interface according to claim 1, it is characterised in that the FPGA moulds Block also includes EPA MAC layer module, and the EPA MAC layer module comprises at least message receiving module, physics Layer chip controls and access modules, message analysis and processing module, cpu data interface module and message sending module.
- 3. the coder transitions device of EPA interface according to claim 1, it is characterised in that the TTL increments Formula encoder interfaces comprise at least TTL differential drive circuits, and the TTL standard signals differential conversion that encoder is exported is single-ended arteries and veins Signal is rushed, enters row data communication with fpga chip.
- 4. the coder transitions device of EPA interface according to claim 3, it is characterised in that the TTL increments Formula encoder interfaces are connected by the TTL pulse counting module of FPGA I/O pin and FPGA increment type TTL interface controllers, The TTL pulse counting module is used to count the pulse for being input to FPGA.
- 5. the coder transitions device of EPA interface according to claim 1, it is characterised in that the sine and cosine Incremental encoder interface comprises at least preamplifier, a/d converter, and preposition amplification, modulus are carried out to encoder output Conversion process, enter row data communication by USB and fpga chip.
- 6. the coder transitions device of EPA interface according to claim 5, it is characterised in that the sine and cosine Incremental encoder interface and FPGA increment type sine and cosine interface controller connect, the increment type sine and cosine interface controller Including at least ADC controllers, sine and cosine subdividing module, wherein the sine and cosine encoder data that the ADC controllers will collect Sine and cosine subdividing module is transferred to, the sine and cosine subdividing module is finely divided processing to the data received from ADC controllers.
- 7. the coder transitions device of EPA interface according to claim 1, it is characterised in that the absolute type Encoder interfaces comprise at least RS485 serial protocol conversion chips, and the dedicated serial data protocol signal of encoder transmission is entered The differential-to-single-ended conversion of row, semiduplex data communication is carried out with fpga chip.
- 8. the coder transitions device of EPA interface according to claim 7, it is characterised in that the absolute type Encoder interfaces and FPGA absolute type encoder interface controller connect, and the absolute type encoder interface controller at least wraps Interface module containing Endat, BISS interface modules, river interface module of rubbing more, SSI interface modules, wherein, Endat interface modules are used In the SOD serial output data for reading Endat protocol interface encoders, BISS interface modules are used to read BISS protocol interfaces coding The SOD serial output data of device, river interface module of rubbing more are used for the SOD serial output data for reading the river protocol interface encoders that rub, SSI more Interface module is used for the SOD serial output data for reading SSI protocol interface encoders.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107360195A (en) * | 2017-09-08 | 2017-11-17 | 科德数控股份有限公司 | A kind of coder transitions device of EPA interface |
| CN110618827A (en) * | 2019-08-26 | 2019-12-27 | 国网河南省电力公司洛阳供电公司 | FPGA remote upgrading method with built-in FLASH |
| CN110940359A (en) * | 2018-09-25 | 2020-03-31 | 发那科株式会社 | Encoder and control system |
| CN113938530A (en) * | 2021-09-09 | 2022-01-14 | 中国联合网络通信集团有限公司 | Data transmission method and device |
| CN115145857A (en) * | 2022-09-05 | 2022-10-04 | 中国船舶重工集团公司第七0七研究所 | Interface protocol converter conversion method and FPGA system for executing method |
-
2017
- 2017-09-08 CN CN201721148112.7U patent/CN207200759U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107360195A (en) * | 2017-09-08 | 2017-11-17 | 科德数控股份有限公司 | A kind of coder transitions device of EPA interface |
| CN107360195B (en) * | 2017-09-08 | 2023-12-01 | 科德数控股份有限公司 | Encoder conversion device of industrial Ethernet interface |
| CN110940359A (en) * | 2018-09-25 | 2020-03-31 | 发那科株式会社 | Encoder and control system |
| CN110618827A (en) * | 2019-08-26 | 2019-12-27 | 国网河南省电力公司洛阳供电公司 | FPGA remote upgrading method with built-in FLASH |
| CN113938530A (en) * | 2021-09-09 | 2022-01-14 | 中国联合网络通信集团有限公司 | Data transmission method and device |
| CN113938530B (en) * | 2021-09-09 | 2023-06-23 | 中国联合网络通信集团有限公司 | Data transmission method and device |
| CN115145857A (en) * | 2022-09-05 | 2022-10-04 | 中国船舶重工集团公司第七0七研究所 | Interface protocol converter conversion method and FPGA system for executing method |
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