CN110618827A - FPGA remote upgrading method with built-in FLASH - Google Patents
FPGA remote upgrading method with built-in FLASH Download PDFInfo
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Abstract
The invention discloses a built-in Flash FPAG remote upgrading system which comprises an upper computer, an Ethernet chip, an FPGA and a dial switch. Also discloses a built-in Flash FPAG remote upgrading method, generating and downloading FPGA factory firmware; generating and updating an application mirror image; and erasing, unlocking, writing an application mirror image, locking, checking, loading the application mirror image and the like by the built-in Flash. The invention provides a convenient upgrading method for the FPGA with built-in Flash, and the upgrading of the FPGA can be realized without disassembling the machine. The application range is wide.
Description
Technical Field
The invention relates to the field of digital overhaul and test of secondary equipment of an intelligent substation, in particular to a method for remotely upgrading an FPGA (field programmable gate array) with a built-in FLASH.
Background
With the rapid development of intelligent power grids in China, more and more intelligent substations are provided, and a large number of test instruments are needed for detection and testing of secondary equipment in the substations. Generally, these test and measurement instruments have requirements for customized functions, diversified interfaces, and the like. Therefore, the FPGA (Field-Programmable Gate Array) chip is very suitable for being applied to electric power secondary test and measurement instruments.
At present, the traditional FPGA is based on SRAM (Static Random-Access Memory) technology, and this type of FPGA must be externally provided with a configuration Flash Memory chip for storing programs. And when the Flash memory chip is powered on, the FPGA loads a program from the Flash memory chip into the FPGA to complete the program loading process of the FPGA. The loading process has the duration from dozens of millimeters to several seconds, and some test instruments needing quick loading cannot meet the field requirement; in addition, the content of the external Flash chip is easy to read and copy, which causes the confidentiality of the product to be poor and the intellectual property right to be not guaranteed. An FPGA with built-in Flash storage is very easy to solve these problems. For example, MAX10 FPGA of Intel corporation is built in Flash memory, and the Flash memory is loaded quickly without exceeding millisecond level, is not read and copied and has good confidentiality.
The FPGA upgrading method of the external Flash chip based on the traditional SRAM framework generally comprises the following steps: the JTAG downloader updates the internal program and the external processor (such as ARM \ DSP), and the hardware selection switch and other circuits to directly erase and write the Flash chip.
Although the internal program of the FPGA with the built-in Flash memory chip can be updated by a JTAG downloader, the method can only be realized by disassembling the FPGA on site or returning to a manufacturer for processing. And the Flash storage module in the FPGA cannot be erased and written in an external processor (such as ARM \ DSP) mode.
Disclosure of Invention
The invention aims to avoid the defects in the prior art and provides a method for remotely upgrading an FPGA with a built-in FLASH.
The invention achieves the following technical effects:
a FPAG remote upgrading method of a built-in Flash comprises the following steps:
step 1, running Quartus software by an upper computer, and generating FPGA factory firmware containing an upgrade image through the Quartus software;
step 2, downloading the FPGA factory firmware to an upgrading area of a built-in Flash of the FPGA by using Quartus software through a JTAG interface and an FPGA downloader;
step 3, compiling and generating an application mirror image by using Quartus software;
step 4, restarting the FPGA, setting a toggle switch connected with the FPGA to be a low level, and after the FPGA4 identifies that the toggle switch inputs the low level, loading an upgrade mirror image by the FPGA from an upgrade area of a built-in Flash;
step 5, the upper computer runs FPGA upgrading software and loads the application mirror image generated in the step 3;
step 6, the FPGA upgrading software communicates with the FPGA through the Ethernet to acquire information of a hardware platform of the FPGA, and judges whether the loaded application mirror image corresponds to the hardware platform of the FPGA according to the information of the hardware platform of the FPGA, if so, step 7 is executed, otherwise, step 5 is executed;
step 7, the FPGA upgrading software issues an erasing command and sets a communication protocol data packet according to the erasing command, the communication protocol data packet is sent to the FPGA through the Ethernet, and step 8 is executed;
step 8, after receiving a communication protocol data packet sent by FPGA upgrading software through the Ethernet, the FPGA sends the communication protocol data packet to an upgrading module arranged in the FPGA, the upgrading module analyzes an erasing command in the communication protocol data packet and sends the erasing command to a time sequence control module arranged in the FPGA, and the time sequence control module generates a corresponding erasing time sequence according to the erasing command to erase the built-in Flash;
step 9, the time sequence control module actively reads a control state register with a built-in Flash, the time sequence control module judges whether the erasure is successful or not according to the control state register within a set time, if the erasure is successful, an erasure success signal is generated and sent to the upgrading module, if the erasure is unsuccessful, an erasure failure signal is generated and sent to the upgrading module, the upgrading module sets a communication protocol data packet according to the erasure success signal or the erasure failure signal and sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes the erasure success signal or the erasure failure signal according to the communication protocol data packet, if the erasure success signal is the erasure success signal, the step 10 is executed, and if the erasure failure signal is the erasure failure signal, the step 5 is returned;
step 10, the FPGA upgrading software issues an unlocking command and sets a communication protocol data packet according to the unlocking command, and the FPGA upgrading software sends the communication protocol data packet to the FPGA through the Ethernet;
step 11, after receiving a communication protocol data packet sent by FPGA upgrade software through an Ethernet, the FPGA sends the communication protocol data packet to an upgrade module built in the FPGA4, the upgrade module analyzes an unlocking command in the communication protocol data packet and sends the unlocking command to a time sequence control module built in the FPGA, and the time sequence control module generates a corresponding unlocking time sequence according to the unlocking command to unlock the built-in Flash;
step 12, the time sequence control module actively reads a control state register with a built-in Flash, the time sequence control module judges whether the unlocking is successful or not according to the control state register within a set time, if the unlocking is successful, an unlocking success signal is generated and sent to the upgrading module, if the unlocking is unsuccessful, an unlocking failure signal is generated and sent to the upgrading module, the upgrading module sets a communication protocol data packet according to the unlocking success signal or the unlocking failure signal and sends the communication protocol data packet to the FPGA upgrading software, the FPGA upgrading software analyzes the unlocking success signal or the unlocking failure signal according to the communication protocol data packet, if the unlocking success signal is the unlocking success signal, the step 13 is executed, and if the unlocking failure signal is the erasing failure signal, the step 5 is returned;
step 13, the FPGA upgrading software acquires application mirror image data of set bytes of the application mirror image every time, issues a write data command, and sets a communication protocol data packet according to the write data command and the application mirror image data of the set bytes;
step 14, after receiving a communication protocol data packet sent by FPGA upgrade software through an Ethernet, the FPGA sends the communication protocol data packet to an upgrade module built in the FPGA, the upgrade module analyzes a write data command and application mirror image data with set bytes in the communication protocol data packet and sends the write data command to a time sequence control module built in the FPGA, the time sequence control module generates a corresponding write data time sequence according to the write data command and writes the application mirror image data with the set bytes into an application area with built-in Flash through the write data time sequence;
step 15, the time sequence control module actively reads the control status register of the built-in Flash, the time sequence control module judges whether the data writing is successful according to the control status register within the set time, if the data writing is successful, a data writing success signal is generated and sent to the upgrading module, if the data writing is unsuccessful, a data writing failure signal is generated and sent to the upgrading module,
the upgrading module sets a communication protocol data packet according to the data writing success signal or the data writing failure signal; the upgrading module sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes a data writing success signal or a data writing failure signal according to the communication protocol data packet, if the communication protocol data packet is the data writing success signal, the step 16 is executed, and if the communication protocol data packet is the data writing failure signal, the step 5 is returned;
step 16, repeating the steps 13-15 until all application images are written into the application area with the built-in Flash, and executing the step 17 after all application images are written;
step 17, the FPGA upgrade software issues a read data command, reads an application area with a built-in Flash, sets a communication protocol data packet according to the read data command, and sends the communication protocol data packet to the FPGA4 through the Ethernet;
step 18, after receiving the communication protocol data packet sent by the FPGA upgrading software through the Ethernet, the FPGA sends the communication protocol data packet to the upgrading module arranged in the FPGA, the upgrading module analyzes the data reading command in the communication protocol data packet and sends the data reading command to the time sequence control module arranged in the FPGA, the time sequence control module generates corresponding data reading time sequence according to the data reading command to carry out data reading operation of the application mirror image with set length on the application area with the built-in Flash,
step 19, the time sequence control module actively reads a control state register with a built-in Flash, the time sequence control module judges whether the data reading is successful or not according to the control state register within a set time, if the data reading is successful, a data reading success signal is generated and sent to the upgrading module, if the data reading is unsuccessful, a data reading failure signal is generated and sent to the upgrading module, the upgrading module sets a communication protocol data packet according to the data reading success signal or the data reading failure signal and sends the communication protocol data packet to the FPGA upgrading software, the FPGA upgrading software analyzes the data reading success signal or the data reading failure signal according to the communication protocol data packet, if the data reading success signal is the data reading success signal, the step 20 is executed, and if the data reading failure signal is the;
step 20, repeating the steps 17-19 until all application images stored in the application area with the built-in Flash are read out to the FPGA upgrading software;
step 21, the FPGA upgrading software compares the read application mirror image with the application mirror image selected in the step 3, if the read application mirror image is consistent with the application mirror image selected in the step 3, the step 22 is executed, and if the read application mirror image is not consistent with the application mirror image selected in the step 3, the step 5 is executed;
step 22, the FPGA upgrading software issues a locking command, sets a communication protocol data packet according to the locking command, and sends the communication protocol data packet to the FPGA through the Ethernet;
step 23, after receiving a communication protocol data packet sent by FPGA upgrading software through the Ethernet, the FPGA sends the communication protocol data packet to an upgrading module arranged in the FPGA, the upgrading module analyzes a locking command in the communication protocol data packet and sends the locking command to a time sequence control module arranged in the FPGA, and the time sequence control module generates a corresponding locking time sequence according to the locking command to lock an application area with Flash arranged in the FPGA;
step 24, the time sequence control module actively reads a control state register with a built-in Flash, the time sequence control module judges whether the locking is successful or not according to the control state register within a set time, if the locking is successful, a locking success signal is generated and sent to the upgrading module, if the locking is unsuccessful, a locking failure signal is generated and sent to the upgrading module, the upgrading module sets a communication protocol data packet according to the locking success signal or the locking failure signal and sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes the locking success signal or the locking failure signal according to the communication protocol data packet, if the locking success signal is the locking success signal, the step 25 is executed, and if the locking failure signal is the locking failure signal, the step 5 is returned;
and 25, setting the toggle switch to be at a high level, and loading the application mirror image after the FPGA identifies the input of the high level by the toggle switch.
2. The FPAG remote upgrade method of built-in Flash according to claim 1, wherein the first byte of the communication protocol data packet represents a command type, the command type is a write command, a read command, write data, or read data;
the second byte and the third byte represent the upper eight bits and the lower eight bits as the effective data length;
the fourth byte represents the operating state;
the fifth byte to the eighth byte represent addresses, and if the command type is a write command or a read command, the addresses are control state register addresses of the built-in Flash; if the command type is write data or read data, the address is a storage address of the built-in Flash;
data from the ninth byte;
a communication protocol data packet is a minimum of 64 bytes.
Compared with the prior art, the invention has the following beneficial effects:
1. the electric connection relation is simple, and the FPGA program can be upgraded only by using the connection between the upper computer and the FPGA.
2. The built-in Flash is arranged in the FPGA, and other personnel except product research personnel are difficult to obtain the configuration file stored by the internal Flash, so that the device obtains higher confidentiality.
3. For part of industries needing rapid power-on loading of the FPGA, the invention supports the power-on loading speed of the FPGA up to millisecond level.
4. The invention provides a remote FPGA (field programmable gate array) upgrading method, which avoids the dismantling and upgrading of products.
Drawings
FIG. 1 is a schematic structural diagram of a FPAG remote upgrade system with built-in Flash according to the present invention;
FIG. 2 is a schematic view of a partition of a built-in Flash according to the present invention;
FIG. 3 is a schematic view of the internal structure of the FPAG of the present invention;
FIG. 4 is a schematic diagram of the read-write flow of the built-in Flash according to the present invention;
FIG. 5 is a flow chart of FPGA upgrade of the present invention;
fig. 6 is a diagram illustrating format definitions of a communication protocol packet.
In the figure, 1-an upper computer; 2-Ethernet; 3-an Ethernet chip; 4-FPGA; 41-built-in Flash; 5-dial switch.
Detailed Description
The present invention will be described in further detail with reference to examples for the purpose of facilitating understanding and practice of the invention by those of ordinary skill in the art, and it is to be understood that the present invention has been described in the illustrative embodiments and is not to be construed as limited thereto.
The invention provides a built-in Flash FPAG remote upgrading system. The method comprises the following steps: host computer 1, ethernet chip 3, FPGA4 and dial-up switch 5.
Wherein, the upper computer 1 runs FPGA upgrading software; the Ethernet chip 3 is used for the Ethernet data communication between the upper computer 1 and the FPGA 4; the FPGA4 is used to load configuration files to implement different logic functions. The dial switch 5 generates a high-low level and outputs to an I/O pin of the FPGA 4. The upper computer 1, the Ethernet chip 3 and the FPGA4 are sequentially connected, and the output of the dial switch 5 is connected to an I/O pin of the FPGA4, as shown in FIG. 1.
The upper computer 1 communicates with the FPGA4 through Ethernet,
the FPGA4 has a built-in Flash (nonvolatile memory) provided therein. The storage space with Flash inside is divided into an upgrading area and an application area. The upgrade area stores an upgrade image, and the application area stores an application image. The FPGA4 has multiple image loading functions, i.e., different logic functions are implemented by loading upgrade images or application images.
Preferably, the FPGA4 is a MAX10 FPGA from Intel corporation.
The upgrading mirror image is loaded to enable the FPGA4 to be in a remote upgrading state, at the moment, the FPGA4 can be in Ethernet communication with FPGA upgrading software operated by an upper computer, and then the FPGA4 application mirror image is updated. The application image is loaded to enable the FPGA4 to be in a normal service function state, and at the moment, the FPGA4 can realize product-level functions.
The upgrade image and the application image both comprise a power-on start controller, and the power-on start controller uses a Dual Configuration IP core to complete the loading of the FPGA4 image file. And the power-on starting controller realizes the function that the FPGA only loads the upgrade mirror image when the input low level is detected, and the FPGA only loads the application mirror image when the input high level is detected.
The dip switches 5 only provide a high low state for the FPGA 4.
A method for remotely upgrading an FPGA program with built-in Flash comprises the following steps:
step 1, the upper computer 1 runs the Quartus software, sets an FPGA Configuration mode as Internal Configuration and a loading mode as Dual Compressed Images in the Quartus software, then compiles and generates an upgrade image, opens a Convert Programming File interface of the Quartus software, adds the upgrade image, and generates FPGA factory firmware containing the upgrade image.
And 2, downloading the FPGA factory firmware to an upgrading area of a built-in Flash of the FPGA4 by using Quartus software through a JTAG interface and an FPGA downloader.
And 3, compiling and generating an application image by using Quartus software.
And 4, restarting the FPGA4, setting the toggle switch to be at a low level, enabling the toggle switch to input the low level to an I/O pin of the FPGA4, and after the FPGA4 identifies the input low level of the toggle switch, loading an upgrade image from an upgrade area with built-in Flash through a Dual Configuration IP core. After the upgrade image is loaded, the FPGA4 has a remote upgrade capability, that is, the upper computer completes the update of the application image of the FPGA4 in an ethernet manner.
And 5, the upper computer 1 runs the FPGA upgrading software and loads the application mirror image generated in the step 3.
And 6, communicating the FPGA upgrading software with the FPGA4 through the Ethernet to acquire information of a hardware platform of the FPGA4, judging whether the loaded application mirror image corresponds to the hardware platform of the FPGA4 or not according to the information of the hardware platform of the FPGA4, and executing the step 7 if the loaded application mirror image corresponds to the hardware platform of the FPGA4, otherwise, executing the step 5.
Step 7, the FPGA upgrading software issues an erasing command, erases an application area with built-in Flash, sets a communication protocol data packet according to the erasing command,
the first byte of the communication protocol Data packet represents the command type (Opt-CMD), 0x 00-represents the Write command (Write CMD/Status), 0x 01-represents the Read command (Read CMD/Status), 0x 02-represents the Write Data (Write Flash Data), and 0x 03-represents the Read Data (Read Flash Data);
the second byte and the third byte are expressed as the upper eight bits (Opt-len H) and the lower eight bits (Opt-len L) of the effective data length (Opt-len), wherein the effective data length refers to the effective data length from the eighth byte (Opt-data) in the communication protocol data packet;
the fourth byte is represented as the operating state (Opt-status); the operation state is only effective when the FPGA4 sends a communication protocol data packet to FPGA upgrading software operated by an upper computer, and after the FPGA4 executes a command issued by the upper computer software, the operation state is set to 0x01 to indicate that the current operation is finished, otherwise, the operation state is set to 0x00 to indicate that the current operation is not finished.
The fifth byte to the eighth byte represent an address (Opt-Addr) which is a control status register address of the built-in Flash if the command type (Opt-cmd) is a "write command" or a "read command"; if the command type is 'write data' or 'read data', the address is the storage address of the built-in Flash;
represents data (Opt-data) from the ninth byte;
a communication protocol data packet is a minimum of 64 bytes.
The method for setting the communication protocol data packet according to the erasing command comprises the following steps: the command type is set to a write command 0x00, the effective data length (Opt-len) is set to 0x0001, the operation state (Opt-status) is set to 0x00, the address (Opt-Addr) is set to 0x00000001, the first four bytes of data (Opt-data) are set to 0xFF9FFFFF, and the following data (Opt-data) are filled with 0 to satisfy a minimum 64-byte ethernet data frame. After the packaging is completed, the packet is sent to the FPGA4 through the ethernet interface, and step 8 is executed.
Step 8, after receiving a communication protocol data packet sent by the FPGA upgrading software through the ethernet interface, the FPGA4 sends the communication protocol data packet to an upgrading module built in the FPGA4, the upgrading module analyzes an erasing command in the communication protocol data packet and sends the erasing command to a timing sequence control module built in the FPGA4, the timing sequence control module generates a corresponding erasing timing sequence according to the erasing command to erase the built-in Flash, and the functional structure is as shown in fig. 3. Step 9 is then performed.
And 9, actively reading a control state register of the built-in Flash by the time sequence control module, and automatically setting a corresponding bit of the control state register to be 1 when the erasure is successful, or else, setting the corresponding bit to be 0. The sequential control module judges that the erasing is successful according to the control state register within 5 seconds, an erasing success signal is generated and sent to the upgrading module, otherwise, an erasing failure signal is generated and sent to the upgrading module, and the upgrading module sets a communication protocol data packet according to the erasing success signal or the erasing failure signal;
the upgrading module sets the communication protocol data packet according to the erasing success signal or the erasing failure signal and comprises the following steps:
the command type (Opt-cmd) is set to a 0x00 write command, the valid data length (Opt-len) is set to 0x0001, if the operation state (Opt-status) is set to 0x01 for the erase success signal, if the operation state (Opt-status) is set to 0x00 for the erase failure signal, the address (Opt-Addr) is set to 0x00000000, the data (Opt-data) of the first four bytes is set to 0 xfffffe 0, and the subsequent data (Opt-data) bytes are padded with 0 to satisfy the minimum 64-byte ethernet data frame.
And the upgrading module sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes an erasing success signal or an erasing failure signal according to the communication protocol data packet, if the erasing success signal is the erasing success signal, the step 10 is executed, and if the erasing failure signal is the erasing failure signal, the step 5 is returned.
Step 10, the FPGA upgrading software issues an unlocking command, unlocks the Flash application area, sets a communication protocol data packet according to the unlocking command, and sends the communication protocol data packet to the FPGA4 through the Ethernet interface.
The step of setting the communication protocol data packet according to the unlocking command comprises the following steps:
the command type (Opt-cmd) is set to a 0x00 write command, the effective data length (Opt-len) is set to 0x0001, the operation state (Opt-status) is set to 0x00, the address (Opt-Addr) is set to 0x00000001, the first four bytes of data (Opt-data) are set to 0xFF7FFFFF, and the subsequent data (Opt-data) bytes are padded with 0 to satisfy a minimum 64 byte Ethernet data frame. After the packaging is completed, the packet is sent to the FPGA4 through the ethernet interface, and step 11 is executed.
Step 11, after receiving a communication protocol data packet sent by the FPGA upgrade software through the ethernet interface, the FPGA4 sends the communication protocol data packet to an upgrade module built in the FPGA4, the upgrade module analyzes an unlocking command in the communication protocol data packet and sends the unlocking command to a timing sequence control module built in the FPGA4, the timing sequence control module generates a corresponding unlocking timing sequence according to the unlocking command to unlock the built-in Flash, and the functional structure is as shown in fig. 3. Step 12 is then performed.
And step 12, the time sequence control module actively reads a control state register of the built-in Flash, when the unlocking is successful, the corresponding position of the control state register is automatically set to 1, otherwise, the corresponding position is 0. The time sequence control module judges whether the unlocking is successful within 5 seconds according to the control state register, generates an unlocking success signal and sends the unlocking success signal to the upgrading module, otherwise generates an unlocking failure signal and sends the unlocking failure signal to the upgrading module, and the upgrading module sets a communication protocol data packet according to the unlocking success signal or the unlocking failure signal;
the upgrading module sets a communication protocol data packet according to the unlocking success signal or the unlocking failure signal and comprises the following steps:
setting a command type (Opt-cmd) to a 0x00 write command, setting a valid data length (Opt-len) to 0x0001, if an operation state (Opt-status) is set to 0x01 for an unlock success signal, if an operation state (Opt-status) is set to 0x00 for an unlock failure signal, setting an address (Opt-Addr) to 0x00000000, setting a data (Opt-data) of the first four bytes to 0 xffffffffc 0, and padding a subsequent data (Opt-data) byte to 0 to satisfy a minimum 64-byte ethernet data frame. And the upgrading module sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes an unlocking success signal or an unlocking failure signal according to the communication protocol data packet, if the communication protocol data packet is the unlocking success signal, the step 13 is executed, and if the communication protocol data packet is the erasing failure signal, the step 5 is returned.
Step 13, the FPGA upgrade software acquires the maximum 1024-byte application mirror image data of the application mirror image every time, issues a write data command, sets a communication protocol data packet according to the write data command and the maximum 1024-byte application mirror image data,
the method for setting the communication protocol data packet according to the data writing command comprises the following steps:
the command type (Opt-cmd) is set to 0x02 to write data, the effective data length (Opt-len) is set to 0x00FF, the operation state (Opt-status) is set to 0x00, the address (Opt-Addr) is set to 0x00008000, and the acquired 1024 bytes of application image data are padded to the data (Opt-data). After the packaging is completed, the packet is sent to the FPGA4 through the ethernet interface, and step 14 is executed.
14, after receiving a communication protocol data packet sent by the FPGA upgrade software through the ethernet interface, the FPGA4 sends the communication protocol data packet to an upgrade module built in the FPGA4, where the upgrade module parses a write data command and 1024-byte application mirror image data in the communication protocol data packet and sends the write data command to a timing control module built in the FPGA4, the timing control module generates a corresponding write data timing sequence according to the write data command, and writes the 1024-byte application mirror image data into an application area with a Flash built in through the write data timing sequence, where a functional structure is shown in fig. 3. Step 15 is then performed.
And step 15, the time sequence control module actively reads the control state register of the built-in Flash, when the data writing is successful, the corresponding position of the control state register is automatically set to be 1, otherwise, the corresponding position is set to be 0. The time sequence control module judges that the data writing is successful according to the control state register within 5 seconds, a data writing success signal is generated and sent to the upgrading module, otherwise, a data writing failure signal is generated and sent to the upgrading module, and the upgrading module sets a communication protocol data packet according to the data writing success signal or the data writing failure signal;
the upgrading module sets a communication protocol data packet according to the data writing success signal or the data writing failure signal and comprises the following steps:
setting the command type (Opt-cmd) to 0x02 for writing data, setting the effective data length (Opt-len) to 0x0001, if the operation status (Opt-status) is set to 0x01 for the write data success signal, if the operation status (Opt-status) is set to 0x00 for the write data failure signal, setting the address (Opt-Addr) to 0x00008000, setting the data (Opt-data) of the first four bytes to 0 xfffffffffc 8, and padding the bytes of the subsequent data (Opt-data) with 0 to satisfy the minimum 64-byte Ethernet data frame. And the upgrading module sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes a data writing success signal or a data writing failure signal according to the communication protocol data packet, if the communication protocol data packet is the data writing success signal, the step 16 is executed, and if the communication protocol data packet is the data writing failure signal, the step 5 is returned.
And step 16, repeating the steps 13-15 until the application mirror image is completely written into the application area with the built-in Flash, and executing the step 17 after all the application mirror image is completely written.
And step 17, the FPGA upgrading software issues a data reading command, reads an application area with built-in Flash, sets a communication protocol data packet according to the data reading command, and sends the communication protocol data packet to the FPGA4 through the Ethernet interface.
The method for setting the communication protocol data packet according to the read data command comprises the following steps:
the command type (Opt-cmd) is set to 0x03 read data, the effective data length (Opt-len) is set to 0x00FF, the operation state (Opt-status) is set to 0x00, the address (Opt-Addr) is set to 0x00008000, and the data (Opt-data) bytes are padded with 0 to satisfy a minimum 64-byte Ethernet data frame. After the packaging is completed, the packet is sent to the FPGA4 through the ethernet interface, and step 18 is executed.
Step 18, after receiving the communication protocol data packet sent by the FPGA upgrade software through the ethernet interface, the FPGA4 sends the communication protocol data packet to the upgrade module built in the FPGA4, the upgrade module parses the read data command in the communication protocol data packet and sends the read data command to the timing control module built in the FPGA4, the timing control module generates a corresponding read data timing according to the read data command to perform the read data operation of the application image with a set length on the application area with the built-in Flash, and the functional structure is as shown in fig. 3. Step 19 is then performed.
And step 19, the time sequence control module actively reads the control state register of the built-in Flash, when the data reading is successful, the corresponding bit of the control state register is automatically set to be 1, otherwise, the corresponding bit is 0. The time sequence control module judges that the data reading is successful according to the control state register within 5 seconds, a data reading success signal is generated and sent to the upgrading module, otherwise a data reading failure signal is generated and sent to the upgrading module, and the upgrading module sets a communication protocol data packet according to the data reading success signal or the data reading failure signal and sends the communication protocol data packet to FPGA upgrading software;
the upgrading module sets a communication protocol data packet according to the data reading success signal or the data reading failure signal and comprises the following steps:
the command type (Opt-cmd) is set to 0x03 read data, the effective data length (Opt-len) is set to 0x00FF, if the operation state (Opt-status) is set to 0x01 for the read data success signal, if the operation state (Opt-status) is set to 0x00 for the read data failure signal, the address (Opt-Addr) is set to 0x00008000, and the data (Opt-data) is set to the application mirror of the set length of read. The upgrading module sends the communication protocol data packet to the FPGA upgrading software, the FPGA upgrading software analyzes a data reading success signal or a data reading failure signal according to the communication protocol data packet, if the data reading success signal is the data reading success signal, the step 20 is executed, and if the data reading failure signal is the data reading failure signal, the step 5 is returned.
And 20, repeating the steps 17-19 until all application images stored in the application area with the built-in Flash are read out to the FPGA upgrading software, and executing the step 21 after all application images are read out.
And 21, the FPGA upgrading software compares the read application mirror image with the selected application mirror image in the step 3, if the read application mirror image is consistent with the selected application mirror image, the step 22 is executed, and if the read application mirror image is not consistent with the selected application mirror image, the step 5 is executed.
Step 22, the FPGA upgrade software issues a locking command, locks an application area with built-in Flash, sets a communication protocol data packet according to the locking command, and sends the communication protocol data packet to the FPGA4 through the Ethernet interface.
The method for setting the communication protocol data packet according to the locking command comprises the following steps:
the command type (Opt-cmd) is set to a 0x00 write command, the effective data length (Opt-len) is set to 0x0001, the operating state (Opt-status) is set to 0x00, the address (Opt-Addr) is set to 0x00000001, the first four bytes of the data (Opt-data) are 0xFFFFFF, and the subsequent bytes of the data are filled with 0 to satisfy a minimum 64 byte Ethernet data frame. After the packaging is completed, the packet is sent to the FPGA4 through the ethernet interface, and step 23 is executed.
Step 23, after receiving a communication protocol data packet sent by the FPGA upgrade software through the ethernet interface, the FPGA4 sends the communication protocol data packet to an upgrade module built in the FPGA4, the upgrade module analyzes a locking command in the communication protocol data packet and sends the locking command to a timing control module built in the FPGA4, the timing control module generates a corresponding locking timing according to the locking command to lock an application area with Flash built in, and the functional structure is as shown in fig. 3. Step 24 is then performed.
And 24, actively reading a control state register of the built-in Flash by the time sequence control module, and automatically setting a corresponding bit of the control state register to be 1 when the locking is successful, or else, setting the bit to be 0. The time sequence control module judges that the locking is successful according to the control state register within 5 seconds, a locking success signal is generated and sent to the upgrading module, otherwise, a locking failure signal is generated and sent to the upgrading module, and the upgrading module sets a communication protocol data packet according to the locking success signal or the locking failure signal;
the upgrading module sets a communication protocol data packet according to the locking success signal or the locking failure signal and comprises the following steps:
setting a command type (Opt-cmd) to a 0x00 write command, setting a valid data length (Opt-len) to 0x0001, if an operation state (Opt-status) is set to 0x01 for a lock success signal, if an operation state (Opt-status) is set to 0x00 for a lock failure signal, setting an address (Opt-Addr) to 0x00000000, setting data (Opt-data) of the first four bytes to 0 xfffffe 0, and padding a subsequent data (Opt-data) byte with 0 to satisfy a minimum 64-byte ethernet data frame. And the upgrading module sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes a locking success signal or a locking failure signal according to the communication protocol data packet, if the locking success signal is the locking success signal, the step 25 is executed, and if the locking failure signal is the locking failure signal, the step 5 is returned.
And step 25, setting the toggle switch to be at a high level, and loading the program of the application mirror image after the FPGA4 identifies the input high level of the toggle switch. The FPGA4 can realize product-level functions after loading the application image stored in the application area.
And step 26, finishing FPGA upgrading.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (2)
1. A FPAG remote upgrading method of a built-in Flash is characterized by comprising the following steps:
step 1, running Quartus software by an upper computer, and generating FPGA factory firmware containing an upgrade image through the Quartus software;
step 2, downloading the FPGA factory firmware to an upgrading area of a built-in Flash of the FPGA by using Quartus software through a JTAG interface and an FPGA downloader;
step 3, compiling and generating an application mirror image by using Quartus software;
step 4, restarting the FPGA, setting a toggle switch connected with the FPGA to be a low level, and after the FPGA4 identifies that the toggle switch inputs the low level, loading an upgrade mirror image by the FPGA from an upgrade area of a built-in Flash;
step 5, the upper computer runs FPGA upgrading software and loads the application mirror image generated in the step 3;
step 6, the FPGA upgrading software communicates with the FPGA through the Ethernet to acquire information of a hardware platform of the FPGA, and judges whether the loaded application mirror image corresponds to the hardware platform of the FPGA according to the information of the hardware platform of the FPGA, if so, step 7 is executed, otherwise, step 5 is executed;
step 7, the FPGA upgrading software issues an erasing command and sets a communication protocol data packet according to the erasing command, the communication protocol data packet is sent to the FPGA through the Ethernet, and step 8 is executed;
step 8, after receiving a communication protocol data packet sent by FPGA upgrading software through the Ethernet, the FPGA sends the communication protocol data packet to an upgrading module arranged in the FPGA, the upgrading module analyzes an erasing command in the communication protocol data packet and sends the erasing command to a time sequence control module arranged in the FPGA, and the time sequence control module generates a corresponding erasing time sequence according to the erasing command to erase the built-in Flash;
step 9, the time sequence control module actively reads a control state register with a built-in Flash, the time sequence control module judges whether the erasure is successful or not according to the control state register within a set time, if the erasure is successful, an erasure success signal is generated and sent to the upgrading module, if the erasure is unsuccessful, an erasure failure signal is generated and sent to the upgrading module, the upgrading module sets a communication protocol data packet according to the erasure success signal or the erasure failure signal and sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes the erasure success signal or the erasure failure signal according to the communication protocol data packet, if the erasure success signal is the erasure success signal, the step 10 is executed, and if the erasure failure signal is the erasure failure signal, the step 5 is returned;
step 10, the FPGA upgrading software issues an unlocking command and sets a communication protocol data packet according to the unlocking command, and the FPGA upgrading software sends the communication protocol data packet to the FPGA through the Ethernet;
step 11, after receiving a communication protocol data packet sent by FPGA upgrade software through an Ethernet, the FPGA sends the communication protocol data packet to an upgrade module built in the FPGA4, the upgrade module analyzes an unlocking command in the communication protocol data packet and sends the unlocking command to a time sequence control module built in the FPGA, and the time sequence control module generates a corresponding unlocking time sequence according to the unlocking command to unlock the built-in Flash;
step 12, the time sequence control module actively reads a control state register with a built-in Flash, the time sequence control module judges whether the unlocking is successful or not according to the control state register within a set time, if the unlocking is successful, an unlocking success signal is generated and sent to the upgrading module, if the unlocking is unsuccessful, an unlocking failure signal is generated and sent to the upgrading module, the upgrading module sets a communication protocol data packet according to the unlocking success signal or the unlocking failure signal and sends the communication protocol data packet to the FPGA upgrading software, the FPGA upgrading software analyzes the unlocking success signal or the unlocking failure signal according to the communication protocol data packet, if the unlocking success signal is the unlocking success signal, the step 13 is executed, and if the unlocking failure signal is the erasing failure signal, the step 5 is returned;
step 13, the FPGA upgrading software acquires application mirror image data of set bytes of the application mirror image every time, issues a write data command, and sets a communication protocol data packet according to the write data command and the application mirror image data of the set bytes;
step 14, after receiving a communication protocol data packet sent by FPGA upgrade software through an Ethernet, the FPGA sends the communication protocol data packet to an upgrade module built in the FPGA, the upgrade module analyzes a write data command and application mirror image data with set bytes in the communication protocol data packet and sends the write data command to a time sequence control module built in the FPGA, the time sequence control module generates a corresponding write data time sequence according to the write data command and writes the application mirror image data with the set bytes into an application area with built-in Flash through the write data time sequence;
step 15, the time sequence control module actively reads the control status register of the built-in Flash, the time sequence control module judges whether the data writing is successful according to the control status register within the set time, if the data writing is successful, a data writing success signal is generated and sent to the upgrading module, if the data writing is unsuccessful, a data writing failure signal is generated and sent to the upgrading module,
the upgrading module sets a communication protocol data packet according to the data writing success signal or the data writing failure signal; the upgrading module sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes a data writing success signal or a data writing failure signal according to the communication protocol data packet, if the communication protocol data packet is the data writing success signal, the step 16 is executed, and if the communication protocol data packet is the data writing failure signal, the step 5 is returned;
step 16, repeating the steps 13-15 until all application images are written into the application area with the built-in Flash, and executing the step 17 after all application images are written;
step 17, the FPGA upgrade software issues a read data command, reads an application area with a built-in Flash, sets a communication protocol data packet according to the read data command, and sends the communication protocol data packet to the FPGA4 through the Ethernet;
step 18, after receiving the communication protocol data packet sent by the FPGA upgrading software through the Ethernet, the FPGA sends the communication protocol data packet to the upgrading module arranged in the FPGA, the upgrading module analyzes the data reading command in the communication protocol data packet and sends the data reading command to the time sequence control module arranged in the FPGA, the time sequence control module generates corresponding data reading time sequence according to the data reading command to carry out data reading operation of the application mirror image with set length on the application area with the built-in Flash,
step 19, the time sequence control module actively reads a control state register with a built-in Flash, the time sequence control module judges whether the data reading is successful or not according to the control state register within a set time, if the data reading is successful, a data reading success signal is generated and sent to the upgrading module, if the data reading is unsuccessful, a data reading failure signal is generated and sent to the upgrading module, the upgrading module sets a communication protocol data packet according to the data reading success signal or the data reading failure signal and sends the communication protocol data packet to the FPGA upgrading software, the FPGA upgrading software analyzes the data reading success signal or the data reading failure signal according to the communication protocol data packet, if the data reading success signal is the data reading success signal, the step 20 is executed, and if the data reading failure signal is the;
step 20, repeating the steps 17-19 until all application images stored in the application area with the built-in Flash are read out to the FPGA upgrading software;
step 21, the FPGA upgrading software compares the read application mirror image with the application mirror image selected in the step 3, if the read application mirror image is consistent with the application mirror image selected in the step 3, the step 22 is executed, and if the read application mirror image is not consistent with the application mirror image selected in the step 3, the step 5 is executed;
step 22, the FPGA upgrading software issues a locking command, sets a communication protocol data packet according to the locking command, and sends the communication protocol data packet to the FPGA through the Ethernet;
step 23, after receiving a communication protocol data packet sent by FPGA upgrading software through the Ethernet, the FPGA sends the communication protocol data packet to an upgrading module arranged in the FPGA, the upgrading module analyzes a locking command in the communication protocol data packet and sends the locking command to a time sequence control module arranged in the FPGA, and the time sequence control module generates a corresponding locking time sequence according to the locking command to lock an application area with Flash arranged in the FPGA;
step 24, the time sequence control module actively reads a control state register with a built-in Flash, the time sequence control module judges whether the locking is successful or not according to the control state register within a set time, if the locking is successful, a locking success signal is generated and sent to the upgrading module, if the locking is unsuccessful, a locking failure signal is generated and sent to the upgrading module, the upgrading module sets a communication protocol data packet according to the locking success signal or the locking failure signal and sends the communication protocol data packet to FPGA upgrading software, the FPGA upgrading software analyzes the locking success signal or the locking failure signal according to the communication protocol data packet, if the locking success signal is the locking success signal, the step 25 is executed, and if the locking failure signal is the locking failure signal, the step 5 is returned;
and 25, setting the toggle switch to be at a high level, and loading the application mirror image after the FPGA identifies the input of the high level by the toggle switch.
2. The FPAG remote upgrade method of built-in Flash according to claim 1, wherein the first byte of the communication protocol data packet represents a command type, the command type is a write command, a read command, write data, or read data;
the second byte and the third byte represent the upper eight bits and the lower eight bits as the effective data length;
the fourth byte represents the operating state;
the fifth byte to the eighth byte represent addresses, and if the command type is a write command or a read command, the addresses are control state register addresses of the built-in Flash; if the command type is write data or read data, the address is a storage address of the built-in Flash;
data from the ninth byte;
a communication protocol data packet is a minimum of 64 bytes.
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