CN110618827A - FPGA remote upgrading method with built-in FLASH - Google Patents

Abstract

The invention discloses a built-in Flash FPAG remote upgrading system which comprises an upper computer, an Ethernet chip, an FPGA and a dial switch. Also discloses a built-in Flash FPAG remote upgrading method, generating and downloading FPGA factory firmware; generating and updating an application mirror image; and erasing, unlocking, writing an application mirror image, locking, checking, loading the application mirror image and the like by the built-in Flash. The invention provides a convenient upgrading method for the FPGA with built-in Flash, and the upgrading of the FPGA can be realized without disassembling the machine. The application range is wide.

Description

A remote upgrade method of FPGA with built-in FLASH

technical field

The invention relates to the field of digital maintenance and testing of secondary equipment in intelligent substations, in particular to an FPGA remote upgrade method with built-in FLASH.

Background technique

With the rapid development of my country's smart grid, there are more and more smart substations, and the detection and testing of secondary equipment in the station requires a large number of testing instruments. Generally, these testing and measuring instruments have requirements such as functional customization and interface diversification. Therefore, FPGA (Field-Programmable Gate Array) chips are very suitable for application in power secondary testing and measuring instruments.

At present, traditional FPGAs are based on SRAM (Static Random-Access Memory) technology, and this type of FPGA must be equipped with an external configuration Flash memory chip for storing programs. When the power is turned on, the FPGA loads the program from the Flash storage chip into the FPGA to complete the program loading process of the FPGA. The length of this loading process ranges from tens of millimeters to several seconds, which cannot meet the on-site requirements in some test instruments that need to be loaded quickly; in addition, the internal memory of the external Flash chip is easy to be read and copied, resulting in poor confidentiality of the product. Intellectual property rights are not guaranteed. An FPGA with built-in Flash storage can easily solve these problems. For example, Intel's MAX10 FPGA has built-in Flash storage, which can be quickly loaded within milliseconds, is not read and copied, and has good confidentiality.

The FPGA upgrade method of the external Flash chip based on the traditional SRAM architecture is generally: the JTAG downloader updates the internal program and the external processor (such as ARM\DSP), hardware selection switch and other circuits directly erase and write the Flash chip.

Although the FPGA with built-in Flash memory chip can use the JTAG downloader to update the internal program, this method can only be disassembled on site or returned to the manufacturer for processing. However, the method based on an external processor (such as ARM\DSP) cannot erase and write the Flash memory module inside the FPGA.

Contents of the invention

The purpose of the present invention is to avoid the deficiencies in the prior art, and provides a method for remotely upgrading FPGA with built-in FLASH.

The present invention has obtained following technical effect:

A FPAG remote upgrade method with built-in Flash, comprising the following steps:

Step 1. The host computer runs the Quartus software, and the FPGA factory firmware including the upgraded image is generated through the Quartus software;

Step 2. Use the Quartus software to download the FPGA factory firmware to the upgrade area of the FPGA's built-in Flash through the JTAG interface and the FPGA downloader;

Step 3, use the Quartus software to compile and generate an application image;

Step 4. Restart the FPGA, set the toggle switch connected to the FPGA to a low level, and after the FPGA4 recognizes that the toggle switch is input to a low level, the FPGA loads the upgrade image from the upgrade area of the built-in Flash;

Step 5. The host computer runs the FPGA upgrade software and loads the application image generated in step 3;

Step 6. The FPGA upgrade software communicates with the FPGA through Ethernet to obtain the information of the hardware platform of the FPGA, and judges whether the loaded application image corresponds to the hardware platform of the FPGA according to the information of the hardware platform of the FPGA. If so, execute step 7. Otherwise, go to step 5;

Step 7, the FPGA upgrade software issues an erase command and sets the communication protocol data packet according to the erase command, the communication protocol data packet is sent to the FPGA through Ethernet, and step 8 is performed;

Step 8. After the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, it sends the communication protocol data packet to the upgrade module built in the FPGA. The upgrade module parses out the erase command in the communication protocol data packet, and The delete command is sent to the timing control module built in the FPGA, and the timing control module generates a corresponding erasing sequence according to the erasing command to erase the built-in Flash;

Step 9. The timing control module actively reads the control status register of the built-in Flash. The timing control module judges whether the erasing is successful according to the control status register within the set time. If the erasing is successful, an erasing success signal is generated and sent to the upgrade module. If the erasing is unsuccessful, an erasure failure signal is generated and sent to the upgrade module, and the upgrade module sets the communication protocol data packet according to the erasure success signal or the erasure failure signal and sends the communication protocol data packet to the FPGA upgrade software, and the FPGA upgrade software according to The communication protocol data packet parses out the erasing success signal or the erasing failure signal, if it is the erasing success signal, execute step 10, and if it is the erasing failure signal, return to step 5;

Step 10, the FPGA upgrade software issues an unlock command and sets the communication protocol data packet according to the unlock command, and the FPGA upgrade software sends the communication protocol data packet to FPGA through Ethernet;

Step 11, after the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, the communication protocol data packet is sent to the upgrade module built in FPGA4, and the upgrade module parses out the unlock command in the communication protocol data packet, and sends the unlock command Send it to the timing control module built in FPGA, and the timing control module will generate corresponding unlock timing according to the unlock command to unlock the built-in Flash;

Step 12. The timing control module actively reads the control status register of the built-in Flash. The timing control module judges whether the unlocking is successful according to the control status register within the set time. If the unlocking is successful, it generates an unlocking success signal and sends it to the upgrade module. If successful, an unlock failure signal is generated and sent to the upgrade module. The upgrade module sets the communication protocol data packet according to the unlock success signal or the unlock failure signal and sends the communication protocol data packet to the FPGA upgrade software. The FPGA upgrade software parses the unlock data packet according to the communication protocol data packet. Success signal or unlocking failure signal, if it is unlocking success signal, execute step 13, if it is erasing failure signal, return to step 5;

Step 13, the FPGA upgrade software obtains the application image data of the set byte of the application image each time, and issues a write data command, and sets the communication protocol packet according to the write data command and the set byte of the application image data;

Step 14. After the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, the communication protocol data packet is sent to the upgrade module built in the FPGA, and the upgrade module parses out the write data command and the setting word in the communication protocol data packet. The application mirror data of the node, and send the write data command to the timing control module built in FPGA, the timing control module generates the corresponding write data timing according to the write data command, and writes the application mirror data of the set byte through the write data timing Go to the application area with built-in Flash;

Step 15, the timing control module actively reads the control status register of the built-in Flash, and the timing control module judges whether the data writing is successful according to the control status register within the set time. If the data writing is successful, a data writing success signal is generated and sent to the upgrade module. If the write data is unsuccessful, a write data failure signal is generated and sent to the upgrade module,

The upgrade module sets the communication protocol data packet according to the write data success signal or the write data failure signal; the upgrade module sends the communication protocol data packet to the FPGA upgrade software, and the FPGA upgrade software analyzes the write data success signal or the write data failure signal according to the communication protocol data packet , if it is a write data success signal, execute step 16, and if it is a write data failure signal, return to step 5;

Step 16. Repeat steps 13-15 until the application image is completely written into the application area of the built-in Flash, and then execute step 17 after all writing is completed;

Step 17, the FPGA upgrade software issues a read data command, reads the application area of the built-in Flash, and sets the communication protocol packet according to the read data command, and sends the communication protocol packet to FPGA4 via Ethernet;

Step 18. After the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, the communication protocol data packet is sent to the FPGA built-in upgrade module, and the upgrade module parses out the read data command in the communication protocol data packet, and reads The data command is sent to the built-in timing control module of the FPGA, and the timing control module generates the corresponding read data timing according to the read data command to perform the read data operation of the application image with a set length in the application area of the built-in Flash.

Step 19, the timing control module actively reads the control status register of the built-in Flash, and the timing control module judges whether the read data is successful according to the control status register within the set time, if the read data is successful, then generates a read data success signal and sends it to the upgrade module, If the data reading is unsuccessful, a signal of failure to read data is generated and sent to the upgrade module, and the upgrade module sets the communication protocol data packet according to the signal of successful data reading or the signal of failure to read data, and sends the communication protocol data packet to the FPGA upgrade software. The communication protocol data packet is analyzed to read the data success signal or the data reading failure signal, if it is the data reading success signal, then perform step 20, and if it is the data reading failure signal, then return to step 5;

Step 20. Repeat steps 17-19 until all the application images stored in the application area of the built-in Flash are read out to the FPGA upgrade software;

Step 21. The FPGA upgrade software compares the read application image with the application image selected in step 3. If they are consistent, execute step 22; otherwise, execute step 5;

Step 22, the FPGA upgrade software issues a locking command and sets the communication protocol data packet according to the locking command, and sends the communication protocol data packet to FPGA through Ethernet;

Step 23. After the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, the communication protocol data packet is sent to the upgrade module built in the FPGA. The upgrade module parses out the lock command in the communication protocol data packet, and adds The lock command is sent to the built-in timing control module of the FPGA, and the timing control module generates a corresponding lock sequence according to the lock command to lock the application area of the built-in Flash;

Step 24, the timing control module actively reads the control status register of the built-in Flash, and the timing control module judges whether the locking is successful according to the control status register within the set time. If the locking is successful, a locking success signal is generated and sent to the upgrade module. If the lock is unsuccessful, a lock failure signal is generated and sent to the upgrade module. The upgrade module sets the communication protocol data packet according to the lock success signal or the lock failure signal and sends it to the FPGA upgrade software. The FPGA upgrade software analyzes the communication protocol data packet. Locking success signal or locking failure signal, if it is a locking success signal, execute step 25, and if it is a locking failure signal, return to step 5;

Step 25. Set the toggle switch to a high level, and after the FPGA recognizes that the toggle switch has input a high level, load the application image.

2. The FPAG remote upgrade method with a built-in Flash according to claim 1, wherein the first byte of the communication protocol data packet represents the command type, and the command type is a write command or a read command or a write command. data or read data;

The second byte and the third byte represent the high and low eight bits of the valid data length;

The fourth byte represents the operation status;

The fifth byte to the eighth byte represent the address. If the command type is write command or read command, the address is the control status register address of the built-in Flash; if the command type is write data or read data, the address is the built-in Flash Flash storage address;

data starting from the ninth byte;

The communication protocol data packet is at least 64 bytes.

Compared with the prior art, the present invention has the following beneficial effects:

1. The electrical connection is simple, and the upgrade of the FPGA program can be completed only by using the connection between the host computer and the FPGA.

2. The built-in Flash is built into the FPGA, except for product R&D personnel, it is difficult for other personnel to obtain the configuration files stored in the internal Flash, which makes the device obtain higher confidentiality.

3. For some industries that require fast FPGA power-on and loading, the present invention supports the FPGA power-on and loading speed up to millisecond level.

4. The present invention provides an FPGA remote upgrade method, which avoids dismantling and upgrading the product.

Description of drawings

Fig. 1 is the structural representation of the FPAG remote upgrade system of built-in Flash of the present invention;

Fig. 2 is the partition schematic diagram of the built-in Flash of the present invention;

Fig. 3 is the internal structure schematic diagram of FPAG of the present invention;

Fig. 4 is a schematic diagram of the built-in Flash reading and writing process of the present invention;

Fig. 5 is the FPGA upgrading flowchart of the present invention;

FIG. 6 is a format definition diagram of a communication protocol data packet.

In the figure, 1-host computer; 2-Ethernet; 3-Ethernet chip; 4-FPGA; 41-built-in Flash; 5-dip switch.

Detailed ways

In order to facilitate those of ordinary skill in the art to understand and implement the present invention, the present invention will be described in further detail below in conjunction with the examples. It should be understood that the implementation examples described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

The invention provides a FPAG remote upgrade system with built-in Flash. Including: upper computer 1, Ethernet chip 3, FPGA4 and DIP switch 5.

Among them, the host computer 1 runs FPGA upgrade software; the Ethernet chip 3 is used for Ethernet data communication between the host computer 1 and FPGA4; FPGA4 is used for loading configuration files to realize different logic functions. DIP switch 5 generates high and low levels, which are output to the I/O pins of FPGA4. The host computer 1, the Ethernet chip 3, and the FPGA4 are connected sequentially, and the output of the dial switch 5 is connected to the I/O pin of the FPGA4, as shown in Figure 1.

Host computer 1 communicates with FPGA4 via Ethernet,

Built-in Flash (non-volatile storage) is set in the FPGA4. The storage space of the built-in Flash is divided into an upgrade area and an application area. The upgrade area stores the upgrade image, and the application area stores the application image. FPGA4 has the function of loading multiple images, that is, different logic functions can be realized by loading upgrade images or application images.

Preferably, FPGA4 adopts MAX10 FPGA of Intel Corporation.

Loading the upgrade image puts FPGA4 in the remote upgrade state. At this time, FPGA4 can communicate with the FPGA upgrade software running on the host computer through Ethernet, and then complete the update of the FPGA4 application image. Loading the application image makes FPGA4 in a normal business function state, and FPGA4 can implement product-level functions at this time.

Both the upgrade image and the application image include a power-on controller, and the power-on controller uses the DualConfiguration IP core to complete the loading of the FPGA4 image file. The power-on controller implements the function that the FPGA only loads the upgrade image when the input low level is detected, and the FPGA only loads the application image when the input high level is detected.

DIP switch 5 only provides high and low level states for FPGA4.

A method for remotely upgrading an FPGA program with built-in Flash, comprising the following steps:

Step 1. Host computer 1 runs the Quartus software. In the Quartus software, set the FPGA configuration mode to InternalConfiguration, set the loading mode to Dual Compressed Images, then compile and generate the upgrade image, open the Convert Programming File interface of the Quartus software, add the upgrade image, and generate FPGA factory firmware containing the upgrade image.

Step 2. Use the Quartus software to download the FPGA factory firmware to the upgrade area of the built-in Flash of the FPGA4 through the JTAG interface and the FPGA downloader.

Step 3. Use the Quartus software to compile and generate an application image.

Step 4. Restart FPGA4, set the toggle switch to low level, so that the toggle switch inputs low level to the I/O pin of FPGA4. The upgrade area with built-in Flash loads the upgrade image. After the upgrade image is loaded, FPGA4 will have the capability of remote upgrade, that is, the upper computer can complete the update of the FPGA4 application image through Ethernet.

Step 5. Host computer 1 runs the FPGA upgrade software and loads the application image generated in step 3.

Step 6, the FPGA upgrade software communicates with the FPGA4 via Ethernet to obtain the information of the hardware platform of the FPGA4, and judges whether the loaded application image corresponds to the hardware platform of the FPGA4 according to the information of the hardware platform of the FPGA4, and if so, execute step 7, Otherwise, go to step 5.

Step 7. The FPGA upgrade software issues an erase command to erase the application area of the built-in Flash, and set the communication protocol data packet according to the erase command.

The first byte of the communication protocol data packet represents the command type (Opt-cmd), 0x00-represents the write command (WriteCMD/Status), 0x01-represents the read command (Read CMD/Status), 0x02-represents the write data (Write FlashData ), 0x03- means read data (Read Flash Data);

The second byte and the third byte represent the high eight bits (Opt-len H) and low eight bits (Opt-len L) of the effective data length (Opt-len), and the effective data length refers to the communication protocol data Effective data length from the eighth byte (Opt-data) in the packet;

The fourth byte represents the operation status (Opt-status); the operation status is only valid when the FPGA4 sends the communication protocol data packet to the FPGA upgrade software running on the upper computer. After the FPGA4 executes the command issued by the upper computer software, it will operate The status is set to 0x01, indicating that the current operation has been completed, otherwise it is set to 0x00, indicating that the current operation has not been completed.

The fifth byte to the eighth byte represent the address (Opt-Addr). If the command type (Opt-cmd) is "write command" or "read command", the address is the address of the control status register of the built-in Flash; if If the command type is "write data" or "read data", the address is the storage address of the built-in Flash;

Indicate data (Opt-data) from the ninth byte;

The communication protocol data packet is at least 64 bytes.

Setting the communication protocol packet according to the erase command includes the following steps: set the command type to write command 0x00, set the effective data length (Opt-len) to 0x0001, set the operation status (Opt-status) to 0x00, set the address (Opt-Addr ) to 0x00000001, set the first four bytes of data (Opt-data) to 0xFF9FFFFF, and fill the subsequent data (Opt-data) with 0 to meet the minimum 64-byte Ethernet data frame. After the package is completed, send it to FPGA4 through the Ethernet interface, and perform step 8.

Step 8. After FPGA4 receives the communication protocol data packet sent by the FPGA upgrade software through the Ethernet interface, the communication protocol data packet is sent to the upgrade module built in FPGA4. The upgrade module analyzes the erase command in the communication protocol data packet, and sends the The erase command is sent to the built-in timing control module of FPGA4, and the timing control module generates a corresponding erase sequence to erase the built-in Flash according to the erase command. The functional structure is shown in Figure 3. Then go to step 9.

Step 9. The timing control module actively reads the control status register of the built-in Flash. When the erasing is successful, the corresponding bit of the control status register will be automatically set to 1, otherwise it will be 0. The timing control module judges that the erasure is successful according to the control status register within 5 seconds, then generates an erase success signal and sends it to the upgrade module, otherwise generates an erase failure signal and sends it to the upgrade module, and the upgrade module generates an erase success signal or an erase failure signal Set the communication protocol packet;

The upgrade module sets the communication protocol data packet according to the erase success signal or the erase failure signal, including the following steps:

Set the command type (Opt-cmd) to 0x00 write command, set the effective data length (Opt-len) to 0x0001, set the operation status (Opt-status) to 0x01 if it is an erase success signal, and set the operation if it is an erase failure signal The status (Opt-status) is 0x00, set the address (Opt-Addr) to 0x00000000, set the first four bytes of data (Opt-data) to 0Xffffffe0, and fill the subsequent data (Opt-data) bytes with 0 to meet the minimum 64 Byte Ethernet data frame.

The upgrade module sends the communication protocol data packet to the FPGA upgrade software. The FPGA upgrade software analyzes the erase success signal or the erase failure signal according to the communication protocol data packet. If it is an erase success signal, perform step 10; if it is an erase failure signal Then return to step 5.

Step 10, the FPGA upgrade software issues an unlock command to unlock the Flash application area, and sets the communication protocol data packet according to the unlock command, and sends the communication protocol data packet to FPGA4 through the Ethernet interface.

Setting the communication protocol data packet according to the unlock command includes the following steps:

Set the command type (Opt-cmd) to 0x00 write command, set the effective data length (Opt-len) to 0x0001, set the operation status (Opt-status) to 0x00, set the address (Opt-Addr) to 0x00000001, set the first four The byte data (Opt-data) is 0xFF7FFFFF, and the subsequent data (Opt-data) bytes are filled with 0 to meet the minimum 64-byte Ethernet data frame. After the package is completed, send it to FPGA4 through the Ethernet interface, and go to step 11.

Step 11. After FPGA4 receives the communication protocol data packet sent by the FPGA upgrade software through the Ethernet interface, it sends the communication protocol data packet to the upgrade module built in FPGA4. The upgrade module parses out the unlock command in the communication protocol data packet and unlocks the The command is sent to the built-in timing control module of FPGA4, and the timing control module generates corresponding unlocking timing according to the unlocking command to unlock the built-in Flash. The functional structure is shown in Figure 3. Then go to step 12.

Step 12. The timing control module actively reads the control status register of the built-in Flash. When the unlocking is successful, the corresponding bit of the control status register will be automatically set to 1, otherwise it will be 0. The timing control module judges that the unlocking is successful according to the control status register within 5 seconds, then generates an unlocking success signal and sends it to the upgrade module, otherwise generates an unlocking failure signal and sends it to the upgrade module, and the upgrade module sets the communication protocol data packet according to the unlocking success signal or the unlocking failure signal ;

The upgrade module sets the communication protocol data packet according to the unlocking success signal or the unlocking failure signal, including the following steps:

Set the command type (Opt-cmd) to 0x00 write command, set the effective data length (Opt-len) to 0x0001, set the operation status (Opt-status) to 0x01 for the unlock success signal, and set the operation status (Opt-status) for the unlock failure signal ( Opt-status) is 0x00, set the address (Opt-Addr) to 0x00000000, set the first four bytes of data (Opt-data) to 0Xffffffc0, and fill the subsequent data (Opt-data) bytes with 0 to meet the minimum 64 bytes Ethernet data frame. The upgrade module sends the communication protocol data packet to the FPGA upgrade software, and the FPGA upgrade software analyzes the unlock success signal or the unlock failure signal according to the communication protocol data packet, if it is the unlock success signal, execute step 13, and if it is the erase failure signal, return to step 5.

Step 13, the FPGA upgrade software obtains the maximum 1024 bytes of application image data of the application image each time, and issues a write data command, and sets the communication protocol packet according to the write data command and the maximum 1024 byte application image data,

Setting the communication protocol data packet according to the write data command includes the following steps:

Set the command type (Opt-cmd) to 0x02 to write data, set the effective data length (Opt-len) to 0x00FF, set the operation status (Opt-status) to 0x00, set the address (Opt-Addr) to 0x00008000, and the obtained 1024 Bytes should be filled with mirrored data to data (Opt-data). After the package is completed, it is sent to FPGA4 through the Ethernet interface, and step 14 is performed.

Step 14: After FPGA4 receives the communication protocol data packet sent by the FPGA upgrade software through the Ethernet interface, it sends the communication protocol data packet to the upgrade module built in FPGA4, and the upgrade module parses out the write data command and 1024 words in the communication protocol data packet Section application image data, and send the write data command to the timing control module built in FPGA4, the timing control module generates the corresponding write data timing according to the write data command, and writes 1024 bytes of application mirror data to the built-in Flash through the write data timing The functional structure of the application area is shown in Figure 3. Then go to step 15.

Step 15. The timing control module actively reads the control status register of the built-in Flash. When the data is successfully written, the corresponding bit of the control status register will be automatically set to 1, otherwise it will be 0. The timing control module judges the success of writing data according to the control status register within 5 seconds, then generates a write data success signal and sends it to the upgrade module, otherwise generates a write data failure signal and sends it to the upgrade module, and the upgrade module according to the write data success signal or write data failure signal Set the communication protocol packet;

The upgrade module sets the communication protocol data packet according to the write data success signal or the write data failure signal, including the following steps:

Set the command type (Opt-cmd) to 0x02 to write data, set the effective data length (Opt-len) to 0x0001, set the operation status (Opt-status) to 0x01 if it is a signal of successful writing data, and set the operation if it is a signal of failure to write data The status (Opt-status) is 0x00, set the address (Opt-Addr) to 0x00008000, set the first four bytes of data (Opt-data) to 0xffffffc8, and fill the subsequent data (Opt-data) bytes with 0 to meet the minimum 64 Byte Ethernet data frame. The upgrade module sends the communication protocol data packet to the FPGA upgrade software, and the FPGA upgrade software analyzes the write data success signal or the write data failure signal according to the communication protocol data packet, if it is the write data success signal, then perform step 16, if it is the write data failure signal Then return to step 5.

Step 16. Repeat steps 13-15 until all the application images are written into the application area of the built-in Flash, and then go to step 17 after all writing is completed.

Step 17, the FPGA upgrade software issues a read data command, reads the application area of the built-in Flash, and sets the communication protocol data packet according to the read data command, and sends the communication protocol data packet to FPGA4 through the Ethernet interface.

Setting the communication protocol packet according to the read data command includes the following steps:

Set the command type (Opt-cmd) to 0x03 to read data, set the effective data length (Opt-len) to 0x00FF, set the operation status (Opt-status) to 0x00, set the address (Opt-Addr) to 0x00008000, and set the data (Opt- data) byte is filled with 0 to meet the minimum 64-byte Ethernet data frame. After the package is completed, it is sent to FPGA4 through the Ethernet interface, and step 18 is performed.

Step 18, after FPGA4 receives the communication protocol packet sent by the FPGA upgrade software through the Ethernet interface, the communication protocol packet is sent to the upgrade module built in FPGA4, and the upgrade module parses out the read data command in the communication protocol packet, and sends the The read data command is sent to the built-in timing control module of FPGA4, and the timing control module generates the corresponding read data timing according to the read data command to perform the read data operation of the application image with a set length in the application area of the built-in Flash. The functional structure is shown in Figure 3 . Then go to step 19.

Step 19: The timing control module actively reads the control status register of the built-in Flash. When the data is read successfully, the corresponding bit of the control status register is automatically set to 1, otherwise it is 0. The timing control module judges the success of reading data according to the control status register within 5 seconds, then generates a read data success signal and sends it to the upgrade module, otherwise generates a read data failure signal and sends it to the upgrade module, and the upgrade module according to the read data success signal or read data failure signal Set the communication protocol data packet, and send the communication protocol data packet to the FPGA upgrade software;

The upgrade module sets the communication protocol data packet according to the read data success signal or the read data failure signal, including the following steps:

Set the command type (Opt-cmd) to 0x03 to read data, set the effective data length (Opt-len) to 0x00FF, set the operation status (Opt-status) to 0x01 if it is a read data success signal, and set the operation if it is a read data failure signal The status (Opt-status) is 0x00, the setting address (Opt-Addr) is 0x00008000, and the setting data (Opt-data) is the application image of the set length read. The upgrade module sends the communication protocol data packet to the FPGA upgrade software, and the FPGA upgrade software parses the read data success signal or the read data failure signal according to the communication protocol data packet, if it is the read data success signal, then perform step 20, if it is the read data failure signal Then return to step 5.

Step 20. Repeat steps 17-19 until all the application images stored in the application area of the built-in Flash are read out to the FPGA upgrade software, and then step 21 is executed after all are read out.

Step 21. The FPGA upgrade software compares the read application image with the application image selected in step 3. If they are consistent, go to step 22; otherwise, go to step 5.

Step 22, the FPGA upgrade software issues a lock command, locks the application area of the built-in Flash, and sets the communication protocol data packet according to the lock command, and sends the communication protocol data packet to FPGA4 through the Ethernet interface.

Setting the communication protocol data packet according to the lock command includes the following steps:

Set the command type (Opt-cmd) to 0x00 write command, set the effective data length (Opt-len) to 0x0001, set the operation status (Opt-status) to 0x00, set the address (Opt-Addr) to 0x00000001, and set the data (Opt- The first four bytes of data) are 0xFFFFFFFF, and the subsequent bytes of the data are filled with 0 to meet the minimum 64-byte Ethernet data frame. After the package is completed, it is sent to FPGA4 through the Ethernet interface, and step 23 is performed.

Step 23, after FPGA4 receives the communication protocol data packet sent by the FPGA upgrade software through the Ethernet interface, the communication protocol data packet is sent to the upgrade module built in FPGA4, and the upgrade module parses out the lock command in the communication protocol data packet, and sends the The lock command is sent to the built-in timing control module of FPGA4, and the timing control module generates a corresponding lock sequence according to the lock command to lock the application area of the built-in Flash. The functional structure is shown in Figure 3. Then execute step 24.

Step 24: The timing control module actively reads the control status register of the built-in Flash. When the lock is successful, the corresponding bit of the control status register will be automatically set to 1, otherwise it will be 0. The timing control module judges that the lock is successful according to the control status register within 5 seconds, then generates a lock success signal and sends it to the upgrade module, otherwise generates a lock failure signal and sends it to the upgrade module, and the upgrade module according to the lock success signal or the lock failure signal Set the communication protocol packet;

The upgrade module sets the communication protocol data packet according to the locking success signal or the locking failure signal, including the following steps:

Set the command type (Opt-cmd) to 0x00 write command, set the effective data length (Opt-len) to 0x0001, set the operation status (Opt-status) to 0x01 for the lock success signal, and set the operation for the lock failure signal The status (Opt-status) is 0x00, set the address (Opt-Addr) to 0x00000000, set the first four bytes of data (Opt-data) to 0Xffffffe0, and fill the subsequent data (Opt-data) bytes with 0 to meet the minimum 64 Byte Ethernet data frame. The upgrade module sends the communication protocol data packet to the FPGA upgrade software, and the FPGA upgrade software analyzes the lock success signal or the lock failure signal according to the communication protocol data packet, if it is the lock success signal, then perform step 25, if it is the lock failure signal Then return to step 5.

Step 25, set the toggle switch to a high level, and after the FPGA4 recognizes that the toggle switch is input with a high level, load the application image program. FPGA4 can realize product-level functions after loading the application image stored in the application area.

Step 26, complete the FPGA upgrade.

The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which the present invention belongs can make various modifications or supplements to the described specific embodiments or adopt similar methods to replace them, but they will not deviate from the spirit of the present invention or go beyond the definition of the appended claims range.

Claims (2)

1. a FPAG remote upgrade method with built-in Flash, is characterized in that, comprises the following steps: Step 1. The host computer runs the Quartus software, and the FPGA factory firmware including the upgraded image is generated through the Quartus software; Step 2. Use the Quartus software to download the FPGA factory firmware to the upgrade area of the FPGA's built-in Flash through the JTAG interface and the FPGA downloader; Step 3, use the Quartus software to compile and generate an application image; Step 4. Restart the FPGA, set the toggle switch connected to the FPGA to a low level, and after the FPGA4 recognizes that the toggle switch is input to a low level, the FPGA loads the upgrade image from the upgrade area of the built-in Flash; Step 5. The host computer runs the FPGA upgrade software and loads the application image generated in step 3; Step 6. The FPGA upgrade software communicates with the FPGA through Ethernet to obtain the information of the hardware platform of the FPGA, and judges whether the loaded application image corresponds to the hardware platform of the FPGA according to the information of the hardware platform of the FPGA. If so, execute step 7. Otherwise, go to step 5; Step 7, the FPGA upgrade software issues an erase command and sets the communication protocol data packet according to the erase command, the communication protocol data packet is sent to the FPGA through Ethernet, and step 8 is performed; Step 8. After the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, it sends the communication protocol data packet to the upgrade module built in the FPGA. The upgrade module parses out the erase command in the communication protocol data packet, and The delete command is sent to the timing control module built in the FPGA, and the timing control module generates a corresponding erasing sequence according to the erasing command to erase the built-in Flash; Step 9. The timing control module actively reads the control status register of the built-in Flash. The timing control module judges whether the erasing is successful according to the control status register within the set time. If the erasing is successful, an erasing success signal is generated and sent to the upgrade module. If the erasing is unsuccessful, an erasure failure signal is generated and sent to the upgrade module, and the upgrade module sets the communication protocol data packet according to the erasure success signal or the erasure failure signal and sends the communication protocol data packet to the FPGA upgrade software, and the FPGA upgrade software according to The communication protocol data packet parses out the erasing success signal or the erasing failure signal, if it is the erasing success signal, execute step 10, and if it is the erasing failure signal, return to step 5; Step 10, the FPGA upgrade software issues an unlock command and sets the communication protocol data packet according to the unlock command, and the FPGA upgrade software sends the communication protocol data packet to FPGA through Ethernet; Step 11, after the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, the communication protocol data packet is sent to the upgrade module built in FPGA4, and the upgrade module parses out the unlock command in the communication protocol data packet, and sends the unlock command Send it to the timing control module built in FPGA, and the timing control module will generate corresponding unlock timing according to the unlock command to unlock the built-in Flash; Step 12. The timing control module actively reads the control status register of the built-in Flash. The timing control module judges whether the unlocking is successful according to the control status register within the set time. If the unlocking is successful, it generates an unlocking success signal and sends it to the upgrade module. If successful, an unlock failure signal is generated and sent to the upgrade module. The upgrade module sets the communication protocol data packet according to the unlock success signal or the unlock failure signal and sends the communication protocol data packet to the FPGA upgrade software. The FPGA upgrade software parses the unlock data packet according to the communication protocol data packet. Success signal or unlocking failure signal, if it is unlocking success signal, execute step 13, if it is erasing failure signal, return to step 5; Step 13, the FPGA upgrade software obtains the application image data of the set byte of the application image each time, and issues a write data command, and sets the communication protocol packet according to the write data command and the set byte of the application image data; Step 14. After the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, the communication protocol data packet is sent to the upgrade module built in the FPGA, and the upgrade module parses out the write data command and the setting word in the communication protocol data packet. The application mirror data of the node, and send the write data command to the timing control module built in FPGA, the timing control module generates the corresponding write data timing according to the write data command, and writes the application mirror data of the set byte through the write data timing Go to the application area with built-in Flash; Step 15, the timing control module actively reads the control status register of the built-in Flash, and the timing control module judges whether the data writing is successful according to the control status register within the set time. If the data writing is successful, a data writing success signal is generated and sent to the upgrade module. If the write data is unsuccessful, a write data failure signal is generated and sent to the upgrade module, The upgrade module sets the communication protocol data packet according to the write data success signal or the write data failure signal; the upgrade module sends the communication protocol data packet to the FPGA upgrade software, and the FPGA upgrade software analyzes the write data success signal or the write data failure signal according to the communication protocol data packet , if it is a write data success signal, execute step 16, and if it is a write data failure signal, return to step 5; Step 16. Repeat steps 13-15 until the application image is completely written into the application area of the built-in Flash, and then execute step 17 after all writing is completed; Step 17, the FPGA upgrade software issues a read data command, reads the application area of the built-in Flash, and sets the communication protocol packet according to the read data command, and sends the communication protocol packet to FPGA4 via Ethernet; Step 18. After the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, the communication protocol data packet is sent to the FPGA built-in upgrade module, and the upgrade module parses out the read data command in the communication protocol data packet, and reads The data command is sent to the built-in timing control module of the FPGA, and the timing control module generates the corresponding read data timing according to the read data command to perform the read data operation of the application image with a set length in the application area of the built-in Flash. Step 19, the timing control module actively reads the control status register of the built-in Flash, and the timing control module judges whether the read data is successful according to the control status register within the set time, if the read data is successful, then generates a read data success signal and sends it to the upgrade module, If the data reading is unsuccessful, a signal of failure to read data is generated and sent to the upgrade module, and the upgrade module sets the communication protocol data packet according to the signal of successful data reading or the signal of failure to read data, and sends the communication protocol data packet to the FPGA upgrade software. The communication protocol data packet is analyzed to read the data success signal or the data reading failure signal, if it is the data reading success signal, then perform step 20, and if it is the data reading failure signal, then return to step 5; Step 20. Repeat steps 17-19 until all the application images stored in the application area of the built-in Flash are read out to the FPGA upgrade software; Step 21. The FPGA upgrade software compares the read application image with the application image selected in step 3. If they are consistent, execute step 22; otherwise, execute step 5; Step 22, the FPGA upgrade software issues a locking command and sets the communication protocol data packet according to the locking command, and sends the communication protocol data packet to FPGA through Ethernet; Step 23. After the FPGA receives the communication protocol data packet sent by the FPGA upgrade software via the Ethernet, the communication protocol data packet is sent to the upgrade module built in the FPGA. The upgrade module parses out the lock command in the communication protocol data packet, and adds The lock command is sent to the built-in timing control module of the FPGA, and the timing control module generates a corresponding lock sequence according to the lock command to lock the application area of the built-in Flash; Step 24, the timing control module actively reads the control status register of the built-in Flash, and the timing control module judges whether the locking is successful according to the control status register within the set time. If the locking is successful, a locking success signal is generated and sent to the upgrade module. If the lock is unsuccessful, a lock failure signal is generated and sent to the upgrade module. The upgrade module sets the communication protocol data packet according to the lock success signal or the lock failure signal and sends it to the FPGA upgrade software. The FPGA upgrade software analyzes the communication protocol data packet. Locking success signal or locking failure signal, if it is a locking success signal, execute step 25, and if it is a locking failure signal, return to step 5; Step 25. Set the toggle switch to a high level, and after the FPGA recognizes that the toggle switch has input a high level, load the application image. 2. the FPAG remote upgrade method of a kind of built-in Flash according to claim 1, is characterized in that, the first byte of described communication protocol packet represents command type, and command type is write command or read command or write data or read data; The second byte and the third byte represent the high and low eight bits of the valid data length; The fourth byte represents the operation status; The fifth byte to the eighth byte represent the address. If the command type is write command or read command, the address is the control status register address of the built-in Flash; if the command type is write data or read data, the address is the built-in Flash Flash storage address; data starting from the ninth byte; The communication protocol data packet is at least 64 bytes.