CN207199623U - A kind of two-way super-low capacity ESD protection chip structure - Google Patents
A kind of two-way super-low capacity ESD protection chip structure Download PDFInfo
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- CN207199623U CN207199623U CN201720929918.3U CN201720929918U CN207199623U CN 207199623 U CN207199623 U CN 207199623U CN 201720929918 U CN201720929918 U CN 201720929918U CN 207199623 U CN207199623 U CN 207199623U
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Abstract
The utility model discloses a kind of two-way super-low capacity ESD protection chip structure, structure includes：Avalanche diode D1 and commutation diode D2, D3, D4, D5；D1 structure：Comprising SN is included inside N well, N well inside substrate, SP is included inside SN, is SiO above monocrystalline silicon2Layer, SiO2Layer segment is opened, SiO2Layer is above front metal, and front metal partially opens, and is passivation layer above front metal；Wherein, D1 SP and D3 and D5 SP are connected, and D1 SN and D2 and D4 SN are connected；D2, D3, D4, D5 structure：Inside substrate comprising inside N well, N well comprising SN and SP, SN and SP into pectinate texture, be SiO above monocrystalline silicon2Layer, SiO2Layer segment is opened, SiO2Layer is above front metal, and front metal partially opens, and is passivation layer above front metal；Wherein, D3 and D5 SP and D1 SP are connected, and D2 and D4 SN and D1 SN are connected, and D2 SP and D3 SN are connected, and D4 SP and D5 SN are connected.The utility model is applied to the ESD protection of high speed interface.
Description
Technical field
The utility model belongs to a kind of two-way super-low capacity ESD protection chip structure, and the ESD protection chip of this structure is applied to
The ESD protection of high speed interface.
Background technology
With the blast of information age data volume, various high-speed interfaces arise at the historic moment, at present the USB3.0 of main flow,
HDMI2.0, and following faster high-speed interfaces of USB4.0, HDMI3.0 etc., to meet the biography of various staggering amount data
Defeated, this, which is resulted in, proposes higher requirement to the ESD protection of high-speed interface, protects the capacitance requirements of chip lower, encapsulates chi
Very little to require smaller, Ipp requires bigger, but chip size and Ipp are proportional relation forever, are added on the market with two-layer epitaxial at present
The super-low capacity chip capacity value of groove structure is in 0.5pF or so.
Utility model content
In order to solve above-mentioned the deficiencies in the prior art, there is provided a kind of two-way super-low capacity ESD protection chip structure, its structure
Including：One avalanche diode D1 and 4 commutation diodes D2, D3, D4, D5.
A, avalanche diode D1 structure includes：N-well is included inside substrate, SN is included inside N-well, is wrapped inside SN
It is SiO2 layers containing SP, above monocrystalline silicon, SiO2 layer segments are opened, and are front metals above SiO2 layers, and front metal partially opens,
It is passivation layer above front metal, wherein, avalanche diode D1 SP is connected with commutation diode D3 and D5 SP, the pole of snowslide two
Pipe D1 SN is connected with commutation diode D2 and D4 SN.
B, commutation diode D2, D3, D4, D5 structure includes：N-well is included inside substrate, SN is included inside N-well
And SP, SN and SP are into pectinate texture, are SiO2 layers above monocrystalline silicon, SiO2 layer segments are opened, and are front metals above SiO2 layers,
Front metal partially opens, and is passivation layer above front metal；Wherein, commutation diode D3 and D5 SP and avalanche diode D1
SP be connected, commutation diode D2 and D4 SN are connected with avalanche diode D1 SN, and D2 SP and D3 SN are connected, D4 SP
It is connected with D5 SN.
Beneficial effect：The single crystalline substrate of this utility model structure is that p-type superelevation hinders 1000 Ω .cm, can reduce junction capacity
To below 0.3pF, 14 photoetching of old structure, this utility model has only used 7 photoetching, has substantially reduced chip manufacturing cost,
Two electrodes are drawn from front, are particularly suitable for flip-chip packaged, and chip need not be thinned to below 150um, need to be only thinned to
200um, fragment rate is reduced, improve yields, eliminated extension and the structure of this complicated difficult control of groove, eliminate the back side
Metal structure, it is often more important that this utility model structure improves the effective dimensions of chip, and same encapsulation Ipp is bigger.
Brief description of the drawings
Fig. 1 is the equivalent circuit diagram of the two-way super-low capacity ESD protection chip of this structure；
Fig. 2 is the metal line and electrode top view of the two-way super-low capacity ESD protection chip of this structure；
Fig. 3 is the avalanche diode sectional view of the two-way super-low capacity ESD protection chip of this structure；
Fig. 4 is the commutation diode sectional view of the two-way super-low capacity ESD protection chip of this structure.
Number explanation：
101：Avalanche diode D1
102：Commutation diode D2
103：Commutation diode D3
104：Commutation diode D4
105：Commutation diode D5
106：I/O electrodes pin1
107：I/O electrodes pin2
201：Avalanche diode D1
202：Commutation diode D2
203：Commutation diode D3
204：Commutation diode D4
205：Commutation diode D5
206：I/O electrodes pin1
207：I/O electrodes pin2
301：P-type High resistivity substrate, resistivity are more than 1000 Ω .cm
302：N-well, function as the PN junction of rectifying tube, and isolation snowslide pipe and rectifying tube
303：SN, effect are to form Ohmic contact with metal, and as the PN junction of snowslide pipe
304：SP, effect are to form Ohmic contact with metal, and as snowslide pipe and the PN junction of rectifying tube
305：SiO2Oxide layer, for isolating metal layer and monocrystalline silicon
306：Metal line, is used as the wiring between diode and the electrode of chip, is used as electrode exposed to outer part
307：Passivation layer, effect is to improve device reliability, usually using SiO2Layer+SiN layer
401：P-type High resistivity substrate, resistivity are more than 1000 Ω .cm
402：N-well, function as the PN junction of rectifying tube, and isolation snowslide pipe and rectifying tube
403：SN, effect are to form Ohmic contact with metal, and as the PN junction of snowslide pipe
404：SP, effect are to form Ohmic contact with metal, and as snowslide pipe and the PN junction of rectifying tube
405：SiO2Oxide layer, for isolating metal layer and monocrystalline silicon
406：Metal line, is used as the wiring between diode and the electrode of chip, is used as electrode exposed to outer part
407：Passivation layer, effect is to improve device reliability, usually using SiO2Layer+SiN layer.
Embodiment
1. the preparation of substrate 301, substrate selects high resistant monocrystalline polished silicon slice, the Ω .cm of resistivity 1000, mark, cleaning, gets rid of
It is dry.
2.N-well 302 is manufactured, and oxidation, photoetching, is etched, is removed photoresist, aoxidizing, then by injection technology doped N-type impurity,
It is usually injected into P element, low dosage, high-energy, high annealing.
3. SN 303 is manufactured, photoetching, etch, remove photoresist, aoxidizing, ion implanting heavy dose N-type impurity, being usually injected into P members
Element, dosage control is critically important, i.e., to accomplish Ohmic contact, also to accomplish suitable snowslide pipe breakdown voltage.
4. SP 304 is manufactured, photoetching, etch, remove photoresist, aoxidizing, ion implanting p type impurity, being usually injected into B element, dosage
Control critically important, i.e., to accomplish Ohmic contact, also to accomplish suitable snowslide pipe breakdown voltage.
5.SN303 the high annealing with SP304.
6. fairlead manufactures, SiO2Oxide layer 305 deposits, photoetching, SiO2Etching.
7. metal line 306 manufactures, metal level deposit, photoetching, metal level etching, remove photoresist, be used as I/O electrodes and diode
Between wiring.
8. passivation layer 307 manufactures, SiO2Deposit, SiN deposits, photoetching, SiN etchings, SiO2Etching, removes photoresist.
9. thinning back side, thinning back side is carried out according to requirement of the encapsulation to chip thickness.
By embodiments described above illustrating the utility model, while it can also realize that this practicality is new using other embodiments
Type.The utility model is not limited to above-mentioned specific embodiment, therefore the utility model has scope restriction.
Claims (1)
1. a kind of two-way super-low capacity ESD protection chip structure, its structure include：One avalanche diode D1 and 4 rectifications two
Pole pipe D2, D3, D4, D5；
The structure of the avalanche diode D1 includes：N-well is included inside substrate, SN layers, SN layers the inside are included inside N-well
It is SiO above monocrystalline silicon comprising SP layers2Layer, SiO2Layer segment is opened, SiO2Layer is above front metal, and front metal part is beaten
Open, be passivation layer above front metal；Wherein, avalanche diode D1 SP layers are connected with commutation diode D3 and D5 SP layers,
Avalanche diode D1 SN layers are connected with commutation diode D2 and D4 SN layers；
Described commutation diode D2, D3, D4, D5 structure include：N-well is included inside substrate, SN layers are included inside N-well
With SP layers, SN layers and SP layers are SiO above monocrystalline silicon into pectinate texture2Layer, SiO2Layer segment is opened, SiO2Layer is front above
Metal, front metal partially open, and are passivation layer above front metal；Wherein, commutation diode D3 and D5 SP layers and snowslide
Diode D1 SP layers are connected, and commutation diode D2 and D4 SN layers are connected with avalanche diode D1 SN layers, D2 SP layers with
D3 SN layers are connected, and D4 SP layers are connected with D5 SN layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720929918.3U CN207199623U (en) | 2017-07-28 | 2017-07-28 | A kind of two-way super-low capacity ESD protection chip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720929918.3U CN207199623U (en) | 2017-07-28 | 2017-07-28 | A kind of two-way super-low capacity ESD protection chip structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207199623U true CN207199623U (en) | 2018-04-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720929918.3U Active CN207199623U (en) | 2017-07-28 | 2017-07-28 | A kind of two-way super-low capacity ESD protection chip structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207199623U (en) |
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2017
- 2017-07-28 CN CN201720929918.3U patent/CN207199623U/en active Active
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