CN206931591U - A kind of semiconductor chip package - Google Patents
A kind of semiconductor chip package Download PDFInfo
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- CN206931591U CN206931591U CN201720737949.9U CN201720737949U CN206931591U CN 206931591 U CN206931591 U CN 206931591U CN 201720737949 U CN201720737949 U CN 201720737949U CN 206931591 U CN206931591 U CN 206931591U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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Abstract
The utility model discloses a kind of semiconductor chip package, including substrate, chip and encapsulated layer.Substrate includes heat dissipating layer, insulating barrier and conductive layer.The first insulating barrier and the first conductive layer are set gradually in the one side of heat dissipating layer, the second insulating barrier and the second conductive layer are set gradually on the another side of heat dissipating layer, the first conductive layer is separated to form multiple join domains isolated from one another.Chip is fixed on the first conductive layer surface, and the circuit exit of chip connects with corresponding join domain, and the join domain being connected with circuit exit is provided through the guide hole of heat dissipating layer, and is electrically connected by guide hole with the second conductive layer.Encapsulated layer and the common coating chip of substrate.The back side of the substrate of semiconductor package is directly exposed, can improve the heat dispersion of semiconductor package.Guide hole can form after chip and the connection of the second conductive layer leadless packages, be mounted using SMT mode, improve integrated level and the convenience of assembling.
Description
Technical field
It the utility model is related to the technical field of semiconductor, more particularly to a kind of semiconductor chip package.
Background technology
Semiconductor chip is the semiconductor by that can realize certain function made of etch, wiring etc. on semiconductor sheet material
Device.Semiconductor chip generally requires the encapsulating structure for being packaged into certain standard size, is cooperatively formed with other electronic components
Control circuit or drive circuit.In the prior art, as shown in figure 1, semiconductor chip package includes the ＇ of lead frame 1, chip
The 2 ＇ and ＇ of encapsulated layer 3.The ＇ of chip 2 is typically welded on the ＇ of lead frame 1, by electrical connector (such as bonding wire, weldering bridge etc.) by chip
2 ＇ circuit exit is connected with the ＇ of lead frame 1 pin, recycles the materials such as epoxy resin from positive and negative the two of the ＇ of lead frame 1
Face coats the ＇ of lead frame 1 and the ＇ of chip 2, forms the ＇ of encapsulated layer 3, the ＇ of the lead frame 1 pin protrusion ＇ of encapsulated layer 3, for it is outer
Portion's circuit connection so that the ＇ of chip 2 circuit exit is had access in external circuit.
The heat dispersion of epoxy resin is not fine, and existing encapsulating structure in the ＇ of chip 2 tow sides due to wrapping
Epoxy resin has been covered, has influenceed the ＇ of chip 2 radiating.Especially to the ＇ of high-power chip 2, such as the core that the caloric value such as driving chip is big
The ＇ of piece 2 influences very big, and heating is rapid during work, is easily damaged the ＇ of chip 2.
Utility model content
The purpose of this utility model is to propose a kind of semiconductor chip package have good heat dispersion, and
Leadless packages can be realized.
To use following technical scheme up to this purpose, the utility model：
A kind of semiconductor chip package, including substrate, chip and encapsulated layer；
Substrate includes：
Heat dissipating layer, for forming agent structure and the radiating of substrate；
Insulating barrier, including the first insulating barrier and the second insulating barrier, the first insulating barrier are arranged at the front of heat dissipating layer, and second is exhausted
Edge layer is arranged at the reverse side of heat dissipating layer；With
Conductive layer, including the first conductive layer and the second conductive layer, the first conductive layer are arranged at the first surface of insulating layer, and second
Conductive layer is arranged at the second surface of insulating layer, and the first conductive layer, which is separated to form, multiple has join domain isolated from one another；
Chip is fixed on the first conductive layer surface, and the circuit exit of chip connects with corresponding join domain, with circuit
The join domain of exit connection is provided through the guide hole of heat dissipating layer, and is electrically connected by guide hole with the second conductive layer；
Encapsulated layer and the common coating chip of substrate.
Further, the inwall of guide hole is provided with hole inner insulating layer, is provided with hole inner conducting layer on the inner insulating layer of hole, in hole
Conductive layer is connected with the first conductive layer and the second conductive layer respectively.
Further, heat dissipating layer is metallic plate.
Further, heat dissipating layer is made up of graphene.
Further, chip is positive cartridge chip, and the circuit exit of positive cartridge chip is connected with join domain by electrical connector
Connect, electrical connector is packaged layer cladding.
Further, chip is flip-chip, and the end of the circuit exit of flip-chip is consolidated with corresponding join domain
Fixed and electrical connection.
Further, the thickness of the first conductive layer is 0.02-0.2mm, and join domain forms corresponding connection circuit.
Further, chip includes control chip and power chip；
Control chip is flip-chip, and the end of circuit exit is fixed and electrically connected with corresponding join domain；
Power chip is positive cartridge chip, and circuit exit is connected with join domain by electrical connector.
Further, encapsulated layer coats the first conductive layer and chip jointly with heat dissipating layer or encapsulated layer and the first insulating barrier.
Further, second conductive layer is led formed with corresponding connection circuit, the connection circuit with described first
The join domain of electric layer is connected by the guide hole.
Beneficial effect：The utility model provides a kind of semiconductor chip package, including substrate, chip and encapsulation
Layer.Substrate includes heat dissipating layer, insulating barrier and conductive layer.Heat dissipating layer is used for agent structure and the radiating for forming substrate.Insulating barrier bag
The first insulating barrier and the second insulating barrier are included, the first insulating barrier is arranged at the front of heat dissipating layer, and the second insulating barrier is arranged at heat dissipating layer
Reverse side.Conductive layer includes the first conductive layer and the second conductive layer, and the first conductive layer is arranged at the first surface of insulating layer, and second leads
Electric layer is arranged at the second surface of insulating layer, and the first conductive layer, which is separated to form, multiple has join domain isolated from one another.Chip is consolidated
Due to the first conductive layer surface, the circuit exit of chip connects with corresponding join domain, the company being connected with circuit exit
The guide hole that region is provided through heat dissipating layer is connect, and is electrically connected by guide hole with the second conductive layer.Encapsulated layer wraps jointly with substrate
Cover chip.After chip is arranged on substrate by semiconductor package, using substrate and encapsulated layer coating chip, encapsulated layer only needs
Will be from the side coating chip of the first conductive layer, it is not necessary to direct at the reverse side coating chip of substrate, the back side of substrate again
It is exposed, the area of dissipation of substrate can be greatly improved, improves the heat dispersion of semiconductor package.In addition, guide hole is by core
After piece and the connection of the second conductive layer, it can directly pass through the second conductive layer and outside circuit communication.Semiconductor package is not
Exposed pin is needed, forms leadless packages, can be mounted in a manner of directly using SMT, improve integrated level and the convenience of assembling
Property.
Brief description of the drawings
Fig. 1 is the structural representation of the semiconductor chip package of prior art.
Fig. 2 is the structural representation of semiconductor chip package of the present utility model.
1- substrates, 11- heat dissipating layers, the insulating barriers of 121- first, the insulating barriers of 122- second, 123- holes inner insulating layer, 131-
One conductive layer, the conductive layers of 132- second, 133- holes inner conducting layer, 14- guide holes, 2- chips, 3- encapsulated layers, 4- electrical connectors；
1 ＇-lead frame, 2 ＇-chip, 3 ＇-encapsulated layer.
Embodiment
It is clearer for the technical scheme and the technique effect that reaches that make technical problem that the utility model solves, use,
Further illustrate the technical solution of the utility model below in conjunction with the accompanying drawings and by embodiment.
Embodiment 1
As shown in Fig. 2 a kind of semiconductor chip package is present embodiments provided, including substrate 1, chip 2 and encapsulation
Layer 3.Substrate 1 includes heat dissipating layer 11, insulating barrier and conductive layer.Heat dissipating layer 11 is used for agent structure and the radiating for forming substrate 1.Dissipate
Thermosphere 11 is generally platy structure, metallic plate, such as aluminium sheet, iron plate etc. can be fabricated to metal, comparison is simple, structure
Intensity and heat dispersion are good, and aluminium sheet can also have preferable stainless property, and lighter in weight.Heat dissipating layer 11 can also use stone
Black alkene makes platy structure, and compared with metallic plate, platy structure made of graphene can thinner, intensity be bigger, heat dispersion
More preferably.
Insulating barrier includes the first insulating barrier 121 and the second insulating barrier 122, and the first insulating barrier 121 is arranged at heat dissipating layer 11
Front, the second insulating barrier 122 are arranged at the reverse side of heat dissipating layer 11., can be by heat dissipating layer 11 and other parts by insulating barrier
Isolation, avoid miscellaneous part short-circuit.Insulating barrier can be containing heat stable resin, curing agent and the curable resin of inorganic filler group
The solidfied material of compound, takes into account heat dispersion and insulating properties.Heat stable resin can be epoxy resin, organic siliconresin, phenolic aldehyde tree
Fat, imide resin etc., inorganic filler, the oxide ceramics such as aluminum oxide, silica, magnesia can be used, or
It is nitride ceramics such as aluminium nitride, silicon nitride, boron nitride, carbide ceramics etc.., can be with hardening resin composition
As needed using silane coupling agent, metatitanic acid lipid coupling agent, stabilizer, curing accelerator etc..
Conductive layer includes the first conductive layer 131 and the second conductive layer 132, and the first conductive layer 131 is arranged at the first insulating barrier
121 surfaces, the second conductive layer 132 are arranged at the surface of the second insulating barrier 122, and the first conductive layer 131 and the second conductive layer 132 are distinguished
By corresponding insulator separation, isolate with heat dissipating layer 11, avoid short cut with each other.First conductive layer 131, which is separated to form, multiple to be had
Join domain isolated from one another, to form connection circuit.Conductive layer can be pasted by metal foil to be formed on the insulating layer, can also
Formed by other structures.
Chip 2 is fixed on the surface of the first conductive layer 131, for example is fixed by modes such as welding.The circuit exit of chip 2
Connected with 131 corresponding join domain of the first conductive layer, the join domain being connected with circuit exit is provided through heat dissipating layer
11 guide hole 14, and electrically connected by guide hole 14 with the second conductive layer 132.The circuit exit of chip 2 is the inside electricity of chip 2
The port that road is connected with the circuit outside chip 2, after circuit exit is connected with the first conductive layer 131, recycle guide hole 14
Second conductive layer 132 is connected with the first conductive layer 131, chip 2 can be connected with the second conductive layer 132.
Encapsulated layer 3 can be the encapsulating materials such as epoxy resin, encapsulated layer 3 and the common coating chip 2 of substrate 1.
The semiconductor package of the present embodiment can be first in heat dissipating layer 11 (such as metallic plate or graphene board)
Obverse and reverse is respectively coated the slurry of insulating barrier, or using the mode of silk-screen printing, corresponding first insulating barrier 121 is set
With the second insulating barrier 131, after being heated to semi-cured state, will can be pasted onto accordingly absolutely for forming the metal foil of conductive layer
In edge layer, the first conductive layer 131 and the second conductive layer 132 are formed, reheating is fully cured.Afterwards can be in the area that needs drill
Domain drills, and forms guide hole 14, and the first conductive layer 131 is connected with the second conductive layer 132.
Specifically, in the present embodiment, the insulating barrier 121 of encapsulated layer 3 and first coats the first conductive layer 131 and chip jointly
2.Avoid the conductive layer 131 of chip 2 and first exposed, short circuit occur and live the failure such as be corroded.In addition it is also possible to it is encapsulated layer 3
With heat dissipating layer 11 the first conductive layer 131 of cladding and chip 2, and the first insulating barrier 121 is also coated jointly, complete envelope is formed
Assembling structure.
The semiconductor package of the present embodiment, after chip 2 is set on substrate 1, wrapped using substrate 1 and encapsulated layer 3
Cover chip 2,3 side coating chips 2 needed from the first conductive layer 131 of encapsulated layer, it is not necessary to again in the reverse side of substrate 1
Coating chip 2, the back side of substrate 1 is directly exposed, can greatly improve the area of dissipation of substrate 1, improves semiconductor packages knot
The heat dispersion of structure.In addition, after guide hole 14 connects chip 2 with the second conductive layer 132, it can directly pass through the second conductive layer
132 with outside circuit communication.Semiconductor package does not need exposed pin, forms leadless packages, can directly use
The mode of surface mounting technology (Surface Mounted Technology, SMT) mounts, and improves integrated level and the convenience of assembling
Property.
For the ease of being connected with external circuit, the second conductive layer 132 connects circuit and the formed with corresponding connection circuit
The join domain of one conductive layer 131 is connected by guide hole 14.The connection circuit that second conductive layer 132 is set is also beneficial to semiconductor
Encapsulating structure is mounted using SMT modes.
In the present embodiment, the inwall of guide hole 14 is provided with hole inner insulating layer 123, is provided with hole inner insulating layer 123 in hole
Conductive layer 133, hole inner conducting layer 133 are connected with the first conductive layer 131 and the second conductive layer 132 respectively.Hole inner insulating layer 123 is used
In avoiding hole inner conducting layer 131 from being electrically connected with heat dissipating layer 11, cause short circuit between each guide hole 14.Specific forming method can be with
With reference to the first above-mentioned insulating barrier 121, the second insulating barrier 122, the first conductive layer 131, the second conductive layer 132 manufacturing process into
Type.
As shown in Fig. 2 for the semiconductor chip package of the present embodiment, chip 2 is positive cartridge chip, formal dress
The circuit exit of chip is connected with join domain by electrical connector 4, and electrical connector 4 is packaged layer 3 and coated.Electrical connector 4
Can be bonding wire (such as copper cash etc.) or bridgeware etc., such a attachment structure technology maturation is reliable.Pass through electrical connector
4 are connected circuit exit with join domain, and then are connected with the second conductive layer 132.
Embodiment 2
On the basis of embodiment 1, as different from Example 1, chip 2 is flip-chip, and the circuit of flip-chip draws
The end for going out end is fixed and electrically connected with corresponding join domain.Corresponding join domain, shape are set on the first conductive layer 131
Into after corresponding circuit, the circuit exit of flip-chip can be connected directly with corresponding join domain, it is not necessary to use electricity
Connector 4 connects, and shortens signal transmission path, it is possible to reduce interference and loss of the signal in transmittance process, improves letter
Number fidelity effect.Such a semiconductor chip package can further simplify encapsulating structure, reduce the height of encapsulated layer 3,
Improve heat dispersion.
In order to improve the integrated level of semiconductor die package, in the present embodiment, chip 2 includes flip-chip and formal dress
Chip, flip-chip can be control chip, and positive cartridge chip can be including power chip etc., and control chip is using flip-chip
Mode, the fidelity performance of the instruction of control chip and efficient transitivity can be improved, better controls over power chip.In order to control
Cost, power chip are connected by the way of formal dress.
The caloric value of power chip is bigger, in the prior art, when power chip encapsulates jointly with control chip, due to
Lead frame is integrally formed, and thickness is consistent, and in order to ensure the radiating of power chip, the thickness of lead frame needs to reach
0.5mm, the line width and line-spacing of the connection line formed after processing on lead frame are typically not less than the thickness of lead frame, because
This, the wire frame and line-spacing of the ＇ of lead frame 1 connection line will not be less than 0.5mm.Cause to cause control core on lead frame
Piece can only also use the form of formal dress, influence the hi-fi of the signal of control chip.The size of chip in itself is smaller, chip
On circuit exit directly can not be connected with the connection line on lead frame, can only use electrical connector (such as bonding wire, weldering
Bridge etc.) connection line that size is smaller, arrangement is more larger with size than the circuit exit of comparatively dense, more sparse compared with arrangement is connected
Connect.
In the present embodiment, the heat of power chip is absorbed by heat dissipating layer 11 and outwards distributed, the first conductive layer 131
Thickness can be reduced to 0.1mm or so, can form corresponding connection circuit, meet the requirement of control chip upside-down mounting connection, carry
The hi-fi of high RST.
In order to preferably coordinate with flip-chip, the thickness of the first conductive layer 131 could be arranged to 0.02-0.2mm.Herein
Under thickness, the first conductive layer 131 has good electric conductivity, and join domain can be set to be formed better and connected accordingly
Connect circuit.The first conductive layer 131 than it is relatively thin when, the distance spaced apart of join domain will not be less than the thickness of join domain in itself
Degree, if the thickness of the first conductive layer 131 is excessive, the width of the spacing and join domain of join domain in itself can also increase,
It will be unable to directly be formed connection circuit accordingly to be connected with flip-chip.
Embodiment 3
On the basis of embodiment 1 and embodiment 2, in this implementation, chip 2 includes control chip and power chip.Wherein,
Control chip is flip-chip, and the end of circuit exit is fixed and electrically connected with corresponding join domain.Power chip is just
Cartridge chip, circuit exit are connected with join domain by electrical connector 4.
The semiconductor package of the present embodiment utilizes two kinds of chips, and common encapsulation forms overall package structure, Ke Yijian
The advantages of caring for two kinds of chips.
Above content is only preferred embodiment of the present utility model, for one of ordinary skill in the art, according to this reality
With new thought, there will be changes, this specification content should not be construed as in specific embodiments and applications
To limitation of the present utility model.
Claims (10)
1. a kind of semiconductor chip package, it is characterised in that including substrate (1), chip (2) and encapsulated layer (3)；
The substrate (1) includes：
Heat dissipating layer (11), for forming agent structure and the radiating of the substrate (1)；
Insulating barrier, including the first insulating barrier (121) and the second insulating barrier (122), first insulating barrier (121) are arranged at described
The front of heat dissipating layer (11), second insulating barrier (122) are arranged at the reverse side of the heat dissipating layer (11)；With
Conductive layer, including the first conductive layer (131) and the second conductive layer (132), first conductive layer (131) are arranged at described
First insulating barrier (121) surface, second conductive layer (132) are arranged at the second insulating barrier (122) surface, and described first
Conductive layer (131) is separated to form multiple join domains isolated from one another；
The chip (2) is fixed on the first conductive layer (131) surface, the circuit exit of the chip (2) with it is corresponding
Join domain connects, and the join domain being connected with circuit exit is provided through the guide hole (14) of the heat dissipating layer (11), and
Electrically connected by the guide hole (14) with the second conductive layer (132)；
The encapsulated layer (3) coats the chip (2) jointly with the substrate (1).
2. semiconductor chip package as claimed in claim 1, it is characterised in that the inwall of the guide hole (14) is provided with
Hole inner insulating layer (123), hole inner conducting layer (133), the hole inner conducting layer are provided with the hole inner insulating layer (123)
(133) it is connected respectively with first conductive layer (131) and second conductive layer (132).
3. semiconductor chip package as claimed in claim 1, it is characterised in that the heat dissipating layer (11) is metallic plate.
4. semiconductor chip package as claimed in claim 1, it is characterised in that the heat dissipating layer (11) is by graphene system
Into.
5. the semiconductor chip package as described in claim any one of 1-4, it is characterised in that the chip (2) is just
Cartridge chip, the circuit exit of the positive cartridge chip are connected with the join domain by electrical connector (4), the electrical connector
(4) coated by the encapsulated layer (3).
6. the semiconductor chip package as described in claim any one of 1-4, it is characterised in that the chip (2) is
Cartridge chip, the end of the circuit exit of the flip-chip are fixed and electrically connected with corresponding join domain.
7. semiconductor chip package as claimed in claim 6, it is characterised in that the thickness of first conductive layer (131)
Spend and form corresponding connection circuit for 0.02-0.2mm, the join domain.
8. the semiconductor chip package as described in claim any one of 1-4, it is characterised in that the chip (2) includes
Control chip and power chip；
The control chip is flip-chip, and the end of circuit exit is fixed and electrically connected with corresponding join domain；
The power chip is positive cartridge chip, and circuit exit is connected with the join domain by electrical connector (4).
9. the semiconductor chip package as described in claim any one of 1-4, it is characterised in that encapsulated layer (3) and radiating
Layer (11) or encapsulated layer (3) coat the first conductive layer (131) and chip (2) jointly with the first insulating barrier (121).
10. the semiconductor chip package as described in claim any one of 1-4, it is characterised in that second conductive layer
(132) formed with corresponding connection circuit, the join domain of the connection circuit and first conductive layer (131) passes through described
Guide hole (14) connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720737949.9U CN206931591U (en) | 2017-06-23 | 2017-06-23 | A kind of semiconductor chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720737949.9U CN206931591U (en) | 2017-06-23 | 2017-06-23 | A kind of semiconductor chip package |
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| Publication Number | Publication Date |
|---|---|
| CN206931591U true CN206931591U (en) | 2018-01-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720737949.9U Active CN206931591U (en) | 2017-06-23 | 2017-06-23 | A kind of semiconductor chip package |
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| Country | Link |
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| CN (1) | CN206931591U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473944A (en) * | 2018-05-09 | 2019-11-19 | 深圳市聚飞光电股份有限公司 | Multipurpose LED support and LED |
| WO2022127531A1 (en) * | 2020-12-14 | 2022-06-23 | 青岛歌尔智能传感器有限公司 | Heat-dissipation packaging structure |
-
2017
- 2017-06-23 CN CN201720737949.9U patent/CN206931591U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473944A (en) * | 2018-05-09 | 2019-11-19 | 深圳市聚飞光电股份有限公司 | Multipurpose LED support and LED |
| WO2022127531A1 (en) * | 2020-12-14 | 2022-06-23 | 青岛歌尔智能传感器有限公司 | Heat-dissipation packaging structure |
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