CN206921816U - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN206921816U CN206921816U CN201720901359.5U CN201720901359U CN206921816U CN 206921816 U CN206921816 U CN 206921816U CN 201720901359 U CN201720901359 U CN 201720901359U CN 206921816 U CN206921816 U CN 206921816U
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- semiconductor structure
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Abstract
The utility model discloses a kind of semiconductor structure.Semiconductor structure provided by the utility model, including：Front-end architecture, the front-end architecture have front end mark；Dielectric layer on the front-end architecture；Through hole in the dielectric layer, the through hole expose the front end mark.Thus front end mark is exposed to thick dielectric layer, realize that normal photolithography aligns, eliminating thick dielectric layer can not alignment issues, improve that the branch mode of existing multiexposure, multiple exposure brings to inclined problem, and double-sided exposure is evaded, effectively prevent the scraping to silicon chip from scratching, it is ensured that alignment quality, to be advantageous to the alignment of subsequent film.
Description
Technical field
Technical field of semiconductors is the utility model is related to, more particularly to a kind of semiconductor structure.
Background technology
In current IC productions, it is frequently encountered needs and meets product requirement using thick dielectric layer.Thick dielectric layer pair
There is very fatal influence in photo-etching mark, thickness is thicker, and the step difference that photo-etching mark is formed is smaller, can not realize photoetching just
Often contraposition.
Fig. 1-Fig. 3 is refer to, shows a kind of dielectric layer alignment method.Comprise the following steps：
As shown in figure 1, two symmetrical register guides are reserved to the very high exposure sources of inclined precision in the application of the front of silicon chip 12
Note 3；
As shown in Fig. 2 back-exposure is carried out, and pass through deep trouth using the alignment mark 3 in front 2 by sided exposure machine
The method of etching, the aid mark 5 that overleaf 4 reserved sided exposure machines use；
As shown in figure 3, carrying out positive 2 graph exposures using the aid mark 5 at the back side 4, thick dielectric layer exposure is realized,
The contraposition of dielectric layer is completed from there through the superposition of multilayer lithography layer.
Because double-sided exposure board is to energy power restriction (to partially minimum control pole running water at 1.5 μm) partially, can not meet
What present product more became more meticulous asks persisting in.
In addition, being also easy to produce scuffing to silicon chip using sided exposure machine, easily cause and scrap.
Then, how to improve drawbacks described above, turn into those skilled in the art's urgent problem to be solved.
Utility model content
The purpose of this utility model is to provide a kind of semiconductor structure, improves thick dielectric layer alignment issues, and reduce silicon
Piece is damaged.
In order to solve the above technical problems, the utility model provides a kind of semiconductor structure, including：
Front-end architecture, the front-end architecture have front end mark；
Dielectric layer on the front-end architecture；
Through hole in the dielectric layer, the through hole expose the front end mark.
Optionally, it is more than or equal to 20 μm for described semiconductor structure, the thickness of the dielectric layer.
Optionally, for described semiconductor structure, the front-end architecture is substrate, epitaxial layer, silicon oxide layer, silicon nitride
One kind in layer, carbon-coating or metal level.
Optionally, for described semiconductor structure, the dielectric layer is epitaxial layer, silicon oxide layer, silicon nitride layer, carbon-coating
Or it is different from the another kind of the front-end architecture in metal level.
Optionally, for described semiconductor structure, the through hole is identical with the quantity that the front end marks and one a pair
Should.
Optionally, for described semiconductor structure, the through hole and the front end marker graphic form fit.
Optionally, rectangle is shaped as described semiconductor structure, the through hole, the front end mark has outside one
Rectangle is connect, the through hole is overlapping with the boundary rectangle center and surrounds the boundary rectangle.
Optionally, it is D, wherein D=D0+ for described semiconductor structure, each side of through hole to the centre distance
C, D0 be the boundary rectangle side arrive the center distance, C be one expression distance constant.
Optionally, for described semiconductor structure, C≤50 μm.
Compared with prior art, a kind of semiconductor structure provided by the utility model, including front-end architecture, the front end knot
Structure has front end mark；Dielectric layer on the front-end architecture；Through hole in the dielectric layer, the through hole exposure
Go out the front end mark.Thus expose front end mark to thick dielectric layer, realize that normal photolithography aligns, improve existing multiexposure, multiple exposure
Branch mode bring to inclined problem, eliminate thick dielectric layer can not alignment issues, and evaded double-sided exposure, effectively prevented pair
The scraping of silicon chip scratches, it is ensured that preferable alignment quality, is advantageous to the alignment of subsequent film.
Brief description of the drawings
Fig. 1-Fig. 3 shows the structural representation in a kind of dielectric layer alignment method；
Fig. 4 is the flow chart of the utility model dielectric layer alignment method；
Fig. 5 is the schematic diagram that front-end architecture is provided in the embodiment of the utility model one；
Fig. 6 is the schematic diagram for arranging front end mark in the embodiment of the utility model one on front-end architecture；
Fig. 7 is the schematic diagram for forming dielectric layer in the embodiment of the utility model one on front-end architecture；
Fig. 8 is to coat photoresist and the schematic diagram being open in the embodiment of the utility model one on dielectric layer；
Fig. 9 is schematic diagram when being exposed in the embodiment of the utility model one to a piece of silicon chip；
Figure 10 is the schematic diagram of an exposing unit in the embodiment of the utility model one；
Figure 11 is the schematic diagram that etch media layer forms through hole in the embodiment of the utility model one；
Figure 12 is the schematic diagram of the semiconductor structure obtained in the embodiment of the utility model one；
Figure 13 is the schematic top plan view of through hole and front end mark in the embodiment of the utility model one；
Figure 14 is the schematic top plan view of through hole and front end mark in another embodiment of the utility model.
Embodiment
Dielectric layer alignment method of the present utility model and semiconductor structure are carried out below in conjunction with schematic diagram more detailed
Description, which show preferred embodiment of the present utility model, it should be appreciated that those skilled in the art can change and be described herein
The utility model, and still realize advantageous effects of the present utility model.Therefore, description below is appreciated that for ability
Field technique personnel's is widely known, and is not intended as to limitation of the present utility model.
The utility model is more specifically described by way of example referring to the drawings in the following passage.According to following explanation and power
Sharp claim, advantages and features of the present utility model will become apparent from.It should be noted that accompanying drawing using very simplified form and
Non- accurately ratio is used, only to purpose that is convenient, lucidly aiding in illustrating the utility model embodiment.
The utility model provides a kind of dielectric layer alignment method, including：
Step S11, there is provided front-end architecture, the front-end architecture have front end mark；
Step S12, dielectric layer is formed on the front-end architecture；
Step S13, photoresist is coated on the dielectric layer, and form opening in the photoresist, expose the medium
Layer, the opening surround the front end mark；
Step S14, etch the dielectric layer from the opening and form through hole, the through hole exposes the front end mark.
Thus expose front end by the additional deep etching method of normal photoetching to thick dielectric layer to mark, realize normal photolithography
Contraposition, eliminate thick dielectric layer can not alignment issues, improve that the branch mode of existing multiexposure, multiple exposure brings to inclined problem.
The dielectric layer alignment method and semiconductor structure of the present embodiment are described in detail with reference to Fig. 4-Figure 14.
As shown in figure 5, for step S11, there is provided front-end architecture 10, the front-end architecture 10 have front end mark 11.Institute
State front-end architecture 10 for example can be substrate, such as silicon substrate etc., or epitaxial layer or be silicon oxide layer, silicon nitride layer,
The arbitrary structures such as carbon-coating, even metal level, it can generally be formed on silicon chip.The front end mark 11 is located at front end knot
The upper surface of structure 10, for alignment afterwards, according to the difference of specific exposure bench, multiple front end marks 11 can be set, such as
It is 2,3,6,8 etc..Shape the utility model of the front end mark 11 does not limit, before being hereinafter related to
End mark 11 is only used as schematical example.
In one embodiment, after such as in view of deep etching (the formation through hole after i.e. in the utility model), it is
Improvement gluing uniformity, the front end mark 11 are placed on silicon chip edge position as far as possible.
As shown in fig. 6, so that photoetching process is operated using Nikon exposure machines as an example, the front end mark 11 can be set
Put including silicon chip integrally asymmetric mark (Wafer Global Asymmetric, WGA), laser step alignment mark (Laser
Step Alignment, LSA) and field picture alignment mark (Field Image Alignment, FIA) including, before this
The field of end mark 11 is placed more than or equal to 5 altogether, such as when being aligned, is first chosen 3 or 2 such fields and marked by WGA
Remember row coarse alignment into, the field 5 and the above that reselection contains this front end mark 11 carry out fine alignment by LSA and FIA marks,
And realize exposure.Required it is understood that the placement location of front end mark 11 meets that exposure bench mark is placed.In order to have
Help the formation of follow-up opening and through hole, can to meet 30 μm between the front end mark 11 and follow-up opening frontier distance
Spacing above.Such as each rectangular block 30 in Fig. 6 to the placement of front end mark 11 as described in aiding in completing, for example, phase up and down
Adjacent two rectangular blocks 30 can limit an exposing unit.In addition, rectangular block 30 and in the absence of on the front-end architecture, only makees
For program booster action.
As shown in fig. 7, for step S12, dielectric layer 12 is formed on the front-end architecture 10.In one embodiment,
The thickness H of the dielectric layer 12 be more than or equal to 20 μm, for the product of demand thickness dielectric layer 12, when dielectric layer 12 be more than etc.
When 20 μm, dielectric layer 12 is serious to mark spreadability, and exposure bench can not differentiate marking signal, as remembered in background technology
Carry, possibly can not realize the normal contraposition of photoetching, the utility model is exactly the method proposed for this thicker dielectric layer 12.
The dielectric layer 12 is covered on the front end mark 11.The dielectric layer 12 for example can be epitaxial layer, or silica
Layer, silicon nitride layer, even carbon-coating, metal level etc., but in order to be subsequently formed through hole, the selection of the dielectric layer 12 needs and institute
The selection difference for stating front-end architecture material is preferred, so that by different etching selection ratios, in favor of etching.
As shown in figure 8, for step S13, photoresist 13 is coated on the dielectric layer 12, and formed in photoresist 13
Opening 131, exposes the dielectric layer 12, and the opening 131 surrounds the front end mark 11, i.e. 131 face institutes of the opening
Front end mark 11 is stated, and it is parallel more than front end mark 11 parallel to the width (cross-sectional width) of the surface direction of front-end architecture 10
In the size of the surface direction of front-end architecture 10.It is described be open for dielectric layer 12 is performed etching to be formed through hole 121 (will such as figure
Described in step S14 shown in 11), it is contemplated that stepped locations (i.e. through-hole side wall and bottom wall after the final formation of through hole 121
Place) effect of signals may be produced to front end mark 11, hence in so that the opening 131 left compared to front end mark 11 it is remaining
Amount.
Specifically, this step S13 can be to be exposed (i.e. blind exposure) and then development shape using the autoregistration of exposure bench
Into opening 131, it is possible thereby to which so that the opening 131 surrounds the front end mark 11.
Fig. 9 is refer to, in the exposure for carrying out a silicon chip 100, the silicon chip 100 there can be multiple exposing units
(shot) 20, such as can be exposed for the exposing unit 20 (as shown in Figure 9) at the place of front end mark 11 arranged in Fig. 6
Light.It is understood that it is different according to the exposure technology of use, corresponding exposure parameter can be used to set, completed to covering
The exposure of photoresist at lid front end mark 11.
Figure 10 is refer to, it illustrates an exposing unit 20, the exposing unit 20 includes a secondary home court of field 22 and one
21, the opening 131 is formed in the secondary field 22, and described remaining position of exposing unit 20 is all covered by photoresist.
As shown in figure 11, for step S14, etch the dielectric layer 12 from the opening and form through hole 121, the through hole
121 expose the front end mark 11.It is mask i.e. with the photoresist 13, by photoresist 13 and the dielectric layer 12 not
With etching selection ratio to etch figure of the through hole 121 in longitudinal direction, complete the etching to the dielectric layer 12, such as
It can be completed using wet etching.
Further, the photoresist is removed, as shown in figure 12.
Specifically, in one embodiment, the through hole 121 is identical with the quantity of the front end mark 11 and one a pair
Should, the through hole 121 matches with the graphics shape of front end mark 11.As shown in figure 13, the through hole 121 is shaped as square
Shape.The front end mark 11 is cross, and the front end mark 11 has a boundary rectangle 111, the through hole 121 with it is described outer
It is overlapping and surround the boundary rectangle 111 to connect the center of rectangle 111.In one embodiment, it is contemplated that in order to prevent the side of through hole 121
Boundary may influence exposure bench and scan the front end mark 11, remember 121 each side of through hole to the centre distance be D, wherein D
=D0+C, D0 be the boundary rectangle 111 side arrive the center distance, C be one expression distance constant, C≤50 μm, this
Influence of the border of through hole 121 to exposure bench can be evaded falling by one data area, and excessive, be unfavorable for miniaturization production.
In one embodiment, such as C=20 μm, C=30 μm etc., C size according to actual demand, can be set.It is understood that
In the case of non-square, refer to each boundary rectangle 111 while and through hole 121 corresponding thereto while each to institute
The distance for stating center meets above-mentioned D=D0+C.Because the area of through hole 121 is big, the front end mark can be completely exposed
11, therefore help to carry out follow-up alignment.
It is understood that the shape of generally front end mark 11 is all close to or can extended as rectangle, therefore make
Front end mark 11 can farthest be exposed as rectangular-shaped by obtaining the through hole 121.Certainly, this can not turn into through hole
The limitation of 121 shapes, such as circular even triangle is also acceptable, it is only necessary to front end mark 11 can be completely exposed
Out.
Figure 14 is refer to, shows a case that the front end mark 11 of other shapes.Such as front end mark 11 here includes 3
Part, can be certainly other shapes per part as an example, this 3 part is rectangle, then, can be with the basis of this 3 part
A boundary rectangle 111 is obtained, for the ease of identification, mark center O.Formed with through hole 121, the through hole in dielectric layer 12
The 121 and encirclement boundary rectangles 111 overlapping with the center O of boundary rectangle 111.In one embodiment, it is contemplated that in order to
Prevent the border of through hole 121 from may influence exposure bench and scanning the front end mark 11, remember through hole 121 each side to the center
O distances are D, wherein D=D0+C, and D0 is that the side of the boundary rectangle 111 represents distance to the distance of the center O, C for one
Influence of the border of through hole 121 to exposure bench can be evaded falling by constant, C≤50 μm, this data area, and excessive then unfavorable
Produced in miniaturization.In one embodiment, such as C=20 μm, C=30 μm etc., the big of C can be set according to actual demand
It is small.Likewise, in the case of non-square, the side of each boundary rectangle 111 and through hole 121 corresponding thereto are referred to
The distance that the center is each arrived on side meets above-mentioned D=D0+C.
Description of the present utility model has been carried out exemplified by using Nikon exposure machines, it is to be understood that this practicality is new above
The method of type can be applied in other exposure bench, such as in scan-type (scan) equipment, and step-by-step movement (step) equipment.
All be " required front end mark is first arranged on front-end architecture, then carries out the formation of dielectric layer (such as thickness >=20 μm),
Front end mark is covered, then the photoresist of patterning is formed by photoetching process, the front end mark is under the opening of photoresist
Side, dielectric layer is then performed etching with photoresist opening, expose front end mark " as process.For different exposure machines
Platform, it is only necessary to which the specific object and quantity of the adjustment front end mark 11 of adaptability, those skilled in the art are reading
After the utility model, flexibly it can be operated certainly using different exposure bench.
Please continue to refer to Figure 12 and Figure 13, a kind of semiconductor structure of the utility model acquisition, including：
Front-end architecture 10, the front-end architecture 10 have front end mark 11；
Dielectric layer 12 on the front-end architecture 10, the thickness H of the dielectric layer 12 are more than or equal to 20 μm；
Through hole 121 in the dielectric layer 12, the through hole 121 expose the front end mark 11.
Wherein, in one embodiment, the through hole 121 is identical with the quantity of the front end mark 11 and corresponds,
The through hole 121 matches with the graphics shape of front end mark 11.For example, the through hole 121 is shaped as rectangle, the front end
11 cross of mark, the front end mark 11 have a boundary rectangle 111, the through hole 121 with the boundary rectangle 111
The heart is overlapping and surrounds the boundary rectangle 111.In one embodiment, it is contemplated that in order to prevent the border of through hole 121 from may influence
Exposure bench scans the front end mark 11, remember 121 each side of through hole to the centre distance be D, wherein D=D0+C, D0
For the boundary rectangle 111 side to the center distance, C be one represent distance constant, C≤50 μm, this data model
Enclosing can evade falling by influence of the border of through hole 121 to exposure bench, and excessive, be unfavorable for miniaturization production.In an implementation
In example, such as C=20 μm, C=30 μm etc., C size according to actual demand, can be set.It is understood that for anon-normal
Square situation, refer to each boundary rectangle 111 while and through hole 121 corresponding thereto while each arrive the center
Distance meets above-mentioned D=D0+C.Because the area of through hole 121 is big, the front end mark 11 can be completely exposed, therefore have
Help carry out follow-up alignment.
It is understood that the shape of generally front end mark 11 is all close to or can extended as rectangle, therefore make
Front end mark 11 can farthest be exposed as rectangular-shaped by obtaining the through hole 121.Certainly, this can not turn into through hole
The limitation of 121 shapes, such as circular even triangle is also acceptable, it is only necessary to front end mark 11 can be completely exposed
Out.
Compared with prior art, the utility model is exposed to thick dielectric layer by the additional deep etching method of normal photoetching
Front end marks, and realizes that normal photolithography aligns, improve that the branch mode of existing multiexposure, multiple exposure brings to inclined problem, eliminate thick medium
Layer can not alignment issues, and evaded double-sided exposure, effectively prevented the scraping to silicon chip from scratching.Half obtained by this method
Conductor structure, there is preferable alignment quality, be advantageous to the alignment of subsequent film.
Obviously, those skilled in the art can carry out various changes and modification without departing from this practicality to the utility model
New spirit and scope.So, if these modifications and variations of the present utility model belong to the utility model claims and
Within the scope of its equivalent technologies, then the utility model is also intended to comprising including these changes and modification.
Claims (9)
1. a kind of semiconductor structure, including：
Front-end architecture, the front-end architecture have front end mark；
Dielectric layer on the front-end architecture；
Through hole in the dielectric layer, the through hole expose the front end mark.
2. semiconductor structure as claimed in claim 1, it is characterised in that the thickness of the dielectric layer is more than or equal to 20 μm.
3. semiconductor structure as claimed in claim 2, it is characterised in that the front-end architecture is substrate, epitaxial layer, silica
One kind in layer, silicon nitride layer, carbon-coating or metal level.
4. semiconductor structure as claimed in claim 3, it is characterised in that the dielectric layer is epitaxial layer, silicon oxide layer, nitridation
It is different from the another kind of the front-end architecture in silicon layer, carbon-coating or metal level.
5. semiconductor structure as claimed in claim 1, it is characterised in that the through hole is identical with the quantity that the front end marks
And correspond.
6. semiconductor structure as claimed in claim 5, it is characterised in that the through hole and the front end marker graphic shape
Match somebody with somebody.
7. semiconductor structure as claimed in claim 6, it is characterised in that the through hole is shaped as rectangle, the front end mark
Note has a boundary rectangle, and the through hole is overlapping with the boundary rectangle center and surrounds the boundary rectangle.
8. semiconductor structure as claimed in claim 7, it is characterised in that each side of through hole to the centre distance is D, its
Middle D=D0+C, D0 be the boundary rectangle side arrive the center distance, C be one expression distance constant.
9. semiconductor structure as claimed in claim 8, it is characterised in that C≤50 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720901359.5U CN206921816U (en) | 2017-07-24 | 2017-07-24 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720901359.5U CN206921816U (en) | 2017-07-24 | 2017-07-24 | Semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206921816U true CN206921816U (en) | 2018-01-23 |
Family
ID=61347068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720901359.5U Active CN206921816U (en) | 2017-07-24 | 2017-07-24 | Semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206921816U (en) |
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2017
- 2017-07-24 CN CN201720901359.5U patent/CN206921816U/en active Active
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