CN206893608U - High-density system-in-package structure - Google Patents
High-density system-in-package structure Download PDFInfo
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- CN206893608U CN206893608U CN201720571575.8U CN201720571575U CN206893608U CN 206893608 U CN206893608 U CN 206893608U CN 201720571575 U CN201720571575 U CN 201720571575U CN 206893608 U CN206893608 U CN 206893608U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Abstract
The utility model discloses a kind of system-in-package structure, including：System in package SiP substrates；One or more elements on the SiP substrates；And the adapter unit on the SiP substrates, there is conducting wire, the first face of the adapter unit has the structure electrically connected with the SiP substrates, has pad on the second face of the adapter unit on the adapter unit.System-in-package structure disclosed in the utility model effectively can utilize or reduce the area of package substrate, realize higher integrated level, while obtain relatively reliable interconnection.
Description
Technical field
It the utility model is related to field of semiconductor package, more particularly to high-density system-in-package structure.
Background technology
With the continuous development of integrated circuit technique, electronic product is increasingly to miniaturization, intelligent, high-performance and height
Reliability direction is developed.And integrated antenna package not only directly affects the performance of integrated circuit, electronic module or even complete machine, and
And also govern miniaturization, cost degradation and the reliability of whole electronic system.Progressively contracted in IC chip critical size
Small, in the case that integrated level improves constantly, electronics industry proposes higher and higher requirement to integrated antenna package technology, and by
This promotes system in package SiP (System In a Package) generation and development.
According to international semiconductor Freight Vehicles ' Route Organization (ITRS) definition：System in package SiP refers to has difference by multiple
The active electron component of function is assemblied together with optional passive device, realizes the single standard packaging part of certain function, is formed
One system or subsystem.Generally, matched in SiP technologies with active device passive passive device (peripheral circuit,
Discrete device) occupy about 80% package substrate area.To adapt to the development trend of electronic product " light, thin, short, small ", have
Necessity exploitation High Density Integration SiP package modules, further reduce the PCB main board area that encapsulation takes.
Existing SiP technologies not only can be by microprocessor, memory (such as EPROM and DRAM), FPGA, resistance, electric capacity
Merge the packaging part for forming certain function in a package with inductance, can also be by micro-electromechanical system (MEMS) device, optics member
The combination such as part, various kinds of sensors forms the packaging part of certain function in same encapsulation.
By Vertical collection, SiP encapsulation technologies can also shorten interconnection distance, can so shorten signal delay time,
Reduce noise and reduce parasitic capacitance, parasitic resistance effect, making signaling rate, faster power consumption is lower.
However, existing SiP encapsulation chip integration still needs to be lifted, package dimension is still zoomed out.Therefore need a kind of new
SiP encapsulating structures, effectively utilize or reduce the area of package substrate, realize higher integrated level, while obtain relatively reliable
Interconnection.
Utility model content
Existing SiP encapsulation chip integration is still needed to be lifted, and package dimension is still zoomed out.
For problems of the prior art, embodiment of the present utility model provides a kind of system-in-package structure, bag
Include：System in package SiP substrates；One or more elements on the SiP substrates；And installed in the SiP bases
Adapter unit on plate, there is conducting wire on the adapter unit, the first face of the adapter unit has and the SiP bases
The structure of plate electrical connection, has pad on the second face of the adapter unit.
In embodiment of the present utility model, the adapter unit is the slotted substrate of center section hollow out, this or more
Individual element is arranged on the SiP substrates by openwork part.
In embodiment of the present utility model, adapter unit is the grid pinboard of part hollow out, and the one or more is first
Part is arranged on the SiP substrates by the grid of hollow out.
In embodiment of the present utility model, adapter unit is block pinboard.
In embodiment of the present utility model, the Outside Dimensions of adapter unit are not more than the Outside Dimensions of the SiP substrates,
The height of the adapter unit is not less than the height of one or more of elements.
In embodiment of the present utility model, one or more elements include bare chip, chip package, passive element,
One or more of micro-electromechanical system (MEMS) device, optical element, communication device, sensor.
In embodiment of the present utility model, one or more elements include：Installed in the first surface of the SiP substrates
On the element of one or more first；And on the second surface relative with the first surface of the SiP substrates
The element of one or more second.
In embodiment of the present utility model, adapter unit is arranged on the first surface and/or the institute of the SiP substrates
State on second surface.
In embodiment of the present utility model, the system-in-package structure is also encapsulated in the SiP substrates, described one
Plastic package structure outside individual or multiple element and the adapter unit, wherein the pad is exposed at the outer of the plastic package structure
Portion.
In embodiment of the present utility model, the system-in-package structure also includes the soldered ball being arranged on the pad.
Another embodiment of the present utility model provides a kind of method of manufacture system class encapsulation structure, including：System is provided
Irrespective of size encapsulates SiP substrates；One or more elements are installed on the surface of the SiP substrates；On the surface of the SiP substrates
Adapter unit is installed, there is conducting wire on the adapter unit, the first face of the adapter unit has and the SiP substrates
The structure of electrical connection, there is pad on the second face of the adapter unit.
In another embodiment of the present utility model, one or more elements are installed on the surface of SiP substrates to be included：
One or more elements are installed on the first surface of the SiP substrates；One is installed on the second surface of the SiP substrates
Or multiple element.
In another embodiment of the present utility model, this method also includes will be in SiP substrates together with installed in its surface
On element and adapter unit be encapsulated, wherein the pad is exposed at the outside of encapsulation.
In another embodiment of the present utility model, this method also includes：Ball is planted on the pad.
The high-density system-in-package structure provided by embodiment of the present utility model has the following advantages that：
1. system-in-package structure disclosed in the utility model can encapsulate multiple chips in same packaging body, use is two-sided
Attachment process, package substrate area is reused, packaging efficiency greatly improves, so as to greatly reduce encapsulation volume.
2. system-in-package structure disclosed in the utility model can be formed the chip package by different process, material making
One system, for example, the chip based on Si, GaAs, InP can be carried out into integrative packaging, there is compatibility well, in addition,
System-in-package structure disclosed in the utility model can be not only used for analog- and digital- System on Chip/SoC encapsulation, can be also used for light
Communication, sensor and micro-electromechanical system (MEMS) encapsulation.
3. system-in-package structure disclosed in the utility model can make multiple encapsulation integrate, so that total solder joint
Quantity is greatly reduced, and substantially reduces encapsulation volume, weight, shortens the adapter path of element, so that electrical property is improved, tool
There are the ability of good resistance to mechanical and chemical attack and high reliability.
4. system-in-package structure disclosed in the utility model can complete an aims of systems using a packaging body
Whole interconnection of property right and function and performance parameter, it can be interconnected simultaneously using wire bonding with flip chip bonding and other IC chips are straight
Connect interior company's technology.
5. system-in-package structure disclosed in the utility model can provide low-power consumption and the system-level connection of low noise,
Higher operation at frequencies can obtain highway width almost equal with SOC.
6. related process technologies are more ripe used in system-in-package structure disclosed in the utility model, failure is integrated
Risk is relatively low, and compatible with existing packaging technology, without increasing producing line hardware input, greatly shortens the week of launch products
Phase.
Brief description of the drawings
In order to further elucidate the above and other advantages and features of each embodiment of the present utility model, refer to the attached drawing is come
The more specifically description of each embodiment of the present utility model is presented.It is appreciated that these accompanying drawings only describe allusion quotation of the present utility model
Type embodiment, therefore be not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding portion
Part will be represented with same or similar mark.
Fig. 1 shows the diagrammatic cross-section of the system in package SiP structures 100 according to one embodiment of the present utility model.
Fig. 2 shows the top view of the system in package SiP structures 100 shown in Fig. 1.
Fig. 3 A to Fig. 3 C show the top view of the optional example of a variety of adapter units.
Fig. 4 shows the diagrammatic cross-section of system in package SiP structures 400 according to another embodiment of the present utility model.
Fig. 5 A to Fig. 5 G show to form high-density systems level encapsulation SiP structures according to one embodiment of the present utility model
The diagrammatic cross-section of process.
Fig. 6 shows to form the process of high-density systems levels encapsulation SiP structures according to one embodiment of the present utility model
Flow chart 600.
Embodiment
In the following description, the utility model is described with reference to each embodiment.However, those skilled in the art
It will be recognized that each embodiment can be implemented in the case of neither one or multiple specific details or replace and/or add with other
Method, material or component implement each embodiment together.In other situations, it is not shown or known structure, material is not described in detail
Material is operated in order to avoid making the aspects of each embodiment of the present utility model obscure.Similarly, for purposes of explanation, spy is elaborated
Fixed number amount, material and configuration, to provide the comprehensive understanding to embodiment of the present utility model.However, the utility model can be
Do not have to implement in the case of specific detail.Further, it should be understood that each embodiment shown in accompanying drawing be it is illustrative expression and not necessarily
It is drawn to scale.
In this manual, the reference to " one embodiment " or " embodiment " means to combine embodiment description
Special characteristic, structure or characteristic are included at least one embodiment of the present utility model.In this specification middle appearance everywhere
Phrase be not necessarily all referring to the same embodiment " in one embodiment ".
In order to improve SiP encapsulation chip integrations, and relatively reliable interconnection is obtained, an implementation of the present utility model
Example provides a kind of SiP encapsulating structures, as shown in Figure 1.
Fig. 1 shows the diagrammatic cross-section of the system in package SiP structures 100 according to one embodiment of the present utility model.
SiP structures 100 include system in package SiP substrates 110, one or more elements 120 on SiP substrates 110 and
Adapter unit 130 on SiP substrates 110.
In embodiment of the present utility model, SiP substrates 110 can provide mechanical support and electrical interconnection.In the utility model
Specific embodiment in, SiP substrates 110 can improve the packaging efficiency of system with embedding passive element, and passive element can be with
It is inductance, electric capacity, resistance, wave filter, antenna etc..
The material of SiP substrates 110 may be selected from following material：It is high-molecular organic material, liquid crystal polymer LCP, low temperature co-fired
Multi-layer ceramics LTCC, particles reiforced metal-base composition etc..These materials have higher the wiring number of plies and density, are adapted to each
The High Density Integration of kind component.
In the example depicted in fig. 1, one or more elements 120 are installed on the surface 111 of SiP substrates 110.
For example, element 120 can be bare chip or chip package.The bare chip or chip package can be simulation collection
Into circuit chip or digital integrated circuit chip.Analogous Integrated Electronic Circuits chip may include operational amplifier, multiplier, integrated voltage-stabilized
Device, timer, signal generator etc..Digital integrated circuit chip may include a variety of gate circuits (i.e. NAND gate, NOT gate, OR gate
Deng), data selector, coder-decoder, trigger, counter, register, memory, PLD (PLD),
ASIC (application specific integrated circuit) etc..
Element 120 can also be passive element, such as resistance, inductance, electric capacity etc..Element 120 can also be micro-electro-mechanical systems
System MEMS, optical element, communication device, various kinds of sensors etc..
In embodiment of the present utility model, element 120 can be arranged on by the interconnection technique of various chips and component
On the surface 111 of SiP substrates 110.For example, BGA flip chip bondings, wire bonding, tape automated bonding, flip-chip key can be passed through
Close, crimp flip-chip interconnection, penetrate the technologies such as silicon chip interconnection by element 120 on the surface 111 of SiP substrates 110, but this reality
Technology listed above is not limited to new available interconnection technique.Those skilled in the art can select according to being actually needed
Specific chip and/or component are arranged on the surface of SiP substrates by appropriate interconnection technique.Therefore, for simplified and clear
See, omit the detailed description of the interconnection technique of chip and component herein.
In the example depicted in fig. 1, adapter unit 130 is installed on the surface 111 of SiP substrates 110.Can be single in switching
Conducting wire is provided with member 130, its bottom surface 131 has a structure being connected with the electricity of SiP substrates 110, signal, on its top surface 132
With external pad 133, so as to realize SiP substrates and outside electricity, signal interconnection.Although in the specific example shown in Fig. 1,
Adapter unit 130 is arranged on element 120 on the same surface 111 of SiP substrates 110, but those skilled in the art should
, it is realized that the scope of protection of the utility model not limited to this.For example, adapter unit 130 can be arranged on to the of SiP substrates 110
On two surfaces 112.
In embodiment of the present utility model, adapter unit 130 can be the slotted substrate of a piece of center section hollow out.Figure
2 show the top view of the system in package SiP structures 100 shown in Fig. 1.
However, adapter unit is not limited to the hollow substrate shown in Fig. 2, adapter unit can also be other shapes.For example,
Fig. 3 A to Fig. 3 C show the top view of the optional example of a variety of adapter units.As shown in Figure 3A, adapter unit 130 can be multistage
Discrete banding pinboard, there is external pad 133 on its top surface.As shown in Figure 3 B, adapter unit 130 can be part hollow out
The latticed pinboard of class, there is external pad 133 on its top surface, multiple element 120 can be sealed by each grid hollow part
It is filled on SiP substrates 110.As shown in Figure 3 C, adapter unit 130 can be the block pinboard of discrete distribution, have on its top surface
There is external pad 133.It is not limited to it should be appreciated by those skilled in the art the shape of, adapter unit 130 listed above specific
Shape, it can realize that SiP substrates each fall within protection model of the present utility model with outside electricity, any adapter unit of signal interconnection
Enclose.The Outside Dimensions of adapter unit are not more than the Outside Dimensions of SiP substrates 110, or are slightly less than the peripheral chi of SiP substrates 110
It is very little.The height of adapter unit is not less than the height of element 120.In an example of the present utility model, the thickness of interposer substrate
In 0.2mm between 1.2mm.
For the integrated level of further lifting system level encapsulation SiP chips, another embodiment of the present utility model provides
Another SiP encapsulating structures, pass through two-sided the installation active electron component and/or passive device in package substrate, two-sided repetition
Using package substrate area, higher integrated level is realized, while obtain relatively reliable interconnection.Fig. 4 shows new according to this practicality
The diagrammatic cross-section of system in package SiP structures 400 of another embodiment of type.
SiP structures 400 include system in package SiP substrates 410, on the first surface 411 of SiP substrates 410
First element 420 and the second element 430, third element 440 and quaternary on the second surface 412 of SiP substrates 410
Part 450 and the adapter unit 460 on the second surface 412 of SiP substrates 410.
SiP substrates 410 are similar with the SiP substrates 110 shown in Fig. 1, therefore omit its specific descriptions.
First element 420 can be bare chip or chip package.Second element 430 can be passive element, such as electricity
Resistance, inductance, electric capacity etc..Second element 430 can also be micro-electromechanical system (MEMS) device, optical element, communication device, all kinds of biographies
Sensor etc..
Although in the specific example shown in Fig. 4, two kinds of member is installed on the first surface 411 of SiP substrates 410
Part, but it should be appreciated by one skilled in art that the scope of protection of the utility model not limited to this, for example, in SiP substrates
The element of a type of element or three kinds or more type can be only installed on 410 first surface 411.
Third element 440 can be bare chip or chip package.Fourth element 450 can be passive element, such as electricity
Resistance, inductance, electric capacity etc..Fourth element 450 can also be micro-electromechanical system (MEMS) device, optical element, communication device, all kinds of biographies
Sensor etc..
It is similar with first surface 411, can only be installed on the second surface 412 of SiP substrates 410 a type of element or
The element of person's three kinds or more type.
First element 420 to fourth element 450 can be arranged on SiP substrates by the interconnection technique of various chips and component
On 410 surface.
In the example depicted in fig. 4, adapter unit 460 is installed on the second surface 412 of SiP substrates 410.Switching is single
Member 460 is similar with the adapter unit 130 shown in Fig. 1 to Fig. 3, therefore, is not described in detail.It is worthy of note that can be according to tool
The needs of body, adapter unit 460 is arranged on SiP substrates 410 any one or two surfaces.
With reference to Fig. 5 A to Fig. 5 G, introduce and the encapsulation of high-density systems level is formed according to one embodiment of the present utility model
The process of SiP structures 400.Fig. 5 A to Fig. 5 G show to form the encapsulation of high-density systems level according to one embodiment of the present utility model
The diagrammatic cross-section of the process of SiP structures 400.
As shown in Figure 5A, first, there is provided system in package SiP substrates 510.SiP substrates 510 are the important composition portions of system
Point.In embodiment of the present utility model, SiP substrates 510 can provide mechanical support and electrical interconnection.Of the present utility model specific
In embodiment, SiP substrates 510 can improve the packaging efficiency of system with embedding passive element, passive element can be inductance,
Electric capacity, resistance, wave filter, antenna etc..
Next, one or more elements are installed on the first surface 511 of SiP substrates 510.In the example shown in Fig. 5 B
In, the first element 520 and the second element 530 are installed on the first surface 511 of SiP substrates 510.
For example, the first element 520 can be bare chip or chip package.Second element 530 can be passive element, example
Such as resistance, inductance, electric capacity.Second element 530 can also be micro-electromechanical system (MEMS) device, optical element, communication device, each
Class sensor etc..
Although in the specific example shown in Fig. 5 B, installed on the first surface 511 of SiP substrates 510 two kinds of
Element, but it should be appreciated by one skilled in art that the scope of protection of the utility model not limited to this, for example, in SiP bases
The element of a type of element or three kinds or more type can be only installed on the first surface 511 of plate 510.
, can be by the interconnection technique of various chips and component by the He of the first element 520 in embodiment of the present utility model
Second element 530 is arranged on the first surface 511 of SiP substrates 510, including but not limited to BGA flip chip bondings, wire bonding, load
Band automated bonding, flip-chip bonding, crimp flip-chip interconnection, penetrate silicon chip interconnection etc..
Then, as shown in Figure 5 C, SiP substrates 510 are overturn so that second surface 512 is upward.
Next, one or more elements are installed on the second surface 512 of SiP substrates 510.In the example shown in Fig. 5 D
In, third element 540 and fourth element 550 are installed on the second surface 512 of SiP substrates 510.
For example, third element 540 can be bare chip or chip package.Fourth element 550 can be passive element, example
Such as resistance, inductance, electric capacity.Fourth element 550 can also be micro-electromechanical system (MEMS) device, optical element, communication device, each
Class sensor etc..
Although in the specific example shown in Fig. 5 D, installed on the second surface 512 of SiP substrates 510 two kinds of
Element, but it should be appreciated by one skilled in art that the scope of protection of the utility model not limited to this, for example, in SiP bases
The element of a type of element or three kinds or more type can be only installed on the second surface 512 of plate 510.
Next, as shown in fig. 5e, adapter unit 560 is installed on the second surface 512 of SiP substrates 510.Adapter unit
Contact disc is provided with 560 the first face, contact disc and SiP substrates 510 can be realized by soldered ball or other electric connection structures 561
Electricity, signal interconnection.External pad 562 is provided with the face of adapter unit 560 second.
Next, carry out optional plastic packaging process, as illustrated in figure 5f, will SiP substrates 510 together with installation in its surface
First to fourth element and the plastic packaging of adapter unit 560 get up.In order to realize SiP encapsulation and extraneous interconnection, external pad
562 are exposed at the outside of plastic packaging.Those skilled in the art can according to being actually needed, using specific injection molding process technology and
Equipment, complete above-mentioned plastic packaging process.In other embodiment of the present utility model, die press technology for forming can be used, will be in SiP bases
Plate 510 is encapsulated together with first to fourth element and adapter unit 560 installed in its surface.
Next, as depicted in fig. 5g, it can carry out optionally planting the process of ball 570 on reserved external pad 562, realize
SiP encapsulating structures and extraneous electricity, signal interconnection.
Fig. 6 shows to form the process of high-density systems levels encapsulation SiP structures according to one embodiment of the present utility model
Flow chart 600.
In step 610, there is provided system in package SiP substrates.
In step 620, one or more elements are installed on the first surface of SiP substrates.In implementation of the present utility model
In example, the element can be bare chip, chip package, passive element, such as resistance, inductance, electric capacity etc., MEMS
One or more of MEMS, optical element, communication device, various kinds of sensors etc..
Alternatively, in step 630, one or more elements are installed on the second surface of SiP substrates.In the utility model
Embodiment in, the element can be bare chip, chip package, passive element, such as resistance, inductance, electric capacity etc., micro electronmechanical
One or more of system MEMS, optical element, communication device, various kinds of sensors etc..
In step 640, adapter unit is installed on the surface of SiP substrates.Adapter unit can by soldered ball or other be electrically connected
Binding structure realizes electricity, the signal interconnection with SiP substrates.On the adapter unit surface relative with soldered ball or other electric connection structures
It is provided with external pad.
Alternatively, in step 650, will be encapsulated in SiP substrates together with the element and adapter unit installed in its surface
Get up.In order to realize that SiP encapsulation and extraneous interconnection, the external pad of adapter unit are exposed at the outside of plastic packaging.The skill of this area
Art personnel can complete above-mentioned plastic packaging process using specific injection molding process technology and equipment, can also adopt according to being actually needed
With die press technology for forming, will be encapsulated in SiP substrates together with the element and adapter unit installed in its surface.
Alternatively, in step 660, ball is planted on the external pad of reserved adapter unit, realizes SiP encapsulation and the external world
Electricity, signal interconnection.
The high-density system-in-package structure provided by embodiment of the present utility model has the following advantages that：
1. system-in-package structure disclosed in the utility model can encapsulate multiple chips in same packaging body, use is two-sided
Attachment process, package substrate area is reused, packaging efficiency greatly improves, so as to greatly reduce encapsulation volume.
2. system-in-package structure disclosed in the utility model can be formed the chip package by different process, material making
One system, for example, the chip based on Si, GaAs, InP can be carried out into integrative packaging, there is compatibility well, in addition,
System-in-package structure disclosed in the utility model can be not only used for analog- and digital- System on Chip/SoC encapsulation, can be also used for light
Communication, sensor and micro-electromechanical system (MEMS) encapsulation.
3. system-in-package structure disclosed in the utility model can make multiple encapsulation integrate, so that total solder joint
Quantity is greatly reduced, and substantially reduces encapsulation volume, weight, shortens the adapter path of element, so that electrical property is improved, tool
There are the ability of good resistance to mechanical and chemical attack and high reliability.
4. system-in-package structure disclosed in the utility model can complete an aims of systems using a packaging body
Whole interconnection of property right and function and performance parameter, it can be interconnected simultaneously using wire bonding with flip chip bonding and other IC chips are straight
Connect interior company's technology.
5. system-in-package structure disclosed in the utility model can provide low-power consumption and the system-level connection of low noise,
Higher operation at frequencies can obtain highway width almost equal with SOC.
6. related process technologies are more ripe used in system-in-package structure disclosed in the utility model, failure is integrated
Risk is relatively low, and compatible with existing packaging technology, without increasing producing line hardware input, greatly shortens the week of launch products
Phase.
Although described above is each embodiment of the present utility model, however, it is to be understood that they are intended only as example to be in
Existing, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, change can be made to it
Type and change are without departing from spirit and scope of the present utility model.Therefore, width and model of the present utility model disclosed herein
Enclosing should not be limited by above-mentioned disclosed exemplary embodiment, and should be according only to appended claims and its equivalent substitution
To define.
Claims (10)
1. a kind of high-density system-in-package structure, including：
System in package SiP substrates；
One or more elements on the SiP substrates；And
Adapter unit on the SiP substrates, has conducting wire on the adapter unit, and the of the adapter unit
Simultaneously there is the structure electrically connected with the SiP substrates, there is pad on the second face of the adapter unit.
2. high-density system-in-package structure as claimed in claim 1, it is characterised in that the adapter unit is center section
The slotted substrate of hollow out, one or more of elements are arranged on the SiP substrates by openwork part.
3. high-density system-in-package structure as claimed in claim 1, it is characterised in that the adapter unit is part hollow out
Grid pinboard, one or more of elements are arranged on the SiP substrates by the grid of hollow out.
4. high-density system-in-package structure as claimed in claim 1, it is characterised in that the adapter unit is block switching
Plate.
5. high-density system-in-package structure as claimed in claim 1, it is characterised in that the Outside Dimensions of the adapter unit
No more than the Outside Dimensions of the SiP substrates, the height of the adapter unit is not less than the height of one or more of elements.
6. high-density system-in-package structure as claimed in claim 1, it is characterised in that one or more of elements include
One in bare chip, chip package, passive element, micro-electromechanical system (MEMS) device, optical element, communication device, sensor
It is individual or multiple.
7. high-density system-in-package structure as claimed in claim 1, it is characterised in that one or more of element bags
Include：
The element of one or more first on the first surface of the SiP substrates；And
The element of one or more second on the second surface relative with the first surface of the SiP substrates.
8. high-density system-in-package structure as claimed in claim 7, it is characterised in that the adapter unit is arranged on described
On the first surface and/or the second surface of SiP substrates.
9. high-density system-in-package structure as claimed in claim 1, it is characterised in that be also encapsulated in the SiP bases
Plastic package structure outside plate, one or more of elements and the adapter unit, wherein the pad is exposed at the plastic packaging
The outside of structure.
10. high-density system-in-package structure as claimed in claim 9, it is characterised in that also include being arranged on the pad
On soldered ball.
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| CN201720571575.8U CN206893608U (en) | 2017-05-22 | 2017-05-22 | High-density system-in-package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017212A (en) * | 2017-05-22 | 2017-08-04 | 华进半导体封装先导技术研发中心有限公司 | High-density system-in-package structure and its manufacture method |
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2017
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107017212A (en) * | 2017-05-22 | 2017-08-04 | 华进半导体封装先导技术研发中心有限公司 | High-density system-in-package structure and its manufacture method |
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