CN206876303U - A kind of optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature - Google Patents
A kind of optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature Download PDFInfo
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- CN206876303U CN206876303U CN201720811493.6U CN201720811493U CN206876303U CN 206876303 U CN206876303 U CN 206876303U CN 201720811493 U CN201720811493 U CN 201720811493U CN 206876303 U CN206876303 U CN 206876303U
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Abstract
A kind of optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature includes sensing circuit, compensation circuit, clock circuit, logic control circuit, analog to digital conversion circuit, serial interface circuit, selection circuit and storage element；The sensing circuit includes the positive temperature coefficient sensing circuit and negative temperature coefficient sensing circuit being connected with each other.The utility model is the optional TEMP chip of Positive and Negative Coefficient Temperature that monolithic semiconductor integrates, positive temperature coefficient sensing circuit, negative temperature coefficient sensing circuit and its compensation circuit, analog to digital conversion circuit, serial interface circuit etc. are integrated on chip piece simultaneously, terminal applies client can carry out positive temperature coefficient by the output of serial interface circuit and memory cell to chip simultaneously or negative temperature coefficient selects, and temperature coefficient is trimmed, realize the application characteristic that finished product uniformity is good, measurement is accurate, highly integrated, client is easy to use.
Description
Technical field
A kind of sensing chip is the utility model is related to, a kind of optional temperature of single-chip integration Positive and Negative Coefficient Temperature is especially provided and passed
Sense chip.
Background technology
Traditional temperature sensor is typically using devices such as thermocouple, RTD, bimetal releases, by encapsulation volume
Influence, be unfavorable for integrating, be unfavorable for the miniaturization of product.Traditional single chip integrated silicon substrate temperature sensor chip in addition, it is
Single positive temperature coefficient or negative temperature coefficient, and chip during production due to process drift, encapsulation stress etc.
The influence of factor, the temperature coefficient of finished product have fluctuation, and the uniformity of product is poor.
Utility model content
In order to solve the above problems, the purpose of this utility model is to provide a kind of positive temperature coefficient sensing circuit, negative temperature
Coefficient sensing circuit and its compensation circuit, analog to digital conversion circuit, serial interface circuit etc. are integrated in the list on chip piece simultaneously
Piece integrates the optional TEMP chip of Positive and Negative Coefficient Temperature.
To reach above-mentioned purpose, the technical solution of the utility model is as follows：A kind of single-chip integration Positive and Negative Coefficient Temperature is optional
TEMP chip includes sensing circuit, compensation circuit, clock circuit, logic control circuit, analog to digital conversion circuit, serial line interface
Circuit, selection circuit and storage element；The sensing circuit includes positive temperature coefficient sensing circuit and the negative temperature being connected with each other
Coefficient sensing circuit, positive temperature coefficient sensing circuit output voltage linear rise, negative temperature coefficient with the rising of temperature sensor
Sensing circuit output voltage linear decline with the rising of temperature sensor；The compensation circuit is connected with the sensing circuit, right
The factor for influenceing temperature sense precision is compensated or eliminated respectively；The selection circuit and the sensing circuit and analog-to-digital conversion
Circuit is connected, and the output of positive and negative temperature coefficient sensing circuit is carried out analog quantity to the transformation of digital quantity by analog to digital conversion circuit, is carried
The noise resisting ability of height output；The clock circuit provides clock signal for chip internal, with the logic control circuit and mould
Number change-over circuit connection；The logic control circuit provides logic control signal for chip internal, with the serial interface circuit
Connected with analog to digital conversion circuit；The output end connection of the serial interface circuit input and analog-digital conversion circuit as described, as
The communication interface of chip and external signal, it is exported the sensing amount for reflecting temperature information；The memory cell input
It is connected with the serial interface circuit, two ports that client passes through serial interface circuit, it would be desirable to the positive negative temperature system of output
The Positive and Negative Coefficient Temperature amplitude that several selection signals and needs adjusts is stored in the unit, memory cell output end respectively with it is described
Selection circuit connects with sensing circuit, realizes control selections circuit respectively, according to the communication signal for being stored in memory cell module,
Selected the analog signal of chip output positive temperature coefficient or negative temperature coefficient by user and sensing circuit is trimmed, adjusted
The two functions of the temperature coefficient of chip.
Further, the positive temperature coefficient sensing circuit includes power supply, start-up circuit I, positive temperature coefficient voltage generation electricity
Road and voltage follower circuit I10；The power supply is connected with the start-up circuit I and positive temperature coefficient voltage generation circuit, is used for
Power supply；The start-up circuit I is connected with the positive temperature coefficient voltage generation circuit, when electric initial on the supply voltage, for just
Temperaturecoefficient voltage generation circuit provides initial current；The voltage follower circuit I10 produces with the positive temperature coefficient voltage
Circuit is connected, and load capacity is driven for strengthening.
Further, the start-up circuit I includes the first p-type FET MP11, the second p-type FET MP12, the first N
Type FET MN11, the second N-type FET MN12 and diode D11；The positive temperature coefficient voltage generation circuit includes
3rd p-type FET MP13, the 4th p-type FET MP14, the 5th p-type FET MP15, the first triode Q11,
Two triode Q12, resistance R11 and trim electric resistance array Rtrim1；The drain electrode of the first p-type FET MP11 connects the electricity
Source, drain electrode of the source electrode respectively with the positive pole and the first N-type FET MN11 of the diode D11 are connected, and grid is believed with ground connection
Number be connected；The drain electrode of the second p-type FET MP12 meets the power supply, source electrode and the second N-type FET MN12
Drain electrode be connected, grid respectively with the grid of the 3rd p-type FET MP13 and the 4th p-type FET MP14 grid
It is connected；The source electrode and diode with the first p-type FET MP11 respectively that drain of the first N-type FET MN11
D11 positive pole is connected, and source electrode is connected with ground signalling, and grid is connected with the grid of the second N-type FET MN12；It is described
Second N-type FET MN12 drain electrode is connected with the source electrode of the second p-type FET MP12, source electrode and ground signalling phase
Even, grid is connected with the grid of the first N-type FET MN11, and drain electrode is directly connected to grid both ends, the first N
Type FET MN11 and the second N-type FET MN12 forms the relation of current mirror；The positive pole of the diode D11 respectively with
The drain electrode of the source electrode of the first p-type FET MP11 and the first N-type FET MN11 is connected, and negative pole is respectively with described
Three p-type FET MP13 source electrode and the first triode Q11 colelctor electrode are connected；The 3rd p-type FET MP13's
Drain electrode connects the power supply, and source electrode is connected with the negative pole of the diode D11 and the first triode Q11 colelctor electrode respectively, grid
It is connected respectively with the grid of the second p-type FET MP12 and the 4th p-type FET MP14 grid；4th P
Type FET MP14 drain electrode connects the power supply, the source electrode grid and second with the 5th p-type FET MP15 respectively
Triode Q12 colelctor electrode is connected, the grid grid with the second p-type FET MP12 and the 3rd p-type field-effect respectively
Pipe MP13 grid is connected, and grid and source electrode both ends are directly connected to, the second p-type FET MP12 and the 4th p-type field
Effect pipe MP14 forms the relation of current mirror；The drain electrode of the 5th p-type FET MP15 connects the power supply, source electrode respectively with
Described one end for trimming electric resistance array Rtrim1 is connected with voltage follower circuit I10 positive input terminal, and grid is respectively with described
Four p-type FET MP14 source electrode and the second triode Q12 colelctor electrode are connected；The colelctor electrode of the first triode Q11
Be directly connected to base stage both ends, colelctor electrode respectively with the negative pole of the diode D11 and the 3rd p-type FET MP13 source electrode
It is connected, base stage is connected with the base stage of the second triode Q12, and emitter stage is connected with ground signalling；The second triode Q12
Colelctor electrode be connected respectively with the source electrode of the 4th p-type FET MP14 and the 5th p-type FET MP15 grid, base
Pole is connected with the base stage of the first triode Q11, and emitter stage is connected with one end of the resistance R11；The one of the resistance R11
End is connected with the emitter stage of the second triode Q12, and the other end is connected with ground signalling；It is described to trim electric resistance array Rtrim1
One end be connected respectively with the source electrode of the 5th p-type FET MP15 and voltage follower circuit I10 positive input terminal, it is another
End is connected with ground signalling.
Further, the resistance R11 and to trim electric resistance array Rtrim1 be same type resistance, and strictly match.
Further, the negative temperature coefficient sensing circuit includes power supply, start-up circuit II, negative temperature coefficient voltage generation electricity
Road and voltage follower circuit I20；The power supply is connected with the start-up circuit II and negative temperature coefficient voltage generation circuit, is used for
Power supply；The start-up circuit II is connected with the negative temperature coefficient voltage generation circuit, is negative when electric initial on the supply voltage
Temperaturecoefficient voltage generation circuit provides initial current；The voltage follower circuit I20 produces with the negative temperature coefficient voltage
Circuit is connected, and load capacity is driven for strengthening.
Further, the start-up circuit II includes the first p-type FET MP21, the second p-type FET MP22, and first
N-type FET MN21, the second N-type FET MN22 and diode D21；The negative temperature coefficient voltage generation circuit includes
3rd p-type FET MP23, the 4th p-type FET MP24, the 5th p-type FET MP25, the first triode Q21,
Two triode Q22, resistance R21 and trim electric resistance array Rtrim2；The drain electrode of the first p-type FET MP21 connects the electricity
Source, grid are connected with ground signalling, and the drain electrode with the first N-type FET MN21 and diode D21 be just respectively for source electrode
Extremely it is connected；The drain electrode of the second p-type FET MP22 connects the power supply, grid respectively with the 3rd p-type FET
MP23, the 4th p-type FET MP24 and the 5th p-type FET MP25 grid are connected, and source electrode is imitated with the second N-type field
Should pipe MN22 drain electrode be connected；The drain electrode of the first N-type FET MN21 respectively with the first p-type FET MP21
Source electrode be connected with diode D21 positive pole, grid is connected with the grid of the second N-type FET MN22, and source electrode is with connecing
Earth signal is connected；The drain electrode of the second N-type FET MN22 connects the source electrode of the second p-type FET MP22, grid
It is connected with the grid of the first N-type FET MN21, source electrode is connected with ground signalling, and drains and the direct phase in grid both ends
Even；The positive pole of the diode D21 source electrode and the first N-type FET with the first p-type FET MP21 respectively
MN21 drain electrode is connected, the negative pole source electrode with the 4th p-type FET MP24, the first triode Q21 base stages and respectively
Two triode Q22 colelctor electrode is connected；The drain electrode of the 3rd p-type FET MP23 is connected with the power supply, grid difference
It is connected with the second p-type FET MP22, the 4th p-type FET MP24, the 5th p-type FET MP25 grid,
Source electrode is connected with the colelctor electrode of the first triode Q21, and grid is joined directly together with source electrode both ends；The 4th p-type field effect
Should pipe MP24 drain electrode be connected with the power supply, grid respectively with the second p-type FET MP22, the 3rd p-type field-effect
Pipe MP23 and the 5th p-type FET MP25 grid are connected, the source electrode negative pole with the diode D21, the one or three pole respectively
Pipe Q21 base stage is connected with the second triode Q22 colelctor electrode；The drain electrode of the 5th p-type FET MP25 and the electricity
Source is connected, grid respectively with the second p-type FET MP22, the 3rd p-type FET MP23, the 4th p-type FET
MP24 grid is connected, and source electrode is just defeated with described one end for trimming electric resistance array Rtrim2 and voltage follower circuit I20 respectively
Enter end to be connected；The colelctor electrode of the first triode Q21 is connected with the source electrode of the 3rd p-type FET MP23, base stage point
It is not connected with the source electrode, diode D21 negative pole and the second triode Q22 colelctor electrode of the 4th p-type FET MP24,
Emitter stage is connected with one end of the resistance R21 and the second triode Q22 base stage respectively；The collection of the second triode Q22
The electrode source electrode, diode D21 negative pole and the first triode Q21 base stage with the 4th p-type FET MP24 respectively
It is connected, base stage is connected with described the first triode Q21 emitter stage and resistance R21 one end respectively, and emitter stage is believed with ground connection
Number be connected；One end of the resistance R21 respectively with the emitter stage of the first triode Q21 and the second triode Q22 base stage
It is connected, the other end is connected with ground signalling；Described one end for trimming electric resistance array Rtrim2 respectively with the 5th p-type field-effect
Pipe MP25 source electrode is connected with voltage follower circuit I20 positive input terminal, and the other end is connected with ground signalling.
Further, the resistance R21 and to trim electric resistance array Rtrim2 be same type resistance, and strictly match.
Further, the positive temperature coefficient temperature sensing circuit and negative temperature coefficient temperature sensing circuit trim Resistor Array Projector
Row Rtrim1 and Rtrim2 is identical structure, all including initial resistance Rint, same type matching trim resistance R, 2R, 4R, 8R,
16R and switch K1, K2, K3, K4, K5, K1, K2, K3, K4, K5 are switched one by one with described by described resistance R, 2R, 4R, 8R, 16R
After corresponding series connection, it is formed in parallel respectively with the initial resistance Rint.
The beneficial effects of the utility model are：The utility model is the optional temperature of Positive and Negative Coefficient Temperature that monolithic semiconductor integrates
Spend sensing chip, by positive temperature coefficient sensing circuit, negative temperature coefficient sensing circuit and its compensation circuit, analog to digital conversion circuit,
Serial interface circuit etc. is integrated on chip piece simultaneously, while terminal applies client can be single by serial interface circuit and storage
Output of the member to chip carries out positive temperature coefficient or negative temperature coefficient selection, and temperature coefficient is trimmed, and realizes finished product one
The application characteristic that cause property is good, measurement is accurate, highly integrated, client is easy to use.
Brief description of the drawings
Fig. 1 is the optional TEMP chi frame figure of the utility model single-chip integration Positive and Negative Coefficient Temperature；Fig. 2 is this reality
With the circuit diagram of new positive temperature coefficient temperature sensing circuit；Fig. 3 is the electricity of the utility model negative temperature coefficient TEMP electricity
Lu Tu；Fig. 4 is the structural representation that the utility model trims electric resistance array.
Embodiment
Specific embodiment of the present utility model is described in detail below in conjunction with the accompanying drawings.
As shown in figure 1, a kind of optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature includes sensing circuit, compensation electricity
Road, clock circuit, logic control circuit, analog to digital conversion circuit, serial interface circuit, selection circuit and storage element；The biography
Inductive circuit includes the positive temperature coefficient sensing circuit and negative temperature coefficient sensing circuit being connected with each other, positive temperature coefficient sensing circuit
Output voltage linear rise with the rising of temperature sensor, negative temperature coefficient sensing circuit output voltage with temperature sensor rising
And linear decline；The compensation circuit is connected with the sensing circuit, to positive temperature coefficient and negative temperature coefficient sensor circuit
The factor that process drift, voltage pulsation, internal noise, encapsulation stress etc. influence temperature sense precision is compensated or disappeared respectively
Remove；The selection circuit is connected with the sensing circuit and analog to digital conversion circuit, and analog to digital conversion circuit passes positive and negative temperature coefficient
The output of inductive circuit carries out transformation of the analog quantity to digital quantity, improves the noise resisting ability of output；The clock circuit is chip
Inside provides clock signal, is connected with the logic control circuit and analog to digital conversion circuit；The logic control circuit is chip
Inside provides logic control signal, is connected with the serial interface circuit and analog to digital conversion circuit；The serial interface circuit is defeated
Enter end to be connected with the output end of analog-digital conversion circuit as described, as chip and the communication interface of external signal, it will reflect temperature
The sensing amount of information is exported；The memory cell input is connected with the serial interface circuit, and client passes through serial interface
Two ports of mouth circuit, it would be desirable to the Positive and Negative Coefficient Temperature width that the selection signal and needs of the Positive and Negative Coefficient Temperature of output adjust
Degree is stored in the unit, and memory cell output end is connected with the selection circuit and sensing circuit respectively, realizes control choosing respectively
Circuit is selected, according to the communication signal for being stored in memory cell module, chip output positive temperature coefficient or subzero temperature are selected by user
Spend coefficient analog signal and the electric resistance array that trims in sensing circuit is trimmed, adjust chip temperature coefficient the two
Function.
Produced as shown in Fig. 2 the positive temperature coefficient sensing circuit includes power supply, start-up circuit I, positive temperature coefficient voltage
Circuit and voltage follower circuit I10；The power supply is connected with the start-up circuit I and positive temperature coefficient voltage generation circuit, uses
In power supply；The start-up circuit I is connected with the positive temperature coefficient voltage generation circuit, when electric initial on the supply voltage, is
Positive temperature coefficient voltage generation circuit provides initial current；The voltage follower circuit I10 produces with the positive temperature coefficient voltage
Raw circuit is connected, and load capacity is driven for strengthening.
The start-up circuit I includes the first p-type FET MP11, the second p-type FET MP12, the first N-type field effect
Should pipe MN11, the second N-type FET MN12 and diode D11；The positive temperature coefficient voltage generation circuit includes the 3rd p-type
FET MP13, the 4th p-type FET MP14, the 5th p-type FET MP15, the first triode Q11, the second triode
Q12, resistance R11 and trim electric resistance array Rtrim1；The drain electrode of the first p-type FET MP11 connects the power supply, source electrode
The drain electrode with the positive pole and the first N-type FET MN11 of the diode D11 is connected respectively, and grid is connected with ground signalling；
The drain electrode of the second p-type FET MP12 connects the power supply, the drain electrode phase of source electrode and the second N-type FET MN12
Even, grid is connected with the grid of the 3rd p-type FET MP13 and the 4th p-type FET MP14 grid respectively；Institute
State the first N-type FET MN11 drain electrode respectively with the source electrode and diode D11 of the first p-type FET MP11 just
Extremely it is connected, source electrode is connected with ground signalling, and grid is connected with the grid of the second N-type FET MN12；Second N-type
FET MN12 drain electrode is connected with the source electrode of the second p-type FET MP12, and source electrode is connected with ground signalling, grid
It is connected with the grid of the first N-type FET MN11, and drain electrode is directly connected to grid both ends, the first N-type field effect
Should pipe MN11 and the second N-type FET MN12 form the relation of current mirror；The positive pole of the diode D11 is respectively with described
The drain electrode of one p-type FET MP11 source electrode and the first N-type FET MN11 is connected, negative pole respectively with the 3rd p-type
FET MP13 source electrode and the first triode Q11 colelctor electrode are connected；The drain electrode of the 3rd p-type FET MP13 connects
The power supply, source electrode are connected with the negative pole of the diode D11 and the first triode Q11 colelctor electrode respectively, grid respectively with
The grid of the second p-type FET MP12 and the 4th p-type FET MP14 grid are connected；The 4th p-type field effect
Should pipe MP14 drain electrode connect the power supply, the source electrode grid and the second triode with the 5th p-type FET MP15 respectively
Q12 colelctor electrode is connected, the grid grid and the 3rd p-type FET MP13 with the second p-type FET MP12 respectively
Grid be connected, and grid and source electrode both ends are directly connected to, the second p-type FET MP12 and the 4th p-type FET
MP14 forms the relation of current mirror；The drain electrode of the 5th p-type FET MP15 connects the power supply, and source electrode is repaiied with described respectively
Adjust electric resistance array Rtrim1 one end to be connected with voltage follower circuit I10 positive input terminal, grid respectively with the 4th p-type field
Effect pipe MP14 source electrode and the second triode Q12 colelctor electrode are connected；The colelctor electrode and base stage two of the first triode Q11
End is directly connected to, and colelctor electrode is connected with the negative pole of the diode D11 and the 3rd p-type FET MP13 source electrode respectively, base
Pole is connected with the base stage of the second triode Q12, and emitter stage is connected with ground signalling；The current collection of the second triode Q12
Pole is connected with the source electrode of the 4th p-type FET MP14 and the 5th p-type FET MP15 grid respectively, base stage and institute
The base stage for stating the first triode Q11 is connected, and emitter stage is connected with one end of the resistance R11；One end of the resistance R11 and institute
The emitter stage for stating the second triode Q12 is connected, and the other end is connected with ground signalling；Described one end for trimming electric resistance array Rtrim1
It is connected respectively with the source electrode of the 5th p-type FET MP15 and voltage follower circuit I10 positive input terminal, the other end is with connecing
Earth signal is connected.
The resistance R11 and to trim electric resistance array Rtrim1 be same type resistance, and strictly match.
The start-up course of positive temperature coefficient sensing circuit：The the first p-type FET MP11 and diode of start-up circuit I
D11 is provided for the first triode Q11 when electricity is initial on supply voltage VDD and is provided initial current, when electric on supply voltage VDD
After process terminates, the 4th p-type FET MP14 provides stable bias current, the second p-type FET MP12 and the 4th p-type
FET MP14 forms the relation of current mirror, and the first N-type FET MN11 and the second N-type FET MN12 also form electricity
The relation of mirror is flowed, because the breadth length ratio of p-type FET is much smaller than the breadth length ratio of N-type FET, therefore the first N FETs
MN11 drain terminal current potential is that diode D11 anode potential is pulled down to the level close to GND, diode D11 cut-offs, so opening
Dynamic circuit departs from the main body circuit of positive temperature coefficient temperature sensing circuit, so as to complete the start-up course of the circuit.
Positive temperature coefficient voltage generation circuit part forms the main body circuit of positive temperature coefficient temperature sensing circuit.4th P
Type FET MP14 electric current is determined by following formula：
In formula, VbeQ11And VbeQ12Respectively the first triode Q11 and the second triode Q12 base stages and the positive guide of emitter stage
Be powered pressure；VTFor thermal voltage, physical quantity；IC11And IC12Respectively the first triode Q11 and the second triode Q12 colelctor electrode electricity
Flow, I in this exampleC11=IC12；IS11And IS12For the first triode Q11 and the second triode Q12 collector saturation current, the thing
Reason amount is relevant with the base-emitter junction area of triode, and the second triode Q12 base-emitter junction is set in this example
Product is N times of the first triode Q11, i.e. IS12=N*IS11。
Formula (1) can be reduced to：
4th p-type FET MP14 and the 5th p-type FET MP15 forms current mirror, therefore both drain terminal electric currents
Proportional relation：
Id(MP15)=M*Id(MP14)………………………………………………(3)
Voltage follower circuit I10 positive-negative input end is that p-type FET makes, and its input and output electric current is approximately
Zero, thus flow through trim electric resistance array Rtrim1 electric current be the 5th p-type FET MP15 drain terminals electric current.Voltage follow
The voltage of the positive input terminal of circuit I 10 is：
The voltage strengthens it and drives load capacity by the output of voltage follower circuit：
Wherein, resistance R11 and to trim electric resistance array Rtrim1 be same type resistance, and strictly match, its temperature coefficient
Cancel out each other, VTFor positive temperature coefficient voltage, therefore the output Vout of final circuit is positive temperature coefficient.
As shown in figure 3, the negative temperature coefficient sensing circuit includes power supply, start-up circuit II, the production of negative temperature coefficient voltage
Raw circuit and voltage follower circuit I20；The power supply is connected with the start-up circuit II and negative temperature coefficient voltage generation circuit,
For powering；The start-up circuit II is connected with the negative temperature coefficient voltage generation circuit, when electric initial on the supply voltage,
Initial current is provided for negative temperature coefficient voltage generation circuit；The voltage follower circuit I20 and the negative temperature coefficient voltage
Generation circuit is connected, and load capacity is driven for strengthening.
The start-up circuit II includes the first p-type FET MP21, the second p-type FET MP22, the first N-type field effect
Should pipe MN21, the second N-type FET MN22 and diode D21；The negative temperature coefficient voltage generation circuit includes the 3rd p-type
FET MP23, the 4th p-type FET MP24, the 5th p-type FET MP25, the first triode Q21, the second triode
Q22, resistance R21 and trim electric resistance array Rtrim2；The drain electrode of the first p-type FET MP21 connects the power supply, grid
It is connected with ground signalling, source electrode is connected with the drain electrode of the first N-type FET MN21 and diode D21 positive pole respectively；
The drain electrode of the second p-type FET MP22 connects the power supply, grid respectively with the 3rd p-type FET MP23,
Four p-type FET MP24 and the 5th p-type FET MP25 grid are connected, source electrode and the second N-type FET
MN22 drain electrode is connected；The source with the first p-type FET MP21 respectively that drains of the first N-type FET MN21
Pole is connected with diode D21 positive pole, and grid is connected with the grid of the second N-type FET MN22, and source electrode is believed with ground connection
Number be connected；The drain electrode of the second N-type FET MN22 meets the source electrode of the second p-type FET MP22, grid and institute
The grid for stating the first N-type FET MN21 is connected, and source electrode is connected with ground signalling, and drain electrode is joined directly together with grid both ends；
The positive pole of the diode D21 respectively with the source electrode of the first p-type FET MP21 and the first N-type FET MN21
Drain electrode is connected, negative pole source electrode, the first triode Q21 base stages and the two or three pole with the 4th p-type FET MP24 respectively
Pipe Q22 colelctor electrode is connected；The drain electrode of the 3rd p-type FET MP23 is connected with the power supply, grid respectively with it is described
Second p-type FET MP22, the 4th p-type FET MP24, the 5th p-type FET MP25 grid are connected, source electrode with
The colelctor electrode of the first triode Q21 is connected, and grid is joined directly together with source electrode both ends；The 4th p-type FET
MP24 drain electrode is connected with the power supply, grid respectively with the second p-type FET MP22, the 3rd p-type FET
MP23 and the 5th p-type FET MP25 grid are connected, the source electrode negative pole with the diode D21, the first triode respectively
Q21 base stage is connected with the second triode Q22 colelctor electrode；The drain electrode of the 5th p-type FET MP25 and the power supply
Be connected, grid respectively with the second p-type FET MP22, the 3rd p-type FET MP23, the 4th p-type FET
MP24 grid is connected, and source electrode is just defeated with described one end for trimming electric resistance array Rtrim2 and voltage follower circuit I20 respectively
Enter end to be connected；The colelctor electrode of the first triode Q21 is connected with the source electrode of the 3rd p-type FET MP23, base stage point
It is not connected with the source electrode, diode D21 negative pole and the second triode Q22 colelctor electrode of the 4th p-type FET MP24,
Emitter stage is connected with one end of the resistance R21 and the second triode Q22 base stage respectively；The collection of the second triode Q22
The electrode source electrode, diode D21 negative pole and the first triode Q21 base stage with the 4th p-type FET MP24 respectively
It is connected, base stage is connected with described the first triode Q21 emitter stage and resistance R21 one end respectively, and emitter stage is believed with ground connection
Number be connected；One end of the resistance R21 respectively with the emitter stage of the first triode Q21 and the second triode Q22 base stage
It is connected, the other end is connected with ground signalling；Described one end for trimming electric resistance array Rtrim2 respectively with the 5th p-type field-effect
Pipe MP25 source electrode is connected with voltage follower circuit I20 positive input terminal, and the other end is connected with ground signalling.
The resistance R21 and to trim electric resistance array Rtrim2 be same type resistance, and strictly match.
The start-up course of negative temperature coefficient sensing circuit：The the first p-type FET MP21 and diode of start-up circuit II
D21 provides initial current, as supply voltage VDD when electricity is initial on supply voltage VDD for the first triode Q21, resistance R21
After power up terminates, the 3rd p-type FET MP23 provides stable bias current, the second p-type FET MP22 and the
Three p-type FET MP23 form the relation of current mirror, the first N-type FET MN21 and the second N-type FET MN22
The relation of current mirror is formed, because the breadth length ratio of p-type FET is much smaller than the breadth length ratio of N-type FET, therefore the first N fields
Effect pipe MN1 drain terminal current potential is that diode D21 anode potential is pulled down to the level close to GND, and diode D21 ends,
So start-up circuit departs from the main body circuit of negative temperature coefficient temperature sensing circuit, so as to complete the start-up course of the circuit.
Negative temperature coefficient voltage generation circuit part forms the main body circuit of negative temperature coefficient temperature sensing circuit.3rd P
Type FET MP23 electric current is determined by following formula：
Wherein VbeQ22For the second triode Q22 base stages and emitter stage forward conduction voltage.
3rd p-type FET MP23 and the 5th p-type FET MP25 forms current mirror, therefore both drain terminal electric currents
Proportional relation：Id(MP25)=N*Id(MP23)……………………………………………(7)
N is the proportionality coefficient of the 5th p-type FET MP25 and the 3rd p-type FET MP23 breadth length ratio.Voltage with
Positive-negative input end with circuit I 20 is that p-type FET makes, and its input and output electric current is approximately zero, therefore flows through and trim
Electric resistance array Rtrim2 electric current is the electric current of the 5th p-type FET MP25 drain terminals.The positive input terminal of voltage follower circuit
Voltage be：
The voltage strengthens it and drives load capacity by the output of voltage follower circuit：
Wherein, resistance R21 and to trim electric resistance array Rtrim2 be same type resistance, and strictly match, its temperature coefficient
Cancel out each other, VbeQ22For negative temperature coefficient voltage, therefore the output Vout of final circuit is negative temperature coefficient.
As shown in figure 4, the positive temperature coefficient temperature sensing circuit and negative temperature coefficient temperature sensing circuit trim electricity
Hinder array Rtrim1 and Rtrim2 be identical structure, all including initial resistance Rint, same type match trim resistance R, 2R, 4R,
8R, 16R and switch K1, K2, K3, K4, K5, by described resistance R, 2R, 4R, 8R, 16R and described switch K1, K2, K3, K4, K5 mono-
After one corresponding series connection, it is formed in parallel respectively with the initial resistance Rint.
K1-K5 is switching signal, and H represents high level, represents switch conduction, and L represents low level, represents to switch off,
Rint is initial resistance, and R, 2R, 4R, 8R, 16R are that the incremental same type matching of 2 times of resistance trims resistance, therefore trim electric resistance array
All-in resistance be：
Rtrim=Rint+K1*R+K2*2R+K3*4R+K4*8R+K5*16R ... ... ... (10)
Whole circuit designs for micro energy lose, and the electric current of consumption can be neglected in temperature rise caused by chip, reduce itself circuit
Influence to temperature sensing circuit temperature test, improve the precision of temperature test.
Above is preferably implement to be illustrated to of the present utility model, but the invention is not limited to the reality
Example is applied, those skilled in the art can also make a variety of equivalent variations on the premise of without prejudice to the utility model spirit
Or replace, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (8)
- A kind of 1. optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature, it is characterised in that：Including sensing circuit, compensation electricity Road, clock circuit, logic control circuit, analog to digital conversion circuit, serial interface circuit, selection circuit and memory cell；The biography Inductive circuit includes the positive temperature coefficient sensing circuit and negative temperature coefficient sensing circuit being connected with each other, positive temperature coefficient sensing circuit Output voltage linear rise with the rising of temperature sensor, negative temperature coefficient sensing circuit output voltage with temperature sensor rising And linear decline；The compensation circuit is connected with the sensing circuit, and the factor for influenceing temperature sense precision is mended respectively Repay or eliminate；The selection circuit is connected with the sensing circuit and analog to digital conversion circuit, and analog to digital conversion circuit is by positive and negative temperature The output of coefficient sensing circuit carries out transformation of the analog quantity to digital quantity, improves the noise resisting ability of output；The clock circuit Clock signal is provided for chip internal, is connected with the logic control circuit and analog to digital conversion circuit；The logic control circuit Logic control signal is provided for chip internal, is connected with the serial interface circuit and analog to digital conversion circuit；The serial line interface The output end of circuit input end and analog-digital conversion circuit as described connects, and as chip and the communication interface of external signal, it will be anti- The sensing amount for reflecting temperature information is exported；The memory cell input is connected with the serial interface circuit, and client passes through Two ports of serial interface circuit, it would be desirable to the positive negative temperature that the selection signal and needs of the Positive and Negative Coefficient Temperature of output adjust Coefficient amplitude is stored in the unit, and memory cell output end is connected with the selection circuit and sensing circuit, realized respectively respectively Control selections circuit, according to the communication signal for being stored in memory cell module, chip is selected to export positive temperature coefficient by user Or negative temperature coefficient analog signal and sensing circuit is trimmed, adjust the temperature coefficient of chip the two functions.
- A kind of 2. optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature according to claim 1, it is characterised in that： The positive temperature coefficient sensing circuit includes power supply, start-up circuit I, positive temperature coefficient voltage generation circuit and voltage follower circuit I10；The power supply is connected with the start-up circuit I and positive temperature coefficient voltage generation circuit, for powering；The start-up circuit I is connected with the positive temperature coefficient voltage generation circuit, and when electric initial on the supply voltage, electricity is produced for positive temperature coefficient voltage Road provides initial current；The voltage follower circuit I10 is connected with the positive temperature coefficient voltage generation circuit, is driven for strengthening Dynamic load capacity.
- A kind of 3. optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature according to claim 2, it is characterised in that： The start-up circuit I include the first p-type FET MP11, the second p-type FET MP12, the first N-type FET MN11, Second N-type FET MN12 and diode D11；The positive temperature coefficient voltage generation circuit includes the 3rd p-type FET MP13, the 4th p-type FET MP14, the 5th p-type FET MP15, the first triode Q11, the second triode Q12, resistance R11 and trim electric resistance array Rtrim1；The drain electrode of the first p-type FET MP11 connects the power supply, source electrode respectively with institute The drain electrode for stating diode D11 positive pole and the first N-type FET MN11 is connected, and grid is connected with ground signalling；2nd P Type FET MP12 drain electrode connects the power supply, and source electrode is connected with the drain electrode of the second N-type FET MN12, grid point It is not connected with the grid of the 3rd p-type FET MP13 and the 4th p-type FET MP14 grid；First N-type FET MN11 drain electrode is connected with the source electrode of the first p-type FET MP11 and diode D11 positive pole respectively, source Pole is connected with ground signalling, and grid is connected with the grid of the second N-type FET MN12；The second N-type FET MN12 drain electrode is connected with the source electrode of the second p-type FET MP12, and source electrode is connected with ground signalling, grid and described the One N-type FET MN11 grid is connected, and drain electrode is directly connected to grid both ends, the first N-type FET MN11 The relation of current mirror is formed with the second N-type FET MN12；The positive pole of the diode D11 respectively with the first p-type field The drain electrode of effect pipe MP11 source electrode and the first N-type FET MN11 is connected, negative pole respectively with the 3rd p-type FET MP13 source electrode and the first triode Q11 colelctor electrode are connected；The drain electrode of the 3rd p-type FET MP13 connects the electricity Source, source electrode are connected with the negative pole of the diode D11 and the first triode Q11 colelctor electrode respectively, and grid is respectively with described Two p-type FET MP12 grid and the 4th p-type FET MP14 grid are connected；The 4th p-type FET MP14 drain electrode connects the power supply, source electrode respectively with the grid of the 5th p-type FET MP15 and the second triode Q12 Colelctor electrode is connected, grid respectively with the grid of the second p-type FET MP12 and the 3rd p-type FET MP13 grid It is connected, and grid and source electrode both ends are directly connected to, the second p-type FET MP12 and the 4th p-type FET MP14 structures Into the relation of current mirror；The drain electrode of the 5th p-type FET MP15 connects the power supply, and source electrode trims resistance with described respectively Array Rtrim1 one end is connected with voltage follower circuit I10 positive input terminal, grid respectively with the 4th p-type FET MP14 source electrode and the second triode Q12 colelctor electrode are connected；The colelctor electrode of the first triode Q11 and base stage both ends are direct Connection, colelctor electrode are connected with the negative pole of the diode D11 and the 3rd p-type FET MP13 source electrode respectively, base stage and institute The base stage for stating the second triode Q12 is connected, and emitter stage is connected with ground signalling；The colelctor electrode difference of the second triode Q12 It is connected with the source electrode of the 4th p-type FET MP14 and the 5th p-type FET MP15 grid, base stage and described first Triode Q11 base stage is connected, and emitter stage is connected with one end of the resistance R11；One end of the resistance R11 and described second Triode Q12 emitter stage is connected, and the other end is connected with ground signalling；Described one end for trimming electric resistance array Rtrim1 respectively with The source electrode of the 5th p-type FET MP15 is connected with voltage follower circuit I10 positive input terminal, the other end and ground signalling It is connected.
- A kind of 4. optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature according to claim 3, it is characterised in that： The resistance R11 and to trim electric resistance array Rtrim1 be same type resistance, and strictly match.
- A kind of 5. optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature according to claim 1, it is characterised in that： The negative temperature coefficient sensing circuit includes power supply, start-up circuit II, negative temperature coefficient voltage generation circuit and voltage follow electricity Road I20；The power supply is connected with the start-up circuit II and negative temperature coefficient voltage generation circuit, for powering；The startup Circuit II is connected with the negative temperature coefficient voltage generation circuit, is negative temperature coefficient voltage when electric initial on the supply voltage Generation circuit provides initial current；The voltage follower circuit I20 is connected with the negative temperature coefficient voltage generation circuit, is used for Enhancing driving load capacity.
- A kind of 6. optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature according to claim 5, it is characterised in that： The start-up circuit II includes the first p-type FET MP21, the second p-type FET MP22, the first N-type FET MN21, the second N-type FET MN22 and diode D21；The negative temperature coefficient voltage generation circuit is imitated including the 3rd p-type field Should pipe MP23, the 4th p-type FET MP24, the 5th p-type FET MP25, the first triode Q21, the second triode Q22, Resistance R21 and trim electric resistance array Rtrim2；The drain electrode of the first p-type FET MP21 connects the power supply, and grid is with connecing Earth signal is connected, and source electrode is connected with the drain electrode of the first N-type FET MN21 and diode D21 positive pole respectively；It is described Second p-type FET MP22 drain electrode connects the power supply, grid respectively with the 3rd p-type FET MP23, the 4th p-type FET MP24 and the 5th p-type FET MP25 grid are connected, the leakage of source electrode and the second N-type FET MN22 Extremely it is connected；The drain source electrode with the first p-type FET MP21 and two poles respectively of the first N-type FET MN21 Pipe D21 positive pole is connected, and grid is connected with the grid of the second N-type FET MN22, and source electrode is connected with ground signalling；Institute The drain electrode for stating the second N-type FET MN22 connects the source electrode of the second p-type FET MP22, grid and first N-type FET MN21 grid is connected, and source electrode is connected with ground signalling, and drain electrode is joined directly together with grid both ends；The diode Drain electrode of the D21 positive pole respectively with the source electrode and the first N-type FET MN21 of the first p-type FET MP21 is connected, The negative pole source electrode with the 4th p-type FET MP24, the first triode Q21 base stages and the second triode Q22 respectively collection Electrode is connected；The drain electrode of the 3rd p-type FET MP23 is connected with the power supply, grid respectively with the second p-type field Effect pipe MP22, the 4th p-type FET MP24, the 5th p-type FET MP25 grid are connected, source electrode and the described 1st Pole pipe Q21 colelctor electrode is connected, and grid is joined directly together with source electrode both ends；The drain electrode of the 4th p-type FET MP24 with The power supply is connected, grid respectively with the second p-type FET MP22, the 3rd p-type FET MP23 and the 5th p-type field Effect pipe MP25 grid is connected, the source electrode negative pole with the diode D21, the first triode Q21 base stage and second respectively Triode Q22 colelctor electrode is connected；The drain electrode of the 5th p-type FET MP25 is connected with the power supply, grid respectively with The second p-type FET MP22, the 3rd p-type FET MP23, the 4th p-type FET MP24 grid are connected, source Positive input terminal of the pole respectively with described one end for trimming electric resistance array Rtrim2 and voltage follower circuit I20 is connected；Described first Triode Q21 colelctor electrode is connected with the source electrode of the 3rd p-type FET MP23, base stage respectively with the 4th p-type field The colelctor electrode of effect pipe MP24 source electrode, diode D21 negative pole and the second triode Q22 is connected, emitter stage respectively with it is described Resistance R21 one end is connected with the second triode Q22 base stage；The colelctor electrode of the second triode Q22 is respectively with described The base stage of four p-type FET MP24 source electrode, diode D21 negative pole and the first triode Q21 is connected, base stage respectively with institute The the first triode Q21 stated emitter stage is connected with resistance R21 one end, and emitter stage is connected with ground signalling；The resistance R21 One end be connected respectively with the emitter stage of the first triode Q21 and the second triode Q22 base stage, the other end with ground connection believe Number be connected；Described one end for trimming electric resistance array Rtrim2 source electrode and voltage with the 5th p-type FET MP25 respectively The positive input terminal of circuit I 20 is followed to be connected, the other end is connected with ground signalling.
- A kind of 7. optional TEMP chip of single-chip integration Positive and Negative Coefficient Temperature according to claim 6, it is characterised in that： The resistance R21 and to trim electric resistance array Rtrim2 be same type resistance, and strictly match.
- 8. the optional TEMP chip of a kind of single-chip integration Positive and Negative Coefficient Temperature according to claim 3 or 6, its feature exist In：The positive temperature coefficient temperature sensing circuit and negative temperature coefficient temperature sensing circuit trim electric resistance array Rtrim1 and Rtrim2 is identical structure, all including initial resistance Rint, same type matching trim resistance R, 2R, 4R, 8R, 16R and switch K1, K2, K3, K4, K5, corresponded by described resistance R, 2R, 4R, 8R, 16R and described switch K1, K2, K3, K4, K5 after connecting, point It is not formed in parallel with the initial resistance Rint.
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