CN206863435U - A kind of array base palte and display device - Google Patents

Abstract

The utility model provides a kind of array base palte and display device, is related to display technology field, and the achievable cut-out of cabling between IC and Panel with overlapping again.The array base palte includes viewing area and wiring region, and the wiring region includes multiple electrical testing areas, and the electrical testing area includes the first signal line leads and the secondary signal line lead being set up in parallel；The secondary signal line lead includes the first subsignal line lead and the second subsignal line lead mutually disconnected；Wherein, one end of first signal line leads and one end of the first subsignal line lead are connected with first port；One end of the other end of first signal line leads and the second subsignal line lead is connected with second port；The first subsignal line lead and the second subsignal line lead can be by connecting, to turn on the first port and the second port after welding.For electrical testing area.

Description

A kind of array base palte and display device

Technical field

It the utility model is related to display technology field, more particularly to a kind of array base palte and display device.

Background technology

At present, as the fast development of Display Technique, lightening display product are increasingly liked by consumer.For Meet the lightening requirement of product, this requires the integrated level more and more higher of interiors of products, in the prior art often using integrated The driving IC of power module (power modules) or time-sequence control module (TimingController, abbreviation T-CON module) (Drive Integrated Circuit, integrated circuit), driving IC for example can be source drive IC (Source Drive IC) (Flexible Printed Circuit Assembly, weld or be assembled with the flexible circuitry of component to reduce FPCA Plate) area and thickness, show overall lightening of product to realize.

However, the integrated level more and more higher due to driving IC, after external circuit is fewer and fewer, out-of-the way position when occurring bad Just it is increasingly difficult to position.For example, when driving the voltage of the generation of the power module inside IC to have abnormal, with 10.1WU products Exemplified by, voltage and GOA (Gate Driver on Array, the driving of array base palte row) waveform are respectively such as Fig. 1 (a) and Fig. 1 (b) It is shown, because the signal such as CLK (Clock, clock signal) and STV (Start Vertical, grid line initial signal) can pass through battle array Signal line leads on row substrate are by IC input display panels, such as the GOA regions of display panel, therefore now voltage is different Often it is probably that IC internal abnormalities cause, it is also possible to which Panel (display panel) internal abnormality causes.In the prior art, such as Fig. 2 (a) shown in, array base palte includes wiring region 1 and viewing area 2, and wiring region 1 is provided with multiple (Electrical of electrical testing area 11 Test Pad, abbreviation ET Pad area), generally electrical testing area 11 is detected to determine that out-of-the way position is being occurred in IC12 Inside inside, or Panel.As shown in Fig. 2 (b) and Fig. 2 (c), electrical testing area 11 includes the signal wire being cascading Lead 10, flatness layer 20 and conductive layer 30, conductive layer 30 are connected by the via 201 on flatness layer 20 with signal line leads 10. If not cutting off the signal line leads 10 connected between IC12 and Panel in detection, need to exclude correlation one by one, so as to meeting pole Big extension analysis time, reduce analyzing efficiency；If the signal line leads 10 connected between IC12 and Panel are cut off, after cut-out When being judged as that panel's is bad, because signal can not be inputed to Panel by IC12, thus subsequent analysis can be impacted, increased Bonus point analyses difficulty.

Utility model content

Embodiment of the present utility model provides a kind of array base palte and display device, can be achieved to walk between IC and display panel The cut-out of line with overlapping again.

To reach above-mentioned purpose, embodiment of the present utility model adopts the following technical scheme that：

On the one hand, there is provided a kind of array base palte includes viewing area and wiring region, and the wiring region includes multiple electrical testings Area, the electrical testing area include the first signal line leads and the secondary signal line lead being set up in parallel；The secondary signal line Lead includes the first subsignal line lead and the second subsignal line lead mutually disconnected；Wherein, first signal line leads One end and one end of the first subsignal line lead be connected with the first port of the viewing area；First signal wire One end of the other end of lead and the second subsignal line lead is connected with second port；The first subsignal line lead Can be by being connected after welding, to turn on the first port and the second port with the second subsignal line lead.

Preferably, the electrical testing area also includes：Insulating barrier, the insulating barrier at least cover the first subsignal line Between lead, the second subsignal line lead and the first subsignal line lead and the second subsignal line lead Interstitial site；Metal level on the insulating layer is set, along perpendicular to the direction of the metal level, the first subsignal line lead There is overlapping region with the second subsignal line lead and the metal level；The flatness layer being successively set on the metal level And conductive layer；The conductive layer is connected through the via on the flatness layer with the metal level, and the conductive layer also extends through Via is connected with first signal line leads.

Preferably, the conductive layer is including the first conductive pattern above the first subsignal line and positioned at described The second conductive pattern above second subsignal line, first conductive pattern and second conductive pattern mutually disconnect；Edge Perpendicular to the direction of the conductive layer, the gap side between the first subsignal line lead and the second subsignal line lead Boundary is in the dwell boundaries between first conductive pattern and second conductive pattern.

Preferably, the insulating barrier is located at the region hollow out of the first signal line leads face.

Preferably, the first subsignal line lead and the second subsignal line lead draw with first signal wire Line connects with layer.

It is further preferred that the conductive layer includes the first conductive pattern above the first subsignal line, position The second conductive pattern above the second subsignal line and the 3rd conductive pattern above first signal line leads Case；First conductive pattern and second conductive pattern are connected with the 3rd conductive pattern with layer.

Preferably, the conductive layer also includes the 3rd conductive pattern above first signal line leads；It is described First conductive pattern and second conductive pattern are not connected to the 3rd conductive pattern；The first subsignal line lead It is not connected to the second subsignal line lead with first signal line leads.

Preferably, the array base palte also includes thin film transistor (TFT), and the thin film transistor (TFT) includes source electrode, drain electrode, active Layer, grid and gate insulation layer；The signal line layer is with the source electrode and the drain electrode with the same material of layer, the metal level and institute Grid is stated with the same material of layer；Or the signal line layer and the grid be with the same material of layer, the metal level and the source electrode and The drain electrode is the same as the same material of layer.

Preferably, the signal line leads are data cable lead wire or grid line lead.

On the other hand, there is provided a kind of display device, including above-mentioned array base palte.

The utility model embodiment provides a kind of array base palte and display device, if first port is a driving IC end Mouthful, second port is an end of viewing area signal wire, when array base palte occurs bad, it is necessary to position bad by driving inside IC When causing still inside display panel to cause, due to the first subsignal line lead and the second subsignal in secondary signal line lead Line lead mutually disconnects, if the first signal line leads are cut off so that the cabling cut-out between driving IC and display panel, thus Can be to realize the cut-out of signal between driving IC and display panel, so as to quickly judge that bad led by IC internal abnormalities Cause, or caused by bad inside display panel.When being defined as bad inside display panel, still need to carry out electrical testing area Detect driving IC and display panel conducting or still need to, can be by being welded to connect the first subsignal line lead and the second subsignal Line lead so that secondary signal line lead turns on, and so drives the cabling between IC and display panel to turn on, thus drives on IC Signal can transmit to display panel, in order to subsequently continue to detect to bad, thus this practical embodiment provide Array base palte structure can realize driving IC and display panel between cabling cut-out with overlapping again.

Brief description of the drawings

, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only It is some embodiments of the utility model, for those of ordinary skill in the art, is not paying the premise of creative work Under, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 (a) is the waveform diagram of electric voltage exception on a kind of array base palte of prior art offer；

Fig. 1 (b) is the waveform diagram of GOA abnormal signals on a kind of array base palte of prior art offer；

Fig. 2 (a) is the structural representation that a kind of array base palte that prior art provides is divided into viewing area and wiring region；

Fig. 2 (b) is the enlarged diagram at C in Fig. 2 (a) that prior art provides；

Fig. 2 (c) be in Fig. 2 (b) AA ' into schematic cross-sectional view or Fig. 3 EE ' to schematic cross-sectional view；

Fig. 3 is the enlarged diagram at C in Fig. 2 (a) that the utility model embodiment provides；

Fig. 4 (a) is the structural representation one for the signal line layer that the utility model embodiment provides；

Fig. 4 (b) is the structural representation two for the signal line layer that the utility model embodiment provides；

Fig. 5 (a) be in Fig. 3 DD ' to schematic cross-sectional view one；

Fig. 5 (b) be in Fig. 3 DD ' to schematic cross-sectional view two；

Fig. 5 (c) be in Fig. 3 EE ' to schematic cross-sectional view；

Fig. 6 (a) be in Fig. 3 BB ' to schematic cross-sectional view one；

Fig. 6 (b) be in Fig. 3 BB ' to schematic cross-sectional view two；

Fig. 6 (c) be in Fig. 3 BB ' to schematic cross-sectional view three；

Fig. 6 (d) be in Fig. 3 BB ' to schematic cross-sectional view four；

Fig. 7 (a) is the structural representation one of the signal line layer that the utility model embodiment provides and conductive layer；

Fig. 7 (b) is the structural representation two of the signal line layer that the utility model embodiment provides and conductive layer；

Fig. 7 (c) is the structural representation three of the signal line layer that the utility model embodiment provides and conductive layer；

Fig. 7 (d) is the structural representation four of the signal line layer that the utility model embodiment provides and conductive layer；

Fig. 7 (e) is the structural representation five of the signal line layer that the utility model embodiment provides and conductive layer；

Fig. 8 (a) be in Fig. 3 BB ' to schematic cross-sectional view five；

Fig. 8 (b) be in Fig. 3 TT ' to schematic cross-sectional view.

Reference：

1- wiring regions；2- viewing areas；10- signal line leads；The signal line leads of 101- first；102- secondary signal lines draw Line；1021- the first subsignal line leads；1022- the second subsignal line leads；11- electrical testings area；12-IC；20- flatness layers； Via on 201- flatness layers；30- conductive layers；The conductive patterns of 301- first；The conductive patterns of 302- second；The conductive patterns of 303- the 3rd Case；40- insulating barriers；Via on 401- insulating barriers；50- metal levels.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made The every other embodiment obtained, belong to the scope of the utility model protection.

The utility model embodiment provides a kind of array base palte, as shown in Fig. 2 (a), including viewing area 2 and wiring region 1, cloth Line area 1 includes multiple electrical testing areas 11, and as shown in Fig. 3-Fig. 7, electrical testing area 11 includes the first signal wire being set up in parallel Lead 101 and secondary signal line lead 101；Secondary signal line lead 102 includes the first subsignal line lead mutually disconnected 1021 and the second subsignal line lead 1022.Wherein, one end of the first signal line leads 101 and the first subsignal line lead 1021 One end be connected with first port；One end of the other end of first signal line leads 101 and the second subsignal line lead 1022 It is connected with second port.First subsignal line lead 1021 and the second subsignal line lead 1022 can pass through welding (welding) connect afterwards, to turn on first port and second port.

It should be noted that first, can be the first subsignal line lead 1021 and the second subsignal as shown in Fig. 4 (a) Line lead 1022 is not directly connected with the first signal line leads 101；Can also be as shown in Fig. 4 (b), the first subsignal line draws The subsignal line lead 1022 of line 1021 and second is connected with the first signal line leads 101 with layer, i.e. the first subsignal line lead 1021 and second subsignal line lead 1022 be directly connected to the first signal line leads 101, not by other connecting portions；Certainly It is also possible that any one in the first subsignal line lead 1021 and the second subsignal line lead 1022 and the first signal line leads 101 connect (the utility model embodiment accompanying drawing does not illustrate) with layer.

Second, for first port and second port without limiting, example, first port can be driving IC12 A port, second port can be an ends of viewing area signal wire.When first port to drive IC12 a port, the Two-port netwerk for one of signal wire end when, because one end of the first signal line leads 101 is connected with first port, the other end and Second port is connected, thus drives the signal on IC12 to be inputted by the first signal line leads 101 to display panel, Such as input to the GOA regions of display panel.A port of the utility model embodiment using first port as driving IC12, the Two-port netwerk is to be illustrated exemplified by one of viewing area signal wire holds.

On this basis, for how to detect the signal in the first signal line leads 101 and secondary signal line lead 102 not It is defined, such as electrical testing area 11 may be gone back in addition to including the first signal line leads 101 and secondary signal line lead 102 It is easy to detect so that the signal in signal line leads to be exported including other film layers such as conductive layer.When needing to first port and second When signal between port is detected, the signal in the first signal line leads 101 can be detected, so as to realize Pass through ET during Single cell (IC and FPC (flexible printed circuit, and flexible print circuit) are unbound) Jig feed signal detected and LCD states under (IC and FPC have been bound) carry out signal testing effect.No matter display surface Plate is Single cell states or LCD states, and the first signal line leads 101 in electrical testing area 11 are conductings, and existing Have that structure is identical, thus do not interfere with any test or signal conduction, can be achieved to act on existing structure identical.

3rd, because the first subsignal line lead 1021 and second that secondary signal line lead 102 includes mutually disconnecting is sub Signal line leads 1022, thus the signal in first port can not be inputted by secondary signal line lead 102 to second port, or Signal in person's second port can not be inputted to first port by secondary signal line lead 102.When the first subsignal line 1021 After being welded to connect with the second subsignal line lead 1022, first port and second port conducting, therefore now in first port Signal can pass through secondary signal by the signal that secondary signal line lead 102 is inputted to second port, or second port Line lead 102 is inputted to first port.

In addition, how to be welded to connect without limit for the first subsignal line 1021 and the second subsignal line lead 1022 Fixed, the first subsignal line 1021 and the second subsignal line lead 1022 can be with being directly welded to connect, can also be by the first subsignal The subsignal line lead 1022 of line 1021 and second is welded to connect with connecting portion respectively, and then by connecting portion by the first subsignal line 1021 and second subsignal line lead 1022 connect.

4th, because the first subsignal line lead 1021 and second that secondary signal line lead 102 includes mutually disconnecting is sub Signal line leads 1022, thus when needing the signal cut between first port and second port, the first signal only need to be cut off Line lead 101.Specifically, for the first signal line leads 101 off-position without limit, as long as cut-out first letter After number line lead 101, the signal between first port and second port can be cut off.

5th, the cut-out of the first signal line leads 101 and the first subsignal line lead 1021 and the second subsignal line are drawn Connection can be realized by way of adjusting laser energy size after the welding of line 1022.

The utility model embodiment provides a kind of array base palte, due to secondary signal line lead include mutually disconnecting first Subsignal line lead 1021 and the second subsignal line lead 1022, if thus cutting off the first signal line leads 101, first end Signal cut between mouth and second port., can will when needing signal conduction between first port and second port First subsignal line lead 1021 and the second subsignal line lead 1022 are welded to connect.If first port is a driving IC end Mouthful, when second port is an end of viewing area signal wire, when array base palte occurs bad, it is necessary to position bad by driving IC12 When inside causes still inside display panel to cause, due to the first subsignal line lead 1021 in secondary signal line lead 102 Mutually disconnected with the second subsignal line lead 1022, if the first signal line leads 101 are cut off so that driving IC12 and display surface Cabling cut-out between plate, thus can be to realize the cut-out of signal between driving IC12 and display panel, so as to quick Judge that bad caused by IC12 internal abnormalities, or caused by bad inside display panel.When being defined as inside display panel When bad, still need to that electrical testing area 11 is detected or still needed to by driving IC12 and display panel conducting, welding can be passed through Connect the first subsignal line lead 1021 and the second subsignal line lead 1022 so that secondary signal line lead 102 turns on, so Cabling between driving IC12 and display panel turns on, thus drives the signal on IC12 to transmit to display panel, with It is easy to subsequently continue to detect to bad, therefore the structure of the array base palte of this practical embodiment offer can realize driving The cut-out of cabling with overlapping again between IC12 and display panel.

Preferably, as shown in fig. 3 to 7, electrical testing area 11 also includes：Insulating barrier 40, insulating barrier 40 at least cover the first son Signal line leads 1021, the second subsignal line lead 1022 and the first subsignal line lead 1021 and the second subsignal line lead Interstitial site between 1022.The metal level 50 being arranged on insulating barrier 40, along perpendicular to the direction of metal level 50, the first son letter The subsignal line lead 1022 of number line lead 1021 and second has overlapping region with metal level 50.It is successively set on metal level 50 Flatness layer 20 and the conductive layer 30 positioned at electrical testing area 11；Conductive layer 30 passes through the via 201 and metal on flatness layer 20 Layer 50 is connected, and conductive layer 30 also extends through via and is connected with the first signal line leads 101.

Wherein, insulating barrier 40 can be as shown in Fig. 5 (a) and Fig. 6, the first subsignal line lead of covering the 1021, second son letter Interstitial site number between the subsignal line lead 1021 of line lead 1022 and first and the second subsignal line lead 1022, does not cover The first signal line leads of lid 101, now conductive layer 30 is through the via 201 and the phase of the first signal line leads 101 on flatness layer 20 Connection；Insulating barrier 40 can also be the covering electrical testing area 11 as shown in Fig. 5 (b) and Fig. 5 (c), and now conductive layer 30 passes through flat The via 401 on via 201 and insulating barrier 40 on smooth layer 20 is connected with the first signal line leads 101.Herein, insulating barrier is worked as 40 when not covering the first signal line leads 101, in Fig. 3 EE ' to schematic cross-sectional view such as Fig. 2 (c) shown in, when insulating barrier 40 covers During the first signal line leads 101, in Fig. 3 EE ' to schematic cross-sectional view such as Fig. 5 (c) shown in.

Wherein, for insulating barrier 40 material without limiting, such as can be silicon nitride (SiN_x), silica (SiO_x) Or silicon oxynitride (SiO_xN_y) etc..

The utility model embodiment accompanying drawing 5 (a) and accompanying drawing 5 (b) are with the first subsignal line lead 1021 and the first signal Line lead 101 is illustrated exemplified by being connected with layer.

Herein, along perpendicular to the direction of metal level 50, the first subsignal line lead 1021 and the second subsignal line lead 1022 have overlapping region with metal level 50, can be along perpendicular to the direction of metal level 50, metal level 50 and of part first Signal line leads 1021 and/or part the second subsignal line lead 1022 have overlapping region or along perpendicular to metals The direction of layer 50, metal level 50 cover the first subsignal line lead 1021, the second subsignal line lead 1022 and the first son letter Interstitial site between number subsignal line lead 1022 of line lead 1021 and second.

It should be noted that conductive layer 30 is connected through via with the first signal line leads 101, thus when the first signal When line lead 101 turns on, conductive layer 30 can be detected to reach the mesh of signal in the first signal line leads 101 of detection 's；When the first subsignal line lead 1021 and the second subsignal line lead 1022 are turned on by metal level 50, due to conductive layer 30 are connected through via with metal level 50, thus conductive layer 30 can be detected to reach detection secondary signal line lead The purpose of signal on 102.

On this basis, for conductive layer 30 material without limiting, such as can be tin indium oxide (Indium Tin At least one of Oxide, abbreviation ITO) or indium zinc oxide (Indium Zinc Oxide, abbreviation IZO).

Conductive layer 30 is located at part on the first subsignal line lead 1021 and conductive layer 30 is located at the second subsignal line and drawn Part on line 1022, mutually disconnect or such as Fig. 6 (b) be It is connected with each other.

Based on this, when conductive layer 30 is located at part on the first subsignal line lead 1021 and conductive layer 30 positioned at the second son Part in signal line leads 1022 mutually disconnects, and the part that conductive layer 30 is located on the first subsignal line lead 1021 is First conductive pattern 301, the part that conductive layer 30 is located on the second subsignal line lead 1022 are the second conductive pattern 302.This When can be as shown in Fig. 6 (a), along perpendicular to the direction of conductive layer 30, the first subsignal line cabling 1021 and the second subsignal Dwell boundaries between line cabling 1022 are in the dwell boundaries between the first conductive pattern 301 and the second conductive pattern 302； Can also be as shown in Fig. 6 (c), along perpendicular to the direction of conductive layer 30, the first subsignal line cabling 1021 and the second subsignal Dwell boundaries between line cabling 1022 are overlapping with the dwell boundaries between the first conductive pattern 301 and the second conductive pattern 302； Certainly can also be as shown in Fig. 6 (d), the dwell boundaries between the first conductive pattern 301 and the second conductive pattern 302 are positioned at the In dwell boundaries between one subsignal line cabling 1021 and the second subsignal line cabling 1022.

On this basis, the part that conductive layer 30 is located in the first signal line leads 101 is the 3rd conductive pattern 303, can To be as shown in Fig. 7 (a), along the width of the first signal line leads 101, the first conductive pattern 301, the second conductive pattern 302 and the 3rd conductive pattern 303 be not connected to；Can also be the first conductive pattern 301, the as shown in Fig. 7 (b) and Fig. 7 (e) Two conductive patterns 302 connect with the 3rd conductive pattern 303 with layer；It can certainly be the first conductive pattern as shown in Fig. 7 (c) Any one in the conductive pattern 302 of case 301 and second is connected with the 3rd conductive pattern 303 with layer.

With the first subsignal line lead 1021 and the second son in the utility model Figure of description 7 (a), 7 (b) and 7 (c) Signal line leads 1022 are illustrated exemplified by being not connected to the first signal line leads 101.

Based on above-mentioned, a port using first port as driving IC12, second port is one of viewing area signal wire Exemplified by end, if array base palte occur it is bad, when the first subsignal line lead 1021 and the second subsignal line lead 1022 are with the One signal line leads 101 connect with layer, and/or, the first conductive pattern 301 and the second conductive pattern 302 with the 3rd conductive pattern When case 303 connects with layer, only cut-out and the gap digit of the first subsignal line lead 1021 and the second subsignal line lead 1022 The first signal line leads 101 and the 3rd conductive pattern 303 (position F in such as Fig. 7 (b)) of place's face are put, driving could be cut off Cabling between IC12 and display panel, realize the cut-out of signal between driving IC12 and display panel.As shown in Fig. 7 (a), when First subsignal line lead 1021 and the second subsignal line lead 1022 are not connected to the first signal line leads 101, and first When the conductive pattern 302 of conductive pattern 301 and second is not connected to the 3rd conductive pattern 303, the first signal is now cut off simultaneously Any position on the conductive pattern 303 of line lead 101 and the 3rd, can cut the cabling between driving IC12 and display panel It is disconnected, realize the cut-out of signal between driving IC and display panel.As shown in Fig. 7 (c), when the second subsignal line lead 1022 and One signal line leads 101 are not connected to, and the second conductive pattern 302 is not connected to the 3rd conductive pattern 303, now cut off the first son The He of the first signal line leads 101 of face at interstitial site between the subsignal line lead 1022 of signal line leads 1021 and second 3rd conductive pattern 303, or the first signal line leads 101 and the 3rd of the cut-out face of the second subsignal line lead 1022 are conductive Pattern 303 (position G in such as Fig. 7 (c)) can cut off the cabling between driving IC12 and display panel, realize driving IC12 The cut-out of signal between display panel.Similarly, when the first subsignal line lead 1021 does not connect with the first signal line leads 101 Connect, and the first conductive pattern 301 is not connected to the 3rd conductive pattern 303, same as described above, here is omitted.Such as Fig. 7 (d) It is shown, when the first subsignal line lead 1021 is not connected to the first signal line leads 101, and the second conductive pattern 302 and the 3rd When conductive pattern 303 is not connected to, only cut off between the first subsignal line lead 1021 and the second subsignal line lead 1022 The first signal line leads 101 and the 3rd conductive pattern 303 of face at the disposal of gap, could will driving IC12 and display panel it Between cabling cut-out, realize driving IC12 and display panel between signal cut-out.When the second subsignal line lead 1022 and One signal line leads 101 are not connected to, and when the first conductive pattern 301 and the 3rd conductive pattern 303 are not connected to, it is same as described above, Here is omitted.

After the first signal line leads of cut-out 101 and conductive layer 30 above it, for the ease of subsequently continuing to detect, The signal on IC12 can will now be driven when inputting by secondary signal line lead 102 to display panel, such as Fig. 8 (a) and Fig. 8 (b) shown in, the first subsignal line 1021 need to only be turned on metal level 50, the second subsignal line lead 1022 is led with metal level 50 Logical (as shown in position M in Fig. 8 (a) and Fig. 8 (b)), now equivalent to the first subsignal line lead 1021 and the second son Signal line leads 1022 turn on, thus can realize the conducting of signal between driving IC12 and display panel, so as to continue Electrical testing area 11 is detected.

Herein, laser can be utilized to cut off the first signal line leads 101 and the conductive layer 30 above it, can also utilized Laser welds to the first subsignal line 1021 with metal level 50, to switch it on, and using laser to the second subsignal line Lead 1022 and metal level 50 are welded, to switch it on.On this basis, it can utilize laser microscope adjustment is different to swash Light energy size, electrical testing area 11 can be amplified in the case where showing mirror, and by the color distortion of diverse location film layer come Confirm the area size of cutting or welding, at the same time the size of Laser Focusing and energy size also can synchronous adjustment so as to realizing The cut-out or welding of film layer.Herein, the color distortion of diverse location film layer is due to the quantity and thickness of film layer in electrical testing area The difference of degree, and make it that the light transmittance of light is different with optical filtering situation, thus different face can be presented in diverse location from naked eyes Color.

The utility model embodiment, connected when needing the first subsignal line lead 1021 and the second subsignal line lead 1022 During turning on first port and second port, the first subsignal line lead 1021 and the second subsignal line can be drawn by welding Line 1022 is connected with metal level 50, so that secondary signal line lead 102 turns on, the signal in such first port just can The signal inputted by secondary signal line lead 102 to second port, or second port just can be drawn by secondary signal line Line 102 is inputted to first port.When first port is driving IC a port, second port is one of viewing area signal wire During end, secondary signal line lead 102 turns on, that is, drives the cabling between IC12 and display panel to turn on, thus drives on IC12 Signal can transmit to display panel, in order to subsequently continue to detect to bad.

Preferably, as shown in Fig. 6 (a), conductive layer 30 includes the first conductive pattern positioned at the top of the first subsignal line 1021 Case 301 and the second conductive pattern 302 above the second subsignal line 1022, the first conductive pattern 301 and the second conductive pattern Case 302 mutually disconnects；Along perpendicular to the direction of conductive layer 30, the first subsignal line lead 1021 and the second subsignal line lead Dwell boundaries between 1022 are in the dwell boundaries between the first conductive pattern 301 and the second conductive pattern 302.

Wherein, when needing secondary signal line cabling 102 to turn on, can be welded to being welded at the position N in Fig. 6 (a) After connecing as shown in Fig. 8 (a).

The utility model embodiment, due between the first subsignal line lead 1021 and the second subsignal line lead 1022 Dwell boundaries are in the dwell boundaries between the first conductive pattern 301 and the second conductive pattern 302, thus can be with welding The metal level 50 of face in the gap between the first conductive pattern 301 and the second conductive pattern 302 is set to draw with the first signal wire Line 1021 and secondary signal line lead 1022 turn on.Due to the gap between the first conductive pattern 301 and the second conductive pattern 302 Conductive layer 30 is not provided with border, thus on the one hand can avoid damage to conductive layer 30 in welding, on the other hand, can be kept away Exempt from the loss of energy of conductive layer 30.

Preferably, as shown in Fig. 2 (c), Fig. 5 (a) and Fig. 8 (b), insulating barrier 40 is being located at the first signal line leads 101 just To region hollow out.

Herein, when insulating barrier 40 is located at the region hollow out of the face of the first signal line leads 101, now 30 need of conductive layer are worn The via 201 crossed on flatness layer 20 can be to be connected with the first signal line leads 101.

The utility model embodiment, because insulating barrier 40 is located at the hollow out of the face of the first signal line leads 101, thus work as When needing the conductive layer 30 to be connected with the first signal line leads 101, only via need to be formed on flatness layer 20, can be so that conductive Layer 30 is connected with the first signal line leads 101, if there is insulating barrier 40 in the first signal line leads 101, need to also insulate Via is formed on layer 40, conductive layer 30 could be so connected with the first signal line leads 101, so as to cause array base palte Complex manufacturing technology, thus the utility model example, make the hollow out of insulating barrier 40 with the region of the face of the first signal line leads 101, So as to simplify the manufacture craft of array base palte.

Preferably, as shown in Fig. 4 (b), Fig. 5, Fig. 7 (e) and Fig. 8 (b), the first subsignal line lead 1021 and the second son Signal line leads 1022 are connected with layer with the first signal line leads 101 and (refer to same layer to be directly connected to).

The utility model embodiment, the first subsignal line lead 1021 and the second subsignal line lead 1022 are believed with first Number line lead 101 connects with floor, on the one hand, can simplify the manufacture craft of signal line leads；On the other hand, due to the first signal Line lead 101 and secondary signal line lead 102 are that the signal on same port is passed into another port, thus the first subsignal The subsignal line lead 1022 of line lead 1021 and second is connected with the first signal line leads 101 with layer, can increase signal wire The width of lead, prevent that signal line leads are too thin and are easily broken off.

It is further preferred that as shown in Fig. 7 (e), conductive layer 30 includes first positioned at the top of the first subsignal line 1021 Conductive pattern 301, the second conductive pattern 302 above the second subsignal line 1022 and positioned at the first signal line leads 101 3rd conductive pattern 303 of top；First conductive pattern 301 and the second conductive pattern 302 with 303 same layer of the 3rd conductive pattern Connection.

The utility model embodiment, because the first subsignal line lead 1021 and the second subsignal line lead 1022 are with One signal line leads 101 with layer connect, and the first conductive pattern 301 and the second conductive pattern 302 with the 3rd conductive pattern 303 Connected with layer, thus can both increase the width of signal line leads, can detected again in the optional position on conductive layer 30 Signal.

Preferably, as shown in Fig. 7 (a), conductive layer 30 also includes the 3rd conduction positioned at the top of the first signal line leads 101 Pattern 303；First conductive pattern 301 and the second conductive pattern 302 are not connected to the 3rd conductive pattern 303；First subsignal The subsignal line lead 1022 of line lead 1021 and second is not connected to the first signal line leads 101.

Herein, the first subsignal line lead 1021 and the second subsignal line lead 1022 with the first signal line leads 101 It is not connected to refer to the first subsignal line lead 1021 and the second subsignal line lead 1022 with the first signal line leads 101 not It is directly connected to.

The utility model embodiment, due to the first conductive pattern 301 and the second conductive pattern 302 with the 3rd conductive pattern 303 are not connected to, and the first subsignal line lead 1021 and the second subsignal line lead 1022 with the first signal line leads 101 not Connection, thus the first signal line leads 101 for cutting off optional position can drive IC12 with the conductive layer 30 above it with cut-out Cabling between display panel, so as to reduce the difficulty in array base palte detection process.

Preferably, array base palte also includes thin film transistor (TFT), thin film transistor (TFT) include source electrode, drain electrode, active layer, grid with And gate insulation layer；Signal line layer is with source electrode and drain electrode with the same material of layer, and metal level 50 is with grid with the same material of layer；Or signal Line layer is with grid with the same material of layer, and metal level 50 is with source electrode and drain electrode with the same material of layer.

Wherein, for thin film transistor (TFT) type without limit, can be that N-type TFT or p-type are thin Film transistor.

Herein, when signal line layer and source electrode and drain electrode are now thin with the same material of layer with the same material of layer, metal level 50 and grid Film transistor is top gate type thin film transistor；When signal line layer and grid are same with the same material of layer, metal level 50 and source electrode and drain electrode The same material of layer, now thin film transistor (TFT) is bottom gate thin film transistor.

The utility model embodiment, when signal line layer and source electrode and drain with the same material of layer, metal level 50 and the same layer of grid During with material, thus signal line layer can be formed while source electrode and drain electrode is formed, metal is formed while grid is formed Layer 50；When signal line layer and grid with the same material of layer, metal level 50 and source electrode and drain electrode with the same material of layer, thus can formed Signal line layer while grid, metal level 50 is formed while source electrode and drain electrode is formed, so as to simplify array base palte Manufacture craft.The increased metal level 50 of the utility model embodiment is without the increase of cost and the complex process of technique.

It is further preferred that insulating barrier 40 and gate insulation layer are the same as the same material of layer.

The utility model embodiment, due to insulating barrier 40 with gate insulation layer with the same material of layer, thus it can be shown being formed The insulating barrier 40 of wiring region 1 is formed while the gate insulation layer in area 2, so as to simplify the manufacture craft of array base palte.

Preferably, signal line leads are data cable lead wire or grid line lead.

Herein, signal line leads refer to the first signal line leads 101 and secondary signal line lead 102.

The utility model embodiment, when signal line leads are data cable lead wire, data cable lead wire is connected with data wire, with The signal for driving IC12 outputs is transferred to data wire by data cable lead wire；When signal line leads are grid line lead, grid line Lead is connected with grid line, and the signal for driving IC12 outputs is transferred into grid line by grid line lead.

The utility model embodiment also provides a kind of display device, including above-mentioned array base palte.

Wherein, though display device can be display motion (for example, video) or fixed (for example, rest image) and No matter any device of the image of word or picture.More particularly, it is contemplated that the embodiment may be implemented in a variety of electronics dresses Associated in putting or with a variety of electronic installations, a variety of electronic installations such as (but not limited to) mobile phone, wireless device, individual Data assistant (PDA), hand-held or portable computer, gps receiver/omniselector, camera, MP4 video players, shooting Machine, game console, wrist-watch, clock, calculator, televimonitor, flat-panel monitor, computer monitor, automotive displays (for example, odometer display etc.), navigator, Cockpit Control Unit and/or display, the display of camera view are (for example, vehicle The display of middle rear view camera), electronic photographs, electronic bill-board or direction board, projecting apparatus, building structure, packaging and aesthetics knot Structure (for example, display for the image of a jewelry) etc..Certain display device can also be display panel.

On this basis, display device can be liquid crystal display device (Liquid Crystal Display, abbreviation LCD) or organic electroluminescent diode display device (Organic Light-Emitting Diode, referred to as OLED)。

The utility model embodiment provides a kind of display device, when array base palte appearance is bad, it is necessary to position bad by driving When causing still inside display panel to cause inside dynamic IC12, because the first subsignal line in secondary signal line lead 102 draws The subsignal line lead 1022 of line 1021 and second mutually disconnects, if the first signal line leads 101 are cut off so that driving IC12 and Cabling cut-out between display panel, thus the cut-out of signal between IC12 and display panel can be driven with realization, so as to Quickly to judge that bad caused by IC12 internal abnormalities, or caused by bad inside display panel.When being defined as display surface When intralamellar part is bad, still need to electrical testing area 11 be detected or still needed to by driving IC12 and display panel conducting, Ke Yitong Cross and be welded to connect the first subsignal line lead 1021 and the second subsignal line lead 1022 so that secondary signal line lead 102 is led It is logical, so drive the cabling between IC12 and display panel to turn on, thus drive the signal on IC12 to transmit to display surface In plate, in order to subsequently continue to detect to bad, therefore the structure of the array base palte of this practical embodiment offer can be real The cut-out of cabling between IC12 and display panel is now driven with overlapping again.

It is described above, only specific embodiment of the present utility model, but the scope of protection of the utility model is not limited to In this, any one skilled in the art can readily occur in change in the technical scope that the utility model discloses Or replace, it should all cover within the scope of protection of the utility model.Therefore, the scope of protection of the utility model should be with the power The protection domain that profit requires is defined.

Claims (11)

1. a kind of array base palte, including viewing area and wiring region, the wiring region includes multiple electrical testing areas, and its feature exists In the electrical testing area includes the first signal line leads and the secondary signal line lead being set up in parallel；The secondary signal line Lead includes the first subsignal line lead and the second subsignal line lead mutually disconnected；

Wherein, one end of first signal line leads and one end of the first subsignal line lead are connected with first port Connect；One end of the other end of first signal line leads and the second subsignal line lead is connected with second port；Institute State the first subsignal line lead and the second subsignal line lead can by being connected after welding, with turn on the first port and The second port.

2. array base palte according to claim 1, it is characterised in that the electrical testing area also includes：

Insulating barrier, the insulating barrier at least cover the first subsignal line lead, the second subsignal line lead and institute State the interstitial site between the first subsignal line lead and the second subsignal line lead；

Metal level on the insulating layer is set, along perpendicular to the direction of the metal level, the first subsignal line lead and institute Stating the second subsignal line lead and the metal level has overlapping region；

The flatness layer and conductive layer being successively set on the metal level；The conductive layer through the via on the flatness layer with The metal level is connected, and the conductive layer also extends through via and is connected with first signal line leads.

3. array base palte according to claim 2, it is characterised in that the conductive layer includes being located at first subsignal The first conductive pattern above line and the second conductive pattern above the second subsignal line, first conductive pattern Mutually disconnected with second conductive pattern；Along perpendicular to the direction of the conductive layer, the first subsignal line lead and institute The dwell boundaries between the second subsignal line lead are stated between first conductive pattern and second conductive pattern In dwell boundaries.

4. array base palte according to claim 2, it is characterised in that the insulating barrier is located at first signal line leads The region hollow out of face.

5. array base palte according to claim 1, it is characterised in that the first subsignal line lead and second son Signal line leads are connected with first signal line leads with layer.

6. according to the array base palte described in claim any one of 2-4, it is characterised in that the first subsignal line lead and institute The second subsignal line lead is stated to be connected with layer with first signal line leads.

7. array base palte according to claim 6, it is characterised in that the conductive layer includes being located at first subsignal The first conductive pattern above line, the second conductive pattern above the second subsignal line and positioned at first signal The 3rd conductive pattern above line lead；First conductive pattern and second conductive pattern with the 3rd conductive pattern Case connects with layer.

8. array base palte according to claim 3, it is characterised in that the conductive layer also includes being located at first signal The 3rd conductive pattern above line lead；First conductive pattern and second conductive pattern with the 3rd conductive pattern Case is not connected to；

The first subsignal line lead and the second subsignal line lead are not connected to first signal line leads.

9. array base palte according to claim 2, it is characterised in that the array base palte also includes thin film transistor (TFT), institute Stating thin film transistor (TFT) includes source electrode, drain electrode, active layer, grid and gate insulation layer；

First signal wire and the secondary signal line and the source electrode and the drain electrode with the same material of layer, the metal level with The grid is the same as the same material of layer；Or first signal wire and the secondary signal line with the grid with the same material of layer, institute Metal level is stated with the source electrode and the drain electrode with the same material of layer.

10. array base palte according to claim 1, it is characterised in that the signal line leads are data cable lead wire or grid Line lead.

11. a kind of display device, it is characterised in that including the array base palte described in claim any one of 1-10.