CN206848853U - A kind of anti-windup saturation simulation circuit for PID controller - Google Patents

A kind of anti-windup saturation simulation circuit for PID controller Download PDF

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Publication number
CN206848853U
CN206848853U CN201720749097.5U CN201720749097U CN206848853U CN 206848853 U CN206848853 U CN 206848853U CN 201720749097 U CN201720749097 U CN 201720749097U CN 206848853 U CN206848853 U CN 206848853U
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diode
voltage
vcc
error amplifier
saturation
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孙益余
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ITECH ELECTRONIC (NANJING) CO Ltd
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ITECH ELECTRONIC (NANJING) CO Ltd
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Abstract

A kind of anti-windup saturation simulation circuit for PID controller, using a pair of diodes being oppositely arranged, especially, using the voltage-regulator diode wherein with error amplifier output Opposite direction connection, limit the upper limit of the output end voltage.Using the characteristic of diode, limitation saturation voltage is less than the power supply of error amplifier, so as to which that realizes error amplifier moves back integration saturation.Circuit structure of the present utility model is simple, by the parallel connection of diode, can effectively reduce integration saturation amplitude while the error amplifier output accuracy is not influenceed, also, effectively reduce integration saturation depth.

Description

A kind of anti-windup saturation simulation circuit for PID controller
Technical field
It the utility model is related to automatic control system, more particularly to a kind of anti-windup saturated circuit for PID controller.
Background technology
Current automatic control system, generally can be practical in high-precision control occasion to make controller obtain good stability PID controller.And integration saturation problem can be run into using PID controller.
Generally, under digital circuit, using integration partition method, limit weakening integral PID control scheduling algorithm progress anti-windup is met Saturation.In digital circuit solve saturation problem several method, be required in real time constantly gathered data (including collection PID input End or output end), compare, then judge whether that the direction toward saturation is developed.If it is determined that possess what past saturation direction was developed Trend, then implement negative-feedback or clear-cut stopping integration work immediately, and then realize anti-saturation.
And due in analog circuit, can not and sampled, judged in real time, these above-mentioned methods are placed in analog circuit very Hardly possible is realized.It is even if real in other words, it is also desirable to design considerably complicated circuit.For example, if allow DSP calculate 1+2+3+~ Sum of~~~~10000 value, only need in digital circuit very simple one to instruct, but if calculated with analog circuit Then need huge computing circuit.In existing analog circuit, solves saturation problem, mostly the circuit structure dependent on complexity, no Succinctly, also very big inconvenience is brought to the debugging in engineering.
Therefore, it is badly in need of that a kind of circuit structure is succinct at present, and can effectively solve the problem that the analog circuit of integration saturation problem.
The content of the invention
In order to solve the shortcomings of the prior art, the purpose of this utility model is that providing one kind is used for PID controller Anti-windup saturation simulation circuit, it is effective reduce integration saturation amplitude while, effectively reduce integration saturation depth.
To achieve the above object, anti-windup saturation simulation circuit provided by the utility model, including error amplifier, PID Controller and its peripheral circuit, in addition to the first diode, the second diode, negative bias power supply and biasing resistor, the described 2nd 2 Pole pipe is voltage-regulator diode;
First diode is connected with the positive pole of second diode, described in the negative pole connection of second diode The output end of error amplifier, the negative pole of first diode connect the sampled voltage end of the error amplifier;
One end of the biasing resistor connects the positive pole of second diode, the other end connection institute of the biasing resistor State negative bias power supply.
Wherein, the biasing resistor resistance R3=VCC/ bias currents.
Wherein, the bias current is more than the starting current when voltage-regulator diode turns on.
In above-mentioned anti-windup saturation simulation circuit, the voltage stabilizing value VZ=VCC/4 of the voltage-regulator diode, wherein, VCC is institute State the supply voltage of error amplifier.
Meanwhile the reference voltage V REF of the error amplifier can use, VREF=VCC/4.
Further, in above-mentioned anti-windup saturation simulation circuit, first diode can be voltage-regulator diode or silicon two Pole pipe.
The utility model is compared with existing scheme and had the following technical effect that:
1. the utility model is by voltage-regulator diode, when error amplifier output magnitude of voltage VE exceeds VZ+VD, (VZ is The voltage stabilizing value of voltage-regulator diode, VD are the conduction voltage drop of the first diode), by voltage-regulator diode by error amplifier output Magnitude of voltage VE maximum voltage is limited in VEMAX=VREF+VD+VZ, so as to limit the depth of integration saturation, is advantageous to error and puts Big device moves back integration saturation;Meanwhile
It is 2. further, it is contemplated that the second diode DZ and the first diode D1 have leakage current, to avoid error from putting There is the leakage current of uA ranks when passing through DZ in big device output end VE, influences the output accuracy of error amplifier, the utility model is also Having additional biasing resistor R3 and negative bias power supply-VCC.A biased electrical circulation is provided by biasing resistor R3 and negative bias power supply-VCC Road so that controller will not be because of its output accuracy of the influence of leakage current of voltage-regulator diode and diode when not having a saturation.
3. the positive ordinary wave of error amplifier output voltage further, is large enough to hold for guarantee voltage-regulator diode voltage stabilizing value It is dynamic, the voltage stabilizing value VZ=VCC/4 of the voltage-regulator diode, wherein, VCC is the supply voltage of the error amplifier;VCC= 4VREF, wherein, VREF is the reference voltage of the error amplifier.
4. in addition, it is contemplated that error amplifier power supply is powered by positive supply, negative saturation is not present in circuit in itself, thus, can With using only the output end of a voltage-regulator diode Opposite direction connection error amplifier, in the sampled voltage of the error amplifier End, prevents above-mentioned voltage-regulator diode from occurring when the error amplifier is introduced into saturation state using only common silicon diode Forward conduction.Circuit is further simplified with this, reduces circuit hardware cost.
Brief description of the drawings
Accompanying drawing is used for providing and further understanding to of the present utility model, and a part for constitution instruction, and with this reality With new embodiment together, for explaining the utility model, do not form to limitation of the present utility model.In the accompanying drawings:
Fig. 1 is according to the anti-windup saturated circuit Organization Chart of the present utility model for PID controller;
Fig. 2 is existing PID controller circuit diagram.
Embodiment
Preferred embodiment of the present utility model is illustrated below in conjunction with accompanying drawing, it will be appreciated that described herein excellent Select embodiment to be merely to illustrate and explain the utility model, be not used to limit the utility model.
Fig. 2 is existing PID controller Organization Chart.Wherein, VREF is the reference voltage of error amplifier, and VS is sampling electricity Pressure, VE are the error amplification signals of error amplifier output, and PID regulations (or PID control shown in Fig. 1) are any RC network groups Into PID controller, VCC is the power supply of error amplifier.Sampled voltage VS is compared with reference voltage V REF, output Error amplification signal VE.In common control system, VS values are very close VREF values, if a certain moment is unexpected because loading Become and cause unexpected diminish of VS values to cause error amplifier output VE values positive step occur greatly, controlled when this step signal exceeds Scope processed, then actual VE values will touch the maximum voltage that error amplifier can export, usual Rail to quickly Rail (rail-to-rail) error amplifier can export maximum voltage close to its supply voltage VCC.But once VE values reach VCC values, there have been integration saturated phenomenon.
In the case where integrating saturated conditions, also will not continue to change even if the VS values VE values that again diminish.Only when VS values are than advance When row is reversely adjusted, VE values can just slowly withdrawn from deep saturation region elapsed time T, time T is error amplification Device moves back saturation time.When VE values retract normal control range, it can change VE values with VS value changes again and normally be controlled System.The over control length of controller caused by this integration saturation can cause system undesirable effect occur or even can damage The device of PID controller, more serious influence is caused, therefore, the measure of anti-windup saturation must be done in automatically controlling
The anti-windup saturation simulation circuit that the utility model book provides is as shown in Figure 1.Including error amplifier, PID control Device and its peripheral circuit, in addition to the first diode D1 and the second diode DZ, the second diode DZ are voltage-regulator diode;
The first diode D1 is connected with the positive pole of the second diode DZ, and the negative pole of the second diode DZ connects The output end of the error amplifier is connect, the negative pole of the first diode D1 connects the sampled voltage of the error amplifier End.
In the utility model, the measure of anti-windup saturation is carried out in terms of two simultaneously:Integration saturation amplitude should be reduced Reduce integration saturation depth.Therefore the course of work of circuit is as follows:
When VE is less than VZ, due to voltage-stabiliser tube work premise be backward voltage be more than ZV values, this condition and-VCC without Close also unrelated with VF.Thus, now, D1 and DZ do not work, and anti saturation circuit does not work, controller normal work.
At a certain moment, the unexpected i.e. previously described VE values that diminish of VS values are caused positive step occur greatly because loading to become suddenly When, if VE is more than (VZ+VD), voltage-stabiliser tube DZ and diode D1 work, at this moment VE maximum voltage VEMAX is limited in VEMAX =VREF+VD+VZ, works as VEMAX=VREF+VD+VZ<During VCC, i.e., when saturation voltage value is less than power supply value, be advantageous to miss Poor amplifier moves back integration saturation.Because, it is assumed that normal voltage maximum is 2V during VE unsaturations, if during saturation voltage be 12V and This 2 kinds of voltages of 6V, then the time that apparent 6V returns to 2V is significantly less than the time that 12V returns to 2V, the certain feelings of speed Under condition, distance is more remote, and the time is also longer, also implies that to move back saturation time elongated, is unfavorable for moving back integration saturation.
Preferred embodiment is such as:It is VD=0.7V to make N, and the voltage stabilizing value of voltage-stabiliser tube is VZ=1/4*VCC, VREF=1/4*VCC, VCC=12V ,-VCC=-12V, VEMAX=VREF+VD+VZ=1/4*VCC+0.7V+1/4*VCC=1/ 2*VCC+0.7V<<VCC, now the magnitude of voltage amplitude of saturation is greatly lowered and is advantageous to the error amplifier in very short time and moves back Integrate saturation.
Assuming that VS continues to diminish, VEMAX is caused a Δ VE increment occur, then error amplifier reverse input end electricity Press VF=VEMAX+ Δ VE-VD-VZ=VREF+VD+VZ+ Δ VE-VD-VZ=VFEF+ Δs VE>VREF.Now VF voltage is about Equal to VFEF+ Δ VE, than presteady state when voltage (about VREF) Δ VE values of having wanted big.This means in error amplifier The voltage rise at negative-feedback end, then the output end VE values nature of error amplifier can decline rapidly, and here it is a negative-feedback Process.Thus, VE can decline rapidly.This is advantageous to the depth for reducing integration saturation.
The anti-windup saturation of analog pid adjuster can be effectively realized by such scheme.
Based on above technical scheme, it is contemplated that leakage current caused by diode forward conducting, can also increase in foregoing circuit Negative bias power supply-VCC and biasing resistor R3, the biasing resistor R3 one end is added to connect the positive pole of the second diode DZ, institute The other end for stating biasing resistor R3 connects the negative bias power supply-VCC.Its operation principle is as follows:
In order to avoid VE occurs the output accuracy of the influence of leakage current error amplifier of uA ranks by DZ, R3 can be passed through A bias current passage is provided with-VCC.Preferred embodiment:It is VD=0.7V to make N, voltage-stabiliser tube Voltage stabilizing value is VZ=1/4*VCC, VREF=1/4*VCC, VCC=12V ,-VCC=-12V, due to D1 reverse cut-off ,-VCC <VS (VS ≈ VREF), DZ leakage current will pass through D1 by R3 and not.The selection of voltage and electric current only conduct in the present embodiment Referring generally to being not necessarily to the proportionate relationship for meeting VZ=VREF=VCC/4.In engineering, the electric current have to be larger than voltage stabilizing Starting current when pipe turns on.Typically, 3V or so voltage-stabiliser tube starting current is about 1mA, but bias current again can not be excessive, Cross the loss of conference increase resistance and voltage-stabiliser tube.Thus in the present embodiment, the bias current can provide 1mA, can inhale completely The leakage current for flowing through DZ is received, then R3=VCC/ bias currents=[0V- (- 12V)]/1mA=12k.
Power in view of error amplifier and powered by positive supply, negative saturation is not present in circuit in itself, therefore, it is possible to be used only The output end of one voltage-regulator diode Opposite direction connection error amplifier, in the sampled voltage end VS of the error amplifier, only make Prevent above-mentioned voltage-regulator diode from occurring positive guide when the error amplifier is introduced into saturation state with common silicon diode It is logical.Therefore, circuit hardware cost consideration, in above-mentioned anti-windup saturation simulation circuit, the first diode D1 is preferably common Silicon diode.
One of ordinary skill in the art will appreciate that:Preferred embodiment of the present utility model is the foregoing is only, and Limitation the utility model is not used in, although the utility model is described in detail with reference to the foregoing embodiments, for ability For the technical staff in domain, its technical scheme that can be still recorded to foregoing embodiments is modified, or to its middle part Technical characteristic is divided to carry out equivalent substitution.All any modifications within the spirit and principles of the utility model, made, equally replace Change, improve, should be included within the scope of protection of the utility model.

Claims (6)

1. a kind of anti-windup saturation simulation circuit for PID controller, including, error amplifier and PID controller, its feature It is, in addition to the first diode (D1), the second diode (DZ), negative bias power supply (- VCC) and biasing resistor (R3), described Two diodes (DZ) are voltage-regulator diode;
First diode (D1) is connected with the positive pole of second diode (DZ), the negative pole of second diode (DZ) The output end of the error amplifier is connected, the negative pole of first diode (D1) connects the sampling electricity of the error amplifier Pressure side;
One end of the biasing resistor (R3) connects the positive pole of second diode (DZ), the biasing resistor (R3) it is another End connects the negative bias power supply (- VCC).
2. it is used for the anti-windup saturation simulation circuit of PID controller as claimed in claim 1, it is characterised in that the biasing Resistance (R3) resistance R3=VCC/ bias currents;Wherein, VCC is the absolute value of the negative bias supply voltage.
3. it is used for the anti-windup saturation simulation circuit of PID controller as claimed in claim 2, it is characterised in that the biasing Electric current is more than the starting current when voltage-regulator diode turns on.
4. it is used for the anti-windup saturation simulation circuit of PID controller as claimed in claim 3, it is characterised in that the voltage stabilizing The voltage stabilizing value VZ=VCC/4 of diode, wherein, VCC is the supply voltage of the error amplifier.
5. it is used for the anti-windup saturation simulation circuit of PID controller as claimed in claim 3, it is characterised in that the error The reference voltage V REF=VCC/4 of amplifier, wherein, VCC is the supply voltage of the error amplifier.
6. it is used for the anti-windup saturation simulation circuit of PID controller as claimed in claim 5, it is characterised in that described first Diode (D1) is voltage-regulator diode or silicon diode.
CN201720749097.5U 2017-06-26 2017-06-26 A kind of anti-windup saturation simulation circuit for PID controller Active CN206848853U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110673682A (en) * 2019-11-13 2020-01-10 海光信息技术有限公司 Digital low dropout regulator and control method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110673682A (en) * 2019-11-13 2020-01-10 海光信息技术有限公司 Digital low dropout regulator and control method thereof

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