CN206759508U - A kind of airborne distributed parallel computing environment of modularized design - Google Patents
A kind of airborne distributed parallel computing environment of modularized design Download PDFInfo
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- CN206759508U CN206759508U CN201720286085.3U CN201720286085U CN206759508U CN 206759508 U CN206759508 U CN 206759508U CN 201720286085 U CN201720286085 U CN 201720286085U CN 206759508 U CN206759508 U CN 206759508U
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Abstract
The utility model discloses a kind of airborne distributed parallel computing environment of modularized design, the utility model is by using the modularized design that two-rank moduleization design is that system uses node, each node uses the modularized design of board, overcome the problem of acquisition system autgmentability, bad adaptability are recorded present in prior art, a new analog input card need to be only developed again for new demand, and it need not change in itself for system, the development cost of reduction, scalability and the framework flexibility of system are improved to greatest extent, i.e., with reconfigurability.The utility model can be widely applied to various airborne distributed parallel computing environments.
Description
Technical field
Airborne distributed data acquisition system is the utility model is related to, for gathering a variety of parameters to be measured on aircraft.
Background technology
FPGA:Field-Programmable Gate Array, live restructural gate array.
1553B：1553B buses are the time-division of interior of aircraft, instruction/response multiplex bus.
FC:Fibre Channel, optical-fibre channel.
With the development of computer technology and the communication technology, the airborne data acquisition system collection from low volume data, note
Record develops into Large Copacity, the real-time collection of large-scale data, transmission and record processing, and certain corresponding pass is all deposited between data
System, this proposes higher requirement to data collecting system real-time transmittability and multiple task management ability.Surveyed based on taking a flight test
The features such as test acquisition data class is more, distribution is wide, are widely known together using distributed parallel computing environment.
Current domestic special airborne data acquisition equipment, specific aim is stronger, not strong to new demand autgmentability, to difference
Demand bad adaptability, it is impossible to fully meet the demand of current flight test.Also there are some to be based on Embedded distributed system in addition
System is being studied, although design comparison is simple, the problems such as poor synchronization of collection, bus data capacity is small be present, it is impossible to meet
Fast-developing airborne testing requirement.
Utility model content
In order to solve the above-mentioned technical problem, the purpose of this utility model is to provide a kind of strong airborne distribution of scalability
Acquisition system.
Technical scheme is used by the utility model：
A kind of airborne distributed parallel computing environment of modularized design, including host node and multiple child nodes, the host node
Including master control borad and some pieces of communicating conversion plates, the communicating conversion plate is connected with master control borad；The child node includes communication
Encoding board and some pieces of feature boards, the feature board are connected with communication code plate, the feature board be collection plate, memory plane or
Communicating conversion plate；The communication code plate of the child node is connected with the communicating conversion plate of host node or upper level child node.
Preferably, the host node and multiple child nodes are respectively provided with diverse location aboard, the communicating conversion plate
For photoelectric conversion plate, the photoelectric conversion plate is connected with communication code plate by optical fiber.
Preferably, the host node also includes time-code plate, and the time-code plate is connected with master control borad, and the time-code plate is for being
Master control borad provides system time information and pulse per second (PPS).
Preferably, the child node also includes memory plane, and the memory plane is connected with communication code plate；The child node is also
Including communicating conversion plate, the communicating conversion plate of the child node is connected with the communication code plate of next stage child node；The collection
Plate includes one in DI collection plates, ADI collection plates, video acquisition plate, 1553B collection plates, 422 collection plates and Ethernet collection plate
Kind or a variety of collection plates.
Preferably, the system also includes configuration computer, and the configuration computer passes through gigabit Ethernet and master control borad
Connection.
Preferably, master control borad and the communication code plate realizes the forwarding and processing of data using FPGA.
The beneficial effects of the utility model are：
The utility model uses by using the modularized design that two-rank moduleization design is that system uses node, each node
The modularized design of board, the problem of acquisition system autgmentability, bad adaptability are recorded present in prior art is overcome, for
New demand need to only develop a new analog input card again, and need not change in itself for system, the development cost of reduction,
Scalability and the framework flexibility of system are improved to greatest extent, i.e., with reconfigurability.
In addition, the utility model also by using FPGA as core processing device, due to the parallel real-time characteristics of FPGA, no
The uncertain problem of embedded system thread dispatching be present, what the delay time error of data transfer was to determine, by each to system
Node-node transmission Time delay measurement amendment, it is ensured that the precision of system synchronization collection.Data are transmitted by optical fiber between each node, ensured
The reliability and stability of the remote high-speed transfers of data.
The utility model can be widely applied to various airborne distributed parallel computing environments.
Brief description of the drawings
Specific embodiment of the present utility model is described further below in conjunction with the accompanying drawings：
Fig. 1 is the node topology structural representation of the first embodiment of Tthe utility model system；
Fig. 2 is the circuit framework topological diagram of second of embodiment of Tthe utility model system；
Fig. 3 is a kind of main control board data forwarding capability interface diagram of embodiment of Tthe utility model system；
Fig. 4 is a kind of communication code plate data forwarding functional interface schematic diagram of embodiment of Tthe utility model system；
Fig. 5 is a kind of photoelectric conversion plate data forwarding functional interface schematic diagram of embodiment of Tthe utility model system.
Embodiment
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase
Mutually combination.
Not strong for existing airborne distributed parallel computing environment adaptability, the problem of poor synchronization, the present embodiment devises one
The airborne distributed real-time acquisition system of restructural of the kind based on FPGA.The characteristics of being handled using FPGA real-time parallels, is being realized
On the basis of distributed measurement function, the synchronism of collection is improved.
As depicted in figs. 1 and 2, the airborne distributed parallel computing environment of a kind of modularized design, including host node 1 and 3 sons
Node 2, host node 1 includes master control borad 11 and some pieces of communicating conversion plates, communicating conversion plate are connected with master control borad 11；Child node
2 are connected including communication code plate 21 and some pieces of feature boards, the feature board with communication code plate 21, and the feature board is to adopt
Collect plate, memory plane 22 or communicating conversion plate；The master control borad 11 of host node 1 is compiled by the communication of communicating conversion plate and each child node 2
Code plate 21 connects.Host node 1 and multiple child nodes 2 are respectively provided with diverse location aboard, and communicating conversion plate is opto-electronic conversion
Plate 12, photoelectric conversion plate 12 are connected with communication code plate 21 by optical fiber.Host node 1 also includes time-code plate 13, time-code plate 13 with
Master control borad 11 connects, and time-code plate 13 is used to provide system time information and pulse per second (PPS) for master control borad 11.The collection plate includes DI
Collection plate 231（Data signal inputs collection plate）, ADI collection plates 232（Analog signal inputs collection plate）, video acquisition plate 233,
1553B collection plates 234,422 collection plates 235（422 rs 232 serial interface signals input collection plate）With one kind in Ethernet collection plate 236 or
A variety of collection plates.System also includes configuration computer 3, and configuration computer 3 is connected by gigabit Ethernet with master control borad 11.Master control
Plate 11 and communication code plate 21 realize the forwarding and processing of data using FPGA.
Specifically, airborne distributed real-time acquisition system, it mainly includes：Computer 3, master control borad 11 are configured, communication is compiled
The compositions such as code plate 21, photoelectric conversion plate 12, other various functions boards.
Computer 3 is configured according to the topological structure of configuration system and the configuration parameter of each functional cards, systematic function board
Configuration file and system operational parameters.
Master control borad 11 is the core board of system, can be connected by Ethernet interface with configuration computer 3, it is each to carry out system
The configuration of kind running parameter.The course of work configures to each functional cards of system, completes each functional cards gathered data
Collect, handle and forward.
Communication code plate 21 completes collection, processing and the forwarding of each data of child node 2.
Photoelectric conversion plate 12 possesses the function of system extension child node 2.
In the present embodiment, airborne distributed parallel computing environment uses real-time data communication pattern, will be dispersed in aircraft difference position
The multiple acquisition nodes put connect and compose a distributed system.Wherein, minimum unit is board, including master control borad 11, communication
Encoding board 21 and various functions board, except time-code plate 13, photoelectric conversion plate 12, memory plane 22 are non-acquired class work(in functional cards
Outside energy board, other are entirely to gather class board.The minimum unit that can be worked in system is node（Host node 1 and child node 2）,
Each node is made up of the communication code plate 21 of master control borad 11/ and various functions board.The communication code plate 21 of master control borad 11/ in node
It is that the element of node there must be and position is fixed, other functional cards can be added according to being actually needed
And deletion, autgmentability, flexibility and adaptability are high.In system, host node 1 carries out next stage child node by photoelectric conversion plate 12
2 extension.In the present embodiment, one piece of photoelectric conversion plate 12 can at most extend 2 each child nodes 2, be entered between node by optical fiber
Row connection, as shown in Figure 2.
In the course of work, system work is divided into two stages：Interaction configuration phase and time slot working stage.It is two stage to set
Configure and work asynchronously in respect of beneficial to the unified of system.
1. interact configuration phase.
Interaction configuration phase system reads the configuration information of configuration computer 3, and the topological structure of system is checked, matched somebody with somebody
Put the board that computer 3 configures needs by master control borad 11 to configure, in all acquisition function plates of interaction configuration phase
Card is all in configuration wait state and without data acquisition.
2. time slot working stage.
After the completion of all configurations, host node 1 is transmitted into slotted mode order, and system enters input time slot working stage,
Each analog input card starts synchronous acquisition, and gathered data is sent in sequence into master by the way of timesharing according to time slot configuration
Plate 11 is controlled, then data processing, forwarding are completed by master control borad 11 is unified, eventually through being passed under PCM or memory plane 22 is remembered
Record.
In the present embodiment, master control borad 11 and communication code plate 21 realize the forwarding and processing of data using FPGA.
The data forwarding of master control borad 11 based on FPGA is designed as shown in figure 3, the 8 road 1.25Gbps that master control borad 11 passes through bottom
High speed serialization transceiver（Selection end GX_RX [1-8] and 8 tunnel branch output end GX_TX [1-8] are inputted including 8 tunnels）With internal work(
Can board（Photoelectric conversion plate 12 and time-code plate 13）It is connected, master control borad 11 is by inquiring about 8 road high-speed transceiver receiving ports（Input
Select end GX_RX [1-8]）, dock and take in capable judgement, one, which breaks but has data to receive the circuit-switched data and pass through, configures（Data are handed over
Change）By data from corresponding high-speed transceiver output end（Branch output end GX_TX [1-8]）Send.
The data forwarding of communication code plate 21 based on FPGA is designed as shown in figure 4,8 tunnels that communication code plate 21 passes through bottom
1.25Gbps high speed serialization transceiver（Including electric signal interface：8 tunnels input selection end GX_RX [1-8] and 8 tunnel branch output ends
GX_TX[1-8]）With built-in function board（DI collection plates 231, ADI collection plates 232, video acquisition plate 233,1553B collection plates
234th, 422 collection plates 235 and Ethernet collection plate 236）It is connected, passes through the optical fiber interface at top（Including optical fiber input interface FC_
RX and optical fiber output interface FC_TX）It is connected with the photoelectric conversion plate 12 of host node 1, end GX_ is selected by the input of high-speed transceiver
The inside gathered data that RX [1-8] is received directly is forwarded to even higher level of node by optical fiber output interface FC_TX（Host node or on
One-level child node）, by the data that optical fiber input interface FC_RX is received by judging that selection exports from the branch of high-speed transceiver
Hold GX_TX [1-8] outputs.
The data forwarding of photoelectric conversion plate 12 is designed as shown in figure 5, the 1 road 1.25Gbps that photoelectric conversion plate 12 passes through bottom
High speed serialization transceiver（Including electric signal interface：1 tunnel input selection end GX_RX and 1 tunnel branch output end GX_TX）With this section
The communication code plate 21 of master control borad 11/ of point is connected, and passes through 2 optical fiber interfaces at top（Including 2 road optical fiber input interface FC_RX
[1,2] and 2 tunnel optical fiber output interface FC_TX [1,2]）It is connected with the communication code plate 21 of next stage child node 2, by receiving and dispatching at a high speed
The data that the input selection end GX_RX of device is received are determined to be forwarded to 2 tunnel optical fiber output interface FC_TX [1,2] wherein by configuration
One, the branch output end GX_TX by the data that optical fiber input interface FC_RX [1,2] is received by bottom high-speed transceiver
It is sent to the communication code plate 21 of master control borad 11/.
Below in Fig. 2, by taking 1 host node, 1,3 child node 2 as an example, each several part of each system is carried out specifically
It is bright.In the present embodiment, host node 1 is by master control borad 11 and functional cards（Most 8 pieces）Form, child node 2 by communication control panel and
Functional cards（Most 8 pieces）Form.System carries out the extension of next stage child node 2 by photoelectric conversion plate 12, and one piece of photoelectricity turns
2 each child nodes 2 can at most be extended by changing plate 12, so 3 each child nodes 2 of extension, at least need 2 pieces of photoelectric conversion plates 12.
1. the function of host node 1 defines
Host node 1 is typically made up of master control borad 11, photoelectric conversion plate 12, time-code plate 13, bottom plate and acquisition function board etc.,
With following function：
Time-code plate 13 gathers outside time-code source（GPS/IRIGB-AC/IRIGB-DC）, system is provided for master control borad 11 after decoding
Temporal information of uniting and pulse per second (PPS)；
Photoelectric conversion plate 12 completes data/commands bag forwarding capability, any agreement and configuration feature is not realized, for system
Pellucidity is in for topology；
Master control borad 11 realized after upper electricity to the function of initializing of system, including the local loading of configuration file, building topology table,
Configuration inspection to each functional cards of system, for each node communication board parse and issue time slot configuration, be communication code plate 21
（PCM plates）Parse and issue form/grid configuration, test link delay, time service is carried out to system, initiates synchronous acquisition instruction etc.
Work energy；Into after the collecting work stage, all data will all pass through master control borad 11, and master control borad 11 realizes data routing forwarding work(
Energy.
2. the function of child node 2 defines
Child node 2 is typically made up of communication code plate 21, bottom plate and acquisition function board etc., has following function：
Collection plate realizes corresponding data acquisition function, and the entry instruction interaction stage is given tacit consent to after upper electricity, waits master control borad 11 to send out
The instruction such as existing topology and configuration, communication code plate 21 is come from when receiving（PCM plates）Access pulse after proceed by data and adopt
Collect and collection or filling packet are sent according to pulse；
The entry instruction interaction stage is given tacit consent on communication code plate 21 after electricity, waits master control borad 11 to find that topology and time slot are matched somebody with somebody
Put, PCM format/grid configuration, configuration is parsed after the beginning acquisition instructions from master control borad 11 are received, after being arrived by next second
Start by the access pulse of time slot sendaisle；Collecting work stage, communication code plate 21 will receive all of whole system and adopt
Collect packet, configured with reference to time slot configuration and PCM grids, the packet of corresponding board is waited in corresponding time slot, if this when
What gap received is that other board packets then abandon and indicate mistake by BIT, if packet of the time slot without corresponding board
Then mend filling bag.
It should be noted that child node 2 can also be by inserting communicating conversion plate（Photoelectric conversion plate 12）, realization is connected to
Next stage child node 2.In other words, child node 2 can have multilevel design, and host node 1 is connected to by photoelectric conversion plate 12
One-level child node 2, child node 2 are connected to next stage child node 2 by photoelectric conversion plate 12.Therefore, the system has stronger
Scalability, networking flexibility and higher environmental suitability.Its data transfer and processing are as described in above-mentioned embodiment, herein not
Repeat.
FPGA using the single clock cycle as the cycle of operation and handle identical data time cycle fix the characteristics of, handing over
The mutual stage is initiated the link delay measurement to each child node 2 by master control borad 11.Tested in test by the transmission link of master control borad 11
Instruction, node communication code plate 21 to be tested are replied immediately after receiving the instruction, and master control borad 11 is sent by testing
The time difference Δ t for receiving and instructing is instructed, the reaction time Δ t1 of child node 2 is gone out by theory analysis（This this take communication code
Reaction time of the plate 21 to test instruction）, (Δ t- Δ t1)/2 are the actual link delay t of node.
In order to ensure that each node of system is synchronous, master control borad 11 is per second to carry out a time service, each child node 2 to child node 2
According to time service order and link delay is received, the local time is corrected.So as to ensure that each node time is synchronous.In the present embodiment, this
The ground time=mainboard time service+link delay.
Each functional cards of system can complete independent acquisition function, and when lock-out pulse arrives, all analog input cards are carried out
Data acquisition, and the time that affix gathers before gathered data, so as to post-processing, the data collected are according to system configuration
Data are sent successively, master control borad 11, master control borad 11 are ultimately feeding to by communication code plate 21, optical fiber, photoelectric conversion plate 12 etc.
Board to being forwarded to system configuration after data processing（Usually memory plane 22）.
The beneficial effect of the system includes：
1st, the system collection two-rank moduleization design is the modularized design that system uses node, and node uses the mould of board
Blockization designs, and has reconfigurability to improve system flexibility to greatest extent.Demand according to airborne testing task is fast
Speed builds the distributed parallel computing environment of required function, and new system is carried out by the configuration computer of system support after the completion of building
Description, system configuration parameter is generated, is configured, re-powered using gigabit Ethernet download system, system can join according to configuration
Number synchronizes collection, record.No matter which data acquisition function is system possess, and no matter system acquisition scale is much, its topology
Forming structure can be completely the same.Difference between different system be used in number of nodes it is different, functional cards are not in node
Together.
2nd, a new analog input card need to be only developed again for new demand, and need not change in itself for system,
The development cost of reduction.
3rd, the system uses FPGA as core processing device, due to the parallel real-time characteristics of FPGA, in the absence of embedded system
Unite the uncertain problem of thread dispatching, what the delay time error of data transfer was to determine, by being delayed to each node-node transmission of system
Measurement amendment, it is ensured that the precision of system synchronization collection.
Above is preferably implement to be illustrated to of the present utility model, but the utility model is created and is not limited to institute
Embodiment is stated, those skilled in the art can also make a variety of be equal on the premise of without prejudice to the utility model spirit
Deformation is replaced, and these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (6)
1. the airborne distributed parallel computing environment of a kind of modularized design, it is characterised in that including host node and multiple child nodes, institute
Host node is stated to be connected with master control borad including master control borad and some pieces of communicating conversion plates, the communicating conversion plate；The child node
Including communication code plate and some pieces of feature boards, the feature board is connected with communication code plate, the feature board be collection plate,
Memory plane or communicating conversion plate；The communication code plate of the child node connects with host node or the communicating conversion plate of upper level child node
Connect.
A kind of 2. airborne distributed parallel computing environment of modularized design according to claim 1, it is characterised in that the master
Node and multiple child nodes are respectively provided with diverse location aboard, and the communicating conversion plate is photoelectric conversion plate, the photoelectricity
Change-over panel is connected with the communication code plate of next stage child node by optical fiber.
A kind of 3. airborne distributed parallel computing environment of modularized design according to claim 2, it is characterised in that the master
Node also includes time-code plate, and the time-code plate is connected with master control borad, and the time-code plate is used to provide system time letter for master control borad
Breath and pulse per second (PPS).
4. the airborne distributed parallel computing environment of a kind of modularized design according to claim 3, it is characterised in that described to adopt
Collecting plate is included in DI collection plates, ADI collection plates, video acquisition plate, 1553B collection plates, 422 collection plates and Ethernet collection plate
It is one or more.
5. a kind of airborne distributed parallel computing environment of modularized design according to any one of Claims 1-4, its feature exist
In the system also includes configuration computer, and the configuration computer is connected by gigabit Ethernet with master control borad.
A kind of 6. airborne distributed parallel computing environment of modularized design according to claim 5, it is characterised in that the master
Control plate and communication code plate realize the forwarding and processing of data using FPGA.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106873464A (en) * | 2017-03-22 | 2017-06-20 | 深圳市中航世星科技有限公司 | A kind of airborne distributed parallel computing environment of restructural and method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106873464A (en) * | 2017-03-22 | 2017-06-20 | 深圳市中航世星科技有限公司 | A kind of airborne distributed parallel computing environment of restructural and method |
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