CN206759397U

CN206759397U - Common-gate low noise amplifier circuit is coupled based on current multiplexing capacitive cross

Info

Publication number: CN206759397U
Application number: CN201720636888.7U
Authority: CN
Inventors: 高海军
Original assignee: Zhejiang Sensitive Sensor Technology Co Ltd
Current assignee: Zhejiang Sensitive Sensor Technology Co Ltd
Priority date: 2017-06-05
Filing date: 2017-06-05
Publication date: 2017-12-15
Anticipated expiration: 2027-06-05

Abstract

It the utility model is related to a kind of based on current multiplexing capacitive cross coupling common-gate low noise amplifier circuit, it is mainly made up of two NMOS tubes, two PMOSs, nine electric capacity, five inductance and four resistance, using current multiplexing technology, in the case of identical bias current, grid NMOS input pipes altogether are coupled by capacitive cross grid PMOS input pipes altogether are coupled to, capacitive cross and produce input mutual conductance to common.The conversion efficiency of input voltage output current is improved in the case of identical bias current, makes the equivalent inpnt mutual conductance of low-noise amplifier increase, improves the voltage gain of low-noise amplifier.Simultaneously, because the electric current for flowing through two common grid input pipes pair of capacitive cross coupling is same electric current, there is very strong correlation between caused channel current noise, the noise of low-noise amplifier is not drawn to increase, therefore the noise coefficient of the structure has certain improvement compared to traditional structure.

Description

Common-gate low noise amplifier circuit is coupled based on current multiplexing capacitive cross

Technical field

It the utility model is related to a kind of current multiplexing capacitive cross that is based on and couple common-gate low noise amplifier circuit, belong to micro- Electronic technology field.

Background technology

Low-noise amplifier is the key modules in wireless receiving and dispatching front-end circuit, and its noise coefficient and gain decide reception The receiving sensitivity of system.Reduce low-noise amplifier noise coefficient, improve its gain be advantageous to improve receiving sensitivity, but The cost brought is that the power consumption of low-noise amplifier sharply increases.The increase of this power consumption modern handheld Wireless Telecom Equipment, It is unacceptable inside implantable medical devices；Therefore, the low power dissipation design of low-noise amplifier is very crucial, and it is determined Determine the service life of handheld wireless communication device, implantable medical devices.

Utility model content

The purpose of this utility model is the above-mentioned deficiency for prior art, there is provided one kind is based on current multiplexing capacitive cross Common-gate low noise amplifier circuit is coupled, to improve the voltage gain of low-noise amplifier and receiving sensitivity, improves noise shape Condition.

The technical solution of the utility model is：One kind is based on current multiplexing capacitive cross coupling common-gate low noise amplifier electricity Road, mainly it is made up of two NMOS tubes, two PMOSs, nine electric capacity, five inductance and four resistance, wherein the first electric capacity First end connects with the first end of the second electric capacity, as in-phase input end, the first end of the 3rd electric capacity and the first of the 4th electric capacity End connection, as inverting input；Second end of the first electric capacity, the first end of the first inductance, the first end of the 5th electric capacity and The source electrode connection of one input NMOS tube, the second end of the second electric capacity, the first end of the second inductance, the first end of the 7th electric capacity and the The source electrode connection of one input PMOS；Second end of the 3rd electric capacity, the first end of the 3rd inductance, the first end of the 6th electric capacity and The source electrode connection of two input NMOS tubes；Second end of the 4th electric capacity, the first end of the 4th inductance, the first end of the 8th electric capacity and The source electrode connection of two input PMOSs；The grid at the second end of the 5th electric capacity, the first end of first resistor and the second input NMOS tube Pole connects；Second end of the 6th electric capacity, the first end of second resistance connect with the grid of the first input NMOS tube；7th electric capacity Second end, the first end of 3rd resistor connect with the grid of the second input PMOS；Second end of the 8th electric capacity, the 4th resistance First end connects with the grid of the first input PMOS；Second end of first resistor connects with the second end of second resistance, as First bias input end；Second end of 3rd resistor connects with the second end of the 4th resistance, as the second bias input end；First Second end of inductance connects and is grounded with the second end of the 3rd inductance；Second end of the second inductance connects with the second end of the 4th inductance Connect and connect power supply；The drain electrode of first input NMOS tube, the drain electrode of the first input PMOS, the first end of the 5th resistance, the 5th electricity The first end of sense connects with the first end of the 9th electric capacity, as in-phase output end；Drain electrode, the second input of second input NMOS tube The drain electrode of PMOS, the second end of the 5th resistance, the second end of the 5th inductance connect with the second end of the 9th electric capacity, as anti-phase Output end.

The beneficial effects of the utility model are：Using current multiplexing technology, in the case of identical bias current, pass through electricity Holding cross-couplings, grid NMOS input pipes couple grid PMOS input pipes pair altogether to, capacitive cross altogether, common to produce input mutual conductance, in phase With the conversion efficiency that input voltage-output current is improved in the case of bias current, make the equivalent inpnt of low-noise amplifier across Increase is led, improves the voltage gain of low-noise amplifier.Simultaneously as flow through two capacitive cross couplings grid input pipe pair altogether Electric current be same electric current, there is very strong correlation, the noise of low-noise amplifier between caused channel current noise It is not drawn to increase, therefore the noise coefficient of the structure has certain improvement compared to traditional structure.

Brief description of the drawings

Fig. 1 is circuit theory diagrams of the present utility model.

Embodiment

Referring to Fig. 1, in amplifier circuit in low noise disclosed in the utility model, the first electric capacity C1 first end and the second electricity Hold C2 first end connection, as the in-phase input end Vin+ of this amplifier circuit in low noise, the 3rd electric capacity C3 first end and 4th electric capacity C4 first end connection, the inverting input Vin- as this amplifier circuit in low noise；

First electric capacity C1 the second end, the first inductance L1 first end, the 5th electric capacity C5 first end and the first input NMOS tube MN1 source electrode connection, the second electric capacity C2 the second end, the second inductance L2 first end, the 7th electric capacity C7 first end Connected with the first input PMOS MP1 source electrode, the 3rd electric capacity C3 the second end, the 3rd inductance L3 first end, the 6th electric capacity C6 first end connects with the second input NMOS tube MN2 source electrode, the 4th electric capacity C4 the second end, the first of the 4th inductance L4 End, the 8th electric capacity C8 first end connect with the second input PMOS MP2 source electrode；

5th electric capacity C5 the second end, first resistor R1 first end connect with the second input NMOS tube MN2 grid, the Six electric capacity C6 the second end, second resistance R2 first end connect with the first input NMOS tube MN1 grid, the 7th electric capacity C7's Second end, 3rd resistor R3 first end connect with the second input PMOS MP2 grid, the 8th electric capacity C8 the second end, the Four resistance R4 first end connects with the first input PMOS MP1 grid；

First resistor R1 the second end connects with second resistance R2 the second end, and as this amplifier circuit in low noise One bias input end Vbiasn；

3rd resistor R3 the second end connects with the 4th resistance R4 the second end, and as this amplifier circuit in low noise Two bias input end Vbiasp；

First inductance L1 the second end connects and is grounded with the 3rd inductance L3 the second end；

Second inductance L2 the second end is connected with the 4th inductance L4 the second end and meets power vd D；

First input NMOS tube MN1 drain electrode, the first input PMOS MP1 drain electrode, the 5th resistance R5 first end, the Five inductance L5 first end connects with the 9th electric capacity C9 first end, the in-phase output end as this amplifier circuit in low noise Vout+；

Second input NMOS tube MN2 drain electrode, the second input PMOS MP2 drain electrode, the 5th resistance R5 the second end, the Five inductance L5 the second end connects with the 9th electric capacity C9 the second end, the reversed-phase output as this amplifier circuit in low noise Vout-。

In the utility model, the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3 and the preferably identical electricity of the 4th electric capacity Hold, for realizing the isolation of DC component in input signal；First resistor R1 and the preferred same resistances of second resistance R2, the 3rd electricity Hinder R3 and the 4th preferred same resistances of resistance R4, it is the respectively second input NMOS tube MN2, the first input NMOS tube MN1, second defeated Enter the input PMOSs of PMOS MP2 and first MP1 and gate bias is provided；5th electric capacity C5 and the preferably identical electricity of the 6th electric capacity C6 Hold, the 7th electric capacity C7 and the 8th preferred same capacitances of electric capacity C8, the respectively second input NMOS tube MN2, the first input NMOS tube MN1, the second input PMOS MP2 and the first input PMOS MP1 grid input capacitance；The electricity of first inductance L1 and second Feel the preferred identical inductances of L3, the 3rd inductance L2 and the 4th preferred identical inductances of inductance L4, be respectively intended to the first input NMOS tube MN1 source electrode, the second input NMOS tube MN2 source electrode, the first input PMOS MP1 source electrode and the second input PMOS MP2 Source electrode provide direct current biasing, while respectively with first input NMOS tube source MN1 poles to ground parasitic capacitance, second input NMOS Parasitic capacitance, the parasitic capacitance of first input PMOS MP1 source electrode to ground and second input PMOS of the pipe MN2 source electrode to ground MP2 source electrode reduces the leakage of input signal, improves gain to the parasitic capacitance resonance on ground；5th inductance L5, the 9th electric capacity C9 A band logical selection laod network is formed with the 5th resistance R5, for realizing that the frequency-selecting of signal is amplified.

Claims

1. one kind is based on current multiplexing capacitive cross coupling common-gate low noise amplifier circuit, it is characterised in that mainly by two NMOS tube, two PMOSs, nine electric capacity, five inductance and four resistance compositions, wherein the first end of the first electric capacity and second The first end connection of electric capacity, as in-phase input end, the first end of the 3rd electric capacity connects with the first end of the 4th electric capacity, as anti- Phase input；Second end of the first electric capacity, the first end of the first inductance, the first end of the 5th electric capacity and first input NMOS tube Source electrode connects, and the second end of the second electric capacity, the first end of the second inductance, the first end of the 7th electric capacity and first input PMOS Source electrode connects；Second end of the 3rd electric capacity, the first end of the 3rd inductance, the first end of the 6th electric capacity and second input NMOS tube Source electrode connects；Second end of the 4th electric capacity, the first end of the 4th inductance, the first end of the 8th electric capacity and second input PMOS Source electrode connects；Second end of the 5th electric capacity, the first end of first resistor connect with the grid of the second input NMOS tube；6th electric capacity The second end, second resistance first end with first input NMOS tube grid connect；Second end of the 7th electric capacity, 3rd resistor First end with second input PMOS grid connect；Second end of the 8th electric capacity, the first end of the 4th resistance and first are defeated Enter the grid connection of PMOS；Second end of first resistor connects with the second end of second resistance, as the first bias input end； Second end of 3rd resistor connects with the second end of the 4th resistance, as the second bias input end；Second end of the first inductance and Second end of the 3rd inductance connects and is grounded；Second end of the second inductance is connected with the second end of the 4th inductance and connects power supply；The The drain electrode of one input NMOS tube, the first input drain electrode of PMOS, the first end of the 5th resistance, the first end of the 5th inductance and the The first end connection of nine electric capacity, as in-phase output end；Second input NMOS tube drain electrode, second input PMOS drain electrode, Second end of the 5th resistance, the second end of the 5th inductance connect with the second end of the 9th electric capacity, as reversed-phase output.