CN206742235U - 芯片尺寸封装 - Google Patents

芯片尺寸封装 Download PDF

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Publication number
CN206742235U
CN206742235U CN201720595077.7U CN201720595077U CN206742235U CN 206742235 U CN206742235 U CN 206742235U CN 201720595077 U CN201720595077 U CN 201720595077U CN 206742235 U CN206742235 U CN 206742235U
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wafer
chip size
size packages
metallization
semiconductor element
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林育圣
王松伟
周志雄
F·J·卡尼
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

本实用新型涉及芯片尺寸封装。所述芯片尺寸封装包括：半导体管芯；位于所述管芯的第一表面上的聚合物树脂涂层；位于所述管芯的所述第一表面上的金属化；位于所述金属化上的焊料单元；以及位于所述管芯的第二表面上的压模。本实用新型解决的一个技术问题是改进芯片尺寸封装。本实用新型实现的一个技术效果是提供改进的芯片尺寸封装。

Description

芯片尺寸封装
技术领域
本实用新型涉及半导体装置，以及更具体地，涉及芯片尺寸封装。
背景技术
半导体管芯(还称为“芯片”)通常包封在封装内以避免物理损坏和侵蚀。当前封装工艺通常费时且需要相对昂贵的材料(例如，引线框架和金线)。此外，这些工艺得到的封装会限制管芯尺寸——例如，由于由于存在必须用来容纳管芯的大旗标。
实用新型内容
本实用新型解决的一个技术问题是改进芯片尺寸封装。
在至少一些实施方案中，芯片尺寸封装包括：半导体管芯；位于管芯的第一表面上的聚合物树脂涂层；位于管芯的第一表面上的金属化；位于所述金属化上的焊料单元；以及位于管芯的第二表面上的压模。可使用以下概念中的一个或多个，以任何次序或以任何组合来补充这些实施方案中的至少一些：其中聚合物树脂涂层选自由以下各项构成的组中：聚酰亚胺(PI)和聚苯并恶唑(PBO)；其中半导体管芯具有至少一个阶梯状侧面；其中聚合物树脂涂层位于管芯的侧面的至少部分上，并且其中所述侧面的至少部分位于与第一表面所在的平面正交的平面中；其中压模位于管芯的侧面的至少部分上，并且其中所述侧面的至少部分位于与第二表面所在的平面正交的平面中；其中焊料单元为焊球；其中焊料单元为回流焊凸点；其中金属化选自由以下项构成的组中：化学镍和金镀层；以及铜镀层；其中所述压模包含选自由以下项构成的组中的材料：聚酰胺、聚酰亚胺、聚酰胺-酰亚胺、聚苯硫醚(PPS)、聚醚醚酮(PEEK)和聚酯玻璃纤维树脂。
在至少一些实施方案中，芯片尺寸封装包括：具有顶表面、底表面和侧表面的半导体管芯；位于半导体管芯的所述顶表面上的金属化；以及位于管芯的所述底表面上、位于管芯的所述侧表面上以及位于管芯的顶表面的一部分上的压模，其中所述部分为沿顶表面的周边的至少部分的条带。可使用以下概念中的一个或多个，以任何次序或以任何组合来补充这些实施方案：其中所述条带具有介于40微米(含)与60微米(含)之间的平均宽度；其中所述条带占据顶表面的总面积的介于20％(含)与40％(含)之间；其中压模由选自由以下项构成的组中的材料制成：聚酰胺、聚酰亚胺、聚酰胺-酰亚胺、聚苯硫醚(PPS)、聚醚醚酮(PEEK)和聚酯玻璃纤维树脂；其中顶表面和底表面彼此相对。
本实用新型实现的一个技术效果是提供改进的芯片尺寸封装。
附图说明
在附图中：
图1A至图1I为示出了芯片封装工艺流程的剖视示意图。
图2为如图1A至图1I所示的用于封装芯片的方法的流程图。
图3A至图3J为示出了替代的芯片封装工艺流程的剖视示意图。
图4为如图3A至图3J所示的用于封装芯片的方法的流程图。
图5A至图5K为示出了替代的芯片封装工艺流程的剖视示意图。
图6为如图5A至图5K所示的用于封装芯片的方法的流程图。
然而，应当理解，附图中给定的具体实施方案以及对它们的详细描述并不限制本公开。相反，这些实施方案和详细描述为本领域技术人员提供了识别替代形式、等价形式和修改形式的基础，这些替代形式、等价形式和修改形式与给定实施方案中的一个或多个一起被包含在所附权利要求书的范围内。如本文所用，术语“耦接”是指直接或间接连接。
具体实施方式
本文公开了用于有效地封装半导体管芯的技术。相对于许多当前技术中使用的材料量，这些技术减少了所使用的封装材料量，由此缩减了成本。此外，根据这些技术制作的封装所容纳的管芯在封装中的可用空间占用百分比会大于通常的百分比，很大部分是因为减少了包封所需的材料。这些技术通常涉及减薄晶圆并借助掩模蚀刻晶圆的第一表面以构建随后使用合适的聚合物树脂填充的沟槽。第一表面的掩模区域使用化学镍和金镀层或铜镀层来金属化。底沟槽被蚀刻到晶圆的相对的表面中并且使用合适的包封模来填充。这样就形成了芯片尺寸封装。然后标记封装，并且在金属化上沉积焊料单元(例如，焊球或者印刷单元)。就印刷焊料单元而言，对这些单元执行回流焊以形成焊料凸点。然后沿蚀刻的沟槽切割晶圆以构建多个、经切割的芯片尺寸封装。替代技术提供了另外的优点，诸如防止焊料上锡到晶圆侧面并发生不理想的电气连接。此类技术通常涉及提供具有合适金属化的晶圆并且将压模施加到晶圆的底表面、晶圆的侧表面以及晶圆的顶表面的周边。现在描述这些以及其他技术。
图1A至图1I示出了根据各种实施方案的芯片封装工艺流程的剖视图，并且图2为如图1A至图1I所示的用于封装芯片的方法200的流程图。相应地，在图1A至图1I的背景下描述图2中所示的步骤。方法200始于减薄晶圆(步骤202)。该步骤在对应的图1A中被示出为减薄的晶圆102。晶圆102可由任何合适的半导体材料构成，所述半导体材料例如为但不限于硅、锗或镓。晶圆102使用任何合适的方法来减薄，所述合适的方法例如为但不限于机械研磨、化学机械抛光(CMP)、湿法蚀刻或常压等离子干法化学蚀刻(ADP-DCE)。然而，方法200不限于这些减薄技术，并且任何以及所有合适的减薄技术都包括在本公开的范围内。
在至少一些实施方案中，晶圆102为超薄晶圆。在至少一些实施方案中，晶圆102的厚度介于100微米与250微米之间，但可预期其他厚度。在一些实施方案中，晶圆102包括TAIKO环，使得晶圆102的周边具有比晶圆102的中心更大的厚度。(如本文所用，术语“周边”通常是指晶圆的顶表面或底表面的靠近该表面的边缘的部分。)例如，在使用了TAIKO环的一些此类实施方案中，环沿晶圆102的周边在宽度上介于大约(即，在15％以内)3mm与5mm之间，并且晶圆102的其余部分具有较小的厚度。然而，TAIKO环不是必需的，并且在一些实施方案中，不使用TAIKO环。图1A，与其余的图1B至图1I一样，仅示出了整个晶圆102的一部分。
方法200然后包括在晶圆的第一(即，顶)表面中蚀刻一个或多个沟槽(步骤204)。该步骤在图1B中示出，其中多个沟槽104被蚀刻到晶圆102的第一表面中。如上所述，图1B(以及其他工艺流程图)中所示的视图仅为总晶圆102的一部分。因此，尽管仅示出了两个示例性沟槽104，但晶圆102实际上可具有每晶圆数十个、数百个、数千个或者更多的沟槽。在至少一些实施方案中，沟槽104使用合适的蚀刻技术来形成，所述合适的蚀刻技术诸如为但不限于深反应离子蚀刻(DRIE)和窄锯道蚀刻(NSS)。然而，方法200不限于这些具体的蚀刻技术，并且可预期其他蚀刻技术并且这些蚀刻技术落在本公开的范围内。此外，尽管沟槽的宽度可根据需要改变，但在至少一些实施方案中，沟槽104为80微米宽。类似地，尽管沟槽的深度可根据需要改变，但在一些实施方案中，沟槽104为50微米深。
方法200接下来包括将掩模施加到第一表面并且在第一表面的被掩模暴露的区域上沉积聚合物树脂(步骤206)。该步骤在图1C中示出，其中根据所使用的掩模，在晶圆102的第一表面(包括沟槽104)上沉积多个聚合物树脂段106。掩模可为任何合适的掩模，诸如焊接掩模，并且它可根据需要形成以容纳受掩模保护的区域108中的金属化。聚合物树脂106可包括聚酰亚胺(PI)和/或聚苯并恶唑(PBO)，但本公开的范围并不仅限于此。另外，尽管图1C中的视图示出了树脂106和掩模区域108的具体图案，但在观察同一晶圆102的其他截面段时，该图案可改变。聚合物树脂层106的厚度可改变，但在一些实施方案中，该厚度介于大约25微米与75微米之间。
方法200随后包括将金属化施加到第一表面的被掩模覆盖的区域(步骤208)。该步骤在图1D中示出。在图1D中，先前受到步骤206的掩模保护的区域108填充有金属化110。所使用的金属化的类型可改变并根据需要选择。在一些实施方案中，金属化包括化学镍和金镀层。在一些实施方案中，金属化包括铜镀层。也可使用其他类型的金属化，并且所述金属化可包括适合用在芯片尺寸封装应用中的任何类型的导电材料。步骤208包括对区域108的任何必要的预处理以便容纳图1D所示的化学镀层。
在步骤210中，方法200包括在晶圆的第二(即，底)表面中蚀刻一个或多个沟槽。该步骤在图1E中示出，其中沟槽112形成在晶圆102的第二表面中。在一些实施方案中，沟槽112与沟槽104竖直对齐，如图1B和图1E所示。在一些实施方案中，沟槽112具有比沟槽104窄的宽度(例如，40微米)，但本公开的范围并不仅限于此。在至少一些实施方案中，沟槽112比沟槽104深(例如，为100微米)，但可预期其他深度。沟槽112优选地足够深，使得它们到达沟槽104中的聚合物树脂106——即，使得沟槽104和112相连。蚀刻步骤210可使用任何合适的蚀刻技术来执行，但在至少一些实施方案中，它适用DRIE或NSS来执行。此外，在蚀刻之前，可用光刻胶涂覆晶圆102的第二表面，使得第二表面的将不蚀刻的区域受到保护并且使得对应于沟槽112的区域暴露。
方法200的下一个步骤212包括将压模施加到晶圆的第二表面。图1F示出了该步骤。具体地讲，压模114被形成为匹配晶圆102的底表面，包括沟槽112。压模114应覆盖晶圆102的底表面的一些或全部，并且它应完全填充沟槽112，但可预期其他压模。在至少一些实施方案中，沉积在晶圆102的第二表面上但位于沟槽112之外的压模114具有介于大约25微米至75微米之间的厚度，但该厚度可改变。可使用任何合适的压模材料，包括但不限于聚酰胺、聚酰亚胺、聚酰胺-酰亚胺、聚苯硫醚(PPS)、聚醚醚酮(PEEK)和/或聚酯玻璃纤维树脂系统。
方法200然后包括使用任何合适的信息来标记封装(步骤214；图1G)，所述信息包括部件号、适当的商标、专利号等。接下来，方法200包括在金属化上投放焊球(步骤216)。该步骤在图1H中示出，其中焊球116沉积在金属化110上。在一些实施方案中，将多个焊球116沉积在同一金属化上，并且在此类实施方案中，焊球116以任何合适的间距间隔。焊球116可根据需要设定尺寸，但在至少一些实施方案中，焊球116完全覆盖其所投放的金属化110的宽度。然后使用例如金刚石刀片沿沟槽104和112执行切割，如图1I中的线118所示(步骤218)。在至少一些实施方案中，在沟槽104和112的宽度的中点处执行该切割。步骤218的结果是，单个晶圆102被划分成一个或多个芯片尺寸封装。所得到的芯片尺寸封装容纳晶圆102的一部分、金属化110、以及金属化110上的焊球116。晶圆102由位于晶圆102的相对表面上的聚合物树脂106和压模114完全包封。晶圆102的侧面由于沟槽104和112的形状而为阶梯状，并且晶圆102中的每个所述侧面由聚合物树脂106和压模114包封。方法200可根据需要调节，包括通过添加、删除或修改一个或多个步骤。
图3A至图3J示出了替代的芯片封装工艺流程。图4为如图3A至图3J所示的用于制作芯片尺寸封装的方法400的流程图。由于方法400的步骤在图3A至图3J中示出，因此彼此相关地描述这些图。方法步骤402、404、406、408、410、412和414与图2的方法步骤202、204、206、208、210、212和214类似或相同。步骤402、404、406、408、410、412和414分别在图3A至图3G中示出。
步骤416包括将焊料单元印刷在金属化上。该步骤在图3H中示出，其中焊料单元300印刷到金属化110上。印刷焊料单元是通常比投放焊球更具成本效益的技术。在一些实施方案中，印刷焊料单元300的宽度与金属化110的宽度相同，印刷焊料单元300印刷在金属化110上，但本公开的范围并不仅限于此。
在步骤418中，对印刷焊料单元300执行回流焊以形成焊料凸点302，如图3I所示。最后，然后使用例如金刚石刀片沿沟槽104和112切割晶圆102，如图3J中的线118所示(步骤420)。在至少一些实施方案中，在沟槽104和112的宽度的中点处执行该切割。步骤420的结果是，单个晶圆102被划分成一个或多个芯片尺寸封装。所得到的芯片尺寸封装容纳晶圆102的一部分、金属化110、以及金属化110上的焊料凸点302。晶圆102由位于晶圆102的相对表面上的聚合物树脂106和压模114完全包封。晶圆102的侧面由于沟槽104和112的形状而为阶梯状，并且晶圆102中的每个所述侧面由聚合物树脂106和压模114包封。方法400可根据需要调节，包括通过添加、删除或修改一个或多个步骤。
图5A至图5K示出了替代的芯片封装工艺流程。图6为如图5A至图5K所示的用于制作芯片尺寸封装的方法600的流程图。由于方法600的步骤在图5A至图5K中示出，因此彼此相关地描述这些图。方法600始于使用溅射技术来将金属层沉积在晶圆上(步骤602)。图5A示出了沉积在晶圆500的顶表面上的金属层502。金属层502包含任何合适的材料，包括例如但不限于锡、铜、或它们的合金。尽管金属层502可使用溅射技术来沉积，但本公开的范围不限于任何具体的沉积技术。金属层502的厚度可根据需要选择，但在至少一些实施方案中，该厚度为大约5微米。
方法600然后包括将光刻胶施加到金属层(步骤604)。图5B示出了该步骤——具体地讲，它示出了沉积在金属层502上的光刻胶504，而该金属层继而沉积在晶圆500上。光刻胶504以一定图案(例如，使用掩模)沉积，使得被光刻胶504暴露的区域是随后在其上可沉积金属化的那些区域。光刻胶的厚度改变，但在至少一些实施方案中，该厚度为大约40微米。方法600接下来包括施加金属化(步骤606)。如图5C所示，金属化506沉积到金属层502的被光刻胶504暴露的区域。所使用的具体金属化图案因应用而异并且可根据需要形成。在至少一些实施方案中，金属化506具有40微米的大致厚度以及40微米的大致宽度。
方法600还包括移除光刻胶(步骤608；图5D)并且使用任何合适的蚀刻技术蚀刻掉金属层(步骤610；图5E)，所述蚀刻技术诸如为但不限于干法化学蚀刻技术、DRIE技术或NSS技术。如图5E所示，只保留金属层502的位于金属化506下方的部分。然后使晶圆500的底表面经受背磨工艺以减薄晶圆，如图5F中的标号508所示(步骤612)。在背磨工艺完成后，晶圆500可具有大约200微米的示例性厚度。
然后将第一胶带512施加到晶圆500的底表面(步骤614；图5G)，并且使用机械锯或光刻胶(例如，硅光刻胶)，结合合适的蚀刻技术(例如，DRIE或NSS)，来将晶圆划分成多块(步骤616；图5G)。在至少一些实施方案中，胶带512具有大约20微米的厚度并且由任何合适的材料诸如丙烯酸酯聚合物构成。接下来，方法600包括翻转晶圆块并将第二胶带514施加到晶圆块的顶表面(步骤618；图5H)。尽管晶圆已划分成块，但这些块是轻松地且同时地翻转，因为胶带512在翻转过程期间将晶圆块保持在适当位置。在施加第二胶带514之后，移除第一胶带512(步骤620；图5H)。
第二胶带514可具有任何合适的厚度(例如，大约100-150微米)。在至少一些实施方案中，第二胶带514包括热敏胶带或紫外线固化胶带。第二胶带514提供的粘附度可基于所使用的热量程度(就热敏胶带而言)或者所执行的紫外线固化程度(在UV固化胶带中)而改变，但粘附度优选地为使得当如步骤622和图5I所示施加压模518时，压模的至少一部分在第二胶带514与晶圆500的顶表面之间渗漏以形成“包胶模”。在图5I中，标号520示出了这种包胶模。为了实现包胶模520，可动态地调节施加压模的压力以及压模自身的粘度，其中考虑第二胶带514提供的粘附度。包胶模520的宽度可改变，但在至少一些实施方案中，该宽度为大约200-250微米。类似地，包胶模520的厚度改变，但在至少一些实施方案中，该厚度为大约20微米。在至少一些实施方案中，压缩模塑包括任何合适的材料(例如，聚酰胺、聚酰亚胺、聚酰胺-酰亚胺、聚苯硫醚(PPS)、聚醚醚酮(PEEK)和聚酯玻璃纤维树脂)。
在施加压模518之后，施加第三胶带522，移除第二胶带514，并且翻转晶圆组件(步骤624；图5J)。在至少一些实施方案中，第三胶带522由与胶带512相同的材料构成。方法600还包括执行切割技术(例如，使用金刚石刀片)以将晶圆块划分成单独的芯片尺寸封装，如图5J中的标号524和526所示(步骤626)。最后，方法600包括移除第三胶带522(步骤628；图5K)。经切割的芯片尺寸封装包括晶圆的底表面和侧表面上的压缩模塑，并且它还包括晶圆顶表面的一部分上的压缩模塑(即，包胶模520)。在至少一些实施方案中，晶圆顶表面上的压缩模塑形成围绕顶表面的周边的一个或多个条带。在至少一些实施方案中，条带具有大约40-60微米的平均宽度。在至少一些实施方案中，条带占据顶表面的介于20％与40％之间的总面积。如果压缩模塑沿循晶圆表面的周边并且占据不超过一半的该表面的面积，则压缩模塑被认为是以“条带”形式或者沿晶圆表面的“周边”施加。
在至少一些实施方案中，一种用于制造芯片尺寸封装的方法包括：提供晶圆；将聚合物树脂施加在晶圆的第一表面的至少部分上以及施加到晶圆的一个或多个侧面；以及将压模施加在晶圆的第二表面的至少部分上以及施加到晶圆的一个或多个侧面，所述第一表面和所述第二表面彼此相对。可使用以下概念中的一个或多个，以任何次序或以任何组合来补充这些实施方案：减薄所述晶圆；在晶圆的所述第一表面中蚀刻一个或多个沟槽；将掩模施加到所述第一表面以便利聚合物树脂的所述施加，其中所述聚合物树脂的至少一些填充所述一个或多个沟槽的至少一部分；使用掩模对第一表面的区域施加金属化；在第二表面中蚀刻一个或多个沟槽以容纳所述压模的至少一部分；在所述金属化上沉积一个或多个焊料单元；以及沿晶圆的第一表面和第二表面中的所述一个或多个沟槽切割以制作芯片尺寸封装；其中减薄晶圆包括实现100微米至250微米的平均晶圆厚度；其中减薄晶圆包括实现沿晶圆周边的晶圆厚度大于晶圆中心处的晶圆的另一个厚度；其中施加所述金属化包括使用铜或者镍和金的组合来执行化学镀层；在第二表面中蚀刻所述一个或多个沟槽之前，将光刻胶涂层施加到第二表面；其中在第二表面中蚀刻一个或多个沟槽包括穿过晶圆蚀刻到容纳在第一表面中的所述一个或多个沟槽中的聚合物树脂；其中所述一个或多个焊料单元为焊球；其中所述一个或多个焊料单元被印刷到金属化上，并且还包括对所述焊料单元执行回流焊以形成焊料凸点；其中在第二表面中蚀刻所述一个或多个沟槽包括使用选自由以下蚀刻技术构成的组中的蚀刻技术：深反应离子蚀刻(DRIE)和窄锯道蚀刻(NSS)；还包括在第一表面中蚀刻一个或多个沟槽以容纳所述聚合物树脂的至少一些，所述蚀刻使用选自由以下蚀刻技术构成的组中的蚀刻技术来执行：深反应离子蚀刻(DRIE)和窄锯道蚀刻(NSS)；其中所述聚合物树脂选自由以下各项构成的组中：聚酰亚胺(PI)和聚苯并恶唑(PBO)。
至少一些实施方案涉及一种用于制造芯片尺寸封装的方法，该方法包括：提供在顶表面上具有金属化的晶圆；以及将压模施加到所述晶圆的底表面、所述晶圆的侧表面以及晶圆的所述顶表面的周边。可使用以下概念中的一个或多个，以任何次序或以任何组合来补充这些实施方案：还包括将胶带施加到所述顶表面，并且其中施加所述压模包括使用足够的压力以使所述压模的至少一些在所述胶带与所述顶表面之间渗漏；其中施加到所述顶表面的所述周边的所述压模形成一个或多个条带，所述一个或多个条带具有介于40微米(含)与60微米(含)之间的平均宽度；还包括：使用溅射技术在所述顶表面上沉积金属层，使用光刻胶在顶表面上沉积所述金属层，蚀刻掉所述金属层的至少部分，对所述底表面进行背磨，将第一胶带施加到所述底表面，将晶圆划分成多块，翻转晶圆块并将第二胶带施加到所述块的顶表面，移除第一胶带，在施加所述压模之后移除第二胶带；以及制作经切割的芯片尺寸封装。
一旦完全理解了上述公开的内容，对于本领域技术人员来说许多其他变型形式和修改形式就将变得显而易见。以下权利要求书被解释为旨在包含所有此类变型形式、修改形式和等同形式。

Claims (10)

1.一种芯片尺寸封装，包括：
半导体管芯；
位于所述管芯的第一表面上的聚合物树脂涂层；
位于所述管芯的所述第一表面上的金属化；
位于所述金属化上的焊料单元；以及
位于所述管芯的第二表面上的压模。
2.根据权利要求1所述的芯片尺寸封装，其中所述聚合物树脂涂层选自由以下项构成的组中：聚酰亚胺(PI)和聚苯并恶唑(PBO)。
3.根据权利要求1所述的芯片尺寸封装，其中所述半导体管芯具有至少一个阶梯状侧面。
4.根据权利要求1所述的芯片尺寸封装，其中所述聚合物树脂涂层位于所述管芯的侧面的至少部分上，并且其中所述侧面的至少部分位于与所述第一表面所在的平面正交的平面中。
5.根据权利要求1所述的芯片尺寸封装，其中所述压模位于所述管芯的侧面的至少部分上，并且其中所述侧面的至少部分位于与所述第二表面所在的平面正交的平面中。
6.根据权利要求1所述的芯片尺寸封装，其中所述焊料单元为焊球。
7.根据权利要求1所述的芯片尺寸封装，其中所述焊料单元为回流焊凸点。
8.根据权利要求1所述的芯片尺寸封装，其中所述金属化选自由以下项构成的组中：化学镍和金镀层；以及铜镀层。
9.一种芯片尺寸封装，包括：
半导体管芯，所述半导体管芯具有顶表面、底表面和侧表面；
金属化，所述金属化位于所述半导体管芯的所述顶表面上；以及
压模，所述压模位于所述半导体管芯的所述底表面上、位于所述半导体管芯的所述侧表面上以及位于所述半导体管芯的所述顶表面的部分上，
其中所述部分为沿所述顶表面的周边的至少部分的条带。
10.根据权利要求9所述的芯片尺寸封装，其中所述顶表面和所述底表面彼此相对。
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