CN206389353U - A kind of pretreatment circuit of increment type sine and cosine encoder signal - Google Patents
A kind of pretreatment circuit of increment type sine and cosine encoder signal Download PDFInfo
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Abstract
The utility model discloses a kind of pretreatment circuit of increment type sine and cosine encoder signal, it exports the preprocessed signal with safety and redundancy feature.Two scaling difference shaping circuits increment signal A+ and A sinusoidal to a pair, a pair of cosine incremental signals B+ and B, difference shaping, scaling generation Asin α, Bcos α are carried out respectively, and A phase sinusoidal signal Asin α and B phase cosine signal Bcos α phase differs 90 °.Corresponding analog quantity add operation is done by adder, subtracter, phase inverter again and exports Asin (+45 ° of α) and-Bcos (+45 ° of α).Asin α and Bcos α are converted to respective rectangular ripple signal by two comparators, and carry out redundancy respectively.Last scaling difference shaping circuit to a pair of reference points increment signal R+ and R, carry out difference shaping, it is scaling after reference point R square-wave signals are converted to by last comparator again.
Description
Technical Field
The utility model relates to a preprocessing circuit especially relates to a preprocessing circuit of incremental sine and cosine encoder signal.
Background
Signal preprocessing is the general term for preprocessing various types of electrical signals, and is the general term for processing according to various expected purposes and requirements, i.e. the process of processing signals recorded on a certain medium to extract useful information, and is the general term for the processing processes of extracting, transforming, analyzing, synthesizing and the like of signals.
The sine-cosine encoder has to pre-process the encoder's raw signal before performing coarse position counting or fine position interpolation. On one hand, the preprocessing circuit provides an ideal square wave signal source for a coarse position counting unit (coarse position counting, namely, 4-time frequency multiplication is carried out on square wave signals firstly, and then the real-time position of a motor rotor is calculated) in a subsequent DSP (digital signal processor); on the other hand, the preprocessing circuit provides an ideal analog signal source for a precise position interpolation unit in a subsequent DSP. The so-called accurate position interpolation is to divide one period of the analog signal into a plurality of equal signal segments by time division, wherein one period of the analog signal only generates one trigger pulse, and a plurality of trigger pulses are generated after the analog signal is divided into a plurality of equal signal segments by interpolation. The resolution of the counting system is improved. For example, the number of lines of a certain type of sine and cosine encoder is 2048 (2048 signal cycles generated per revolution), and after 4 times of frequency multiplication, the physical resolution is one cycle/4 of analog signal/360 × 3600/(2048 × 4) ═ 158.203125 arc seconds, and this value is the resolution of the position counting of the motor rotor by the coarse position counting unit in the DSP. The traditional square wave signal processing method and circuit for the encoder cannot obtain higher resolution of a rotor position counting system because the concept of 4 times of frequency cannot be broken through (more times of frequency will distort position signals).
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a preprocessing circuit of incremental sine and cosine encoder signal, its output has safety and redundant function's preprocessing signal.
The utility model discloses a solution is: a preprocessing circuit of incremental sine and cosine encoder signals is used for outputting preprocessed signals with safety and redundancy functions; the device comprises an adder, a subtracter, a phase inverter, three proportional amplification differential shaping circuits and three comparators; wherein,
the proportional amplification differential shaping circuit is used for carrying out differential shaping and proportional amplification on a pair of sine incremental signals A + and A-output by a pair of incremental sine and cosine encoders to generate an A-phase sine signal Asin alpha;
the proportional amplification differential shaping circuit carries out differential shaping and proportional amplification on a pair of cosine incremental signals B + and B-output by the two pairs of incremental sine and cosine encoders to generate a B-phase cosine signal Bcos alpha; the phase difference between the A-phase sinusoidal signal Asin alpha and the B-phase cosine signal Bcos alpha is 90 degrees;
the adder adds the A-phase sine signal Asin α and the B-phase cosine signal Bcos α to form an analog quantity addition operation(α +45 deg.), and multiplying by a factorObtaining an A-phase 45-degree phase-shifted signal Asin (α +45 degrees) which is phase-shifted by 45 degrees relative to the A-phase sinusoidal signal Asin α;
the subtracter subtracts the A-phase sinusoidal signal Asin α from the B-phase sinusoidal signal Bcos α to form an analog subtraction(α +45 deg.), and multiplying by a factorObtaining a B-phase 45-degree phase shift signal Bcos (α +45 degrees) which is shifted by 45 degrees relative to the B-phase complementary chord signal Bcos α;
the inverter inverts the B-phase 45 ° phase shift signal Bcos (α +45 °) to generate an inverted signal-Bcos (α +45 °);
the first comparator converts the A-phase sinusoidal signal Asin alpha into an A-phase rectangular wave signal S _ A _ 1; the A-phase rectangular wave signal S _ A _1 redundantly generates an A-phase rectangular wave redundant signal S _ A _ 2;
the second comparator converts the B-phase cosine signal Bcos alpha into a B-phase rectangular wave signal S _ B _ 1; b-phase rectangular wave signals S _ B _1 are generated redundantly to generate B-phase rectangular wave redundant signals S _ B _ 2;
and a pair of reference point incremental signals R + and R-output by the three pairs of incremental sine and cosine encoders of the proportional amplification differential shaping circuit are subjected to differential shaping and proportional amplification and then converted into a reference point R rectangular wave signal S _ R by a comparator III.
As a further improvement of the above-described aspect, each of the proportional amplifying differential shaping circuits includes a differential shaping circuit that performs differential shaping on an input signal and a proportional amplifying circuit that performs proportional amplification.
As a further improvement of the scheme, each proportional amplification differential shaping circuit comprises resistors R1-R6, a resistor R20, capacitors C1-C5, a capacitor C7 and operational amplifiers U1-U3; a sine increment signal A + is input into the in-phase end of an operational amplifier U1, the sine increment signal A-is input into the in-phase end of an operational amplifier U2, a resistor R1 is connected in series between the two in-phase ends of the operational amplifiers U1 and U2, the two in-phase ends of the operational amplifiers U1 and U2 are respectively connected with capacitors C1 and C2 in parallel, first-order RC filtering is built, and the two inverting ends of the operational amplifiers U1 and U2 are respectively connected with respective output ends to form negative feedback; the output end of the operational amplifier U1 is connected with the in-phase end of the operational amplifier U3 through a resistor R2, the output end of the operational amplifier U2 is connected with the inverting end of the operational amplifier U3 through a resistor R3, the in-phase end of the operational amplifier U3 is grounded through capacitors C4 and C3, a resistor R4 is connected to the capacitor C4 in parallel, and a power supply is connected between the capacitors C4 and C3; the inverting end of the operational amplifier U3 is connected with the output end of the operational amplifier U3 through a capacitor C5, a resistor R5 is connected to the capacitor C5 in parallel, one end of a capacitor C7 is connected between a resistor R6 and the resistor 20, and the other end of the capacitor C7 is grounded; the output end of the operational amplifier U3 is also used as the output end of the proportional amplifying differential shaping circuit through a resistor R6 and a resistor R20.
As a further improvement of the above solution, the non-inverting terminal of the first comparator receives the a-phase sinusoidal signal Asin α, the inverting terminal of the first comparator is connected to the power supply for bias voltage, and is connected to ground via a capacitor C6, and the output terminal of the first comparator outputs the a-phase square wave signal S _ a _ 1.
As a further improvement of the above solution, the non-inverting terminal of the second comparator receives the B-phase cosine signal Bcos α, the inverting terminal of the second comparator is connected to a power supply for bias voltage, and is connected to ground via a capacitor, and the output terminal of the second comparator outputs the B-phase square wave signal S _ B _ 1.
As a further improvement of the above solution, the output terminal of the third proportional amplifying differential shaping circuit is connected to the non-inverting terminal of the third comparator, the inverting terminal of the third comparator is connected to the power supply for serving as a bias voltage, and is grounded via a capacitor, and the output terminal of the third comparator outputs the reference R rectangular wave signal S _ R.
As a further improvement of the scheme, the adder comprises resistors R7-R11, an operational amplifier U5; the A-phase sinusoidal signal Asin alpha and the B-phase cosine signal Bcos alpha are respectively connected with the in-phase end of an operational amplifier U5 through a resistor R7 and a resistor R8, the inverting end of the operational amplifier U5 is grounded through a resistor R10, two ends of a resistor R9 are respectively connected with the inverting end and the output end of an operational amplifier U5, and the output end of the operational amplifier U5 outputs an A-phase 45-degree phase-shift signal Asin (alpha +45 degrees) through a resistor R11.
As a further improvement of the scheme, the subtracter comprises resistors R12-R16 and an operational amplifier U6, wherein an A-phase sinusoidal signal Asin α is connected with the inverting end of the operational amplifier U6 through a resistor R12, a B-phase cosine signal Bcos α is connected with the inverting end of the operational amplifier U6 through a resistor R13, the inverting end of the operational amplifier U6 is grounded through a resistor R14, two ends of a resistor R15 are respectively connected with the inverting end and the output end of the operational amplifier U6, and the output end of the operational amplifier U6 outputs a signal through a resistor R16(α+45°)。
As a further improvement of the scheme, the inverter comprises resistors R17-R19, an operational amplifier U7; signal(α +45 °) is input to the inverting terminal of the operational amplifier U7, the non-inverting terminal of the operational amplifier U7 is grounded via the resistor R17, both ends of the resistor R18 are connected to the inverting terminal and the output terminal of the operational amplifier U7, respectively, and the output terminal of the operational amplifier U7 outputs a B-phase 45 ° phase shift and an inverted signal — Bcos (α +45 °) via the resistor R19.
The utility model discloses in, through the multi-functional signal to incremental sine and cosine encoder signal preliminary treatment and output, for low reaches DSP handles and provides multiple choice, can satisfy the demand of different user different degree, the circuit that the invention relates to can be in FPGA with the hardware description language handle the utility model discloses a circuit design is IPcore, still can the manufacturing design become a standard ASIC chip even, the utility model discloses a basic research of state equipment manufacturing is being promoted in the field, especially to the rotor real-time position precision of carrying out the parts such as improvement alternating current servo permanent magnet synchronous motor, made the biggest contribution.
Drawings
Fig. 1 is a circuit configuration diagram of a preprocessing circuit of an incremental sine and cosine encoder signal.
Fig. 2 is an electrical connection diagram of a first proportional amplifying differential shaping circuit and a first comparator in fig. 1.
Fig. 3 is a diagram of sine and cosine signal waveforms of a phase a and a phase B, which are obtained by MATLAB simulating the differential shaping circuit one and the differential shaping circuit two in fig. 1, respectively, and have a phase difference of 90 degrees.
Fig. 4 is a graph of an a-phase square wave signal from a MATLAB simulation of the first comparator of fig. 1.
Fig. 5 is a circuit diagram of the adder of fig. 1.
Fig. 6 is a waveform diagram of an output signal obtained by simulating the circuit of fig. 4 by MATLAB.
Fig. 7 is a circuit connection diagram of the subtractor and the inverter in fig. 1.
Fig. 8 is a waveform diagram of an output signal obtained by simulating the circuit of fig. 7 by MATLAB.
Fig. 9 is a signal waveform diagram comparing two paths of signals ASin (a +45 °) and Bcos (a +45 °) finally output in MATLAB.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to 9, the preprocessing circuit of the incremental sine and cosine encoder signal of the present invention is used to output a preprocessed signal with safety and redundancy functions, which is a great difference from the conventional preprocessed signal. Referring to fig. 1, the preprocessing circuit includes three proportional amplifying differential shaping circuits 1 to 3, three comparators 4 to 6, an adder 7, a subtractor 8, and an inverter 9.
Each frame of the preprocessed signal comprises the following signals Asin α, Bcos α, Asin (α +45 °), -Bcos (α +45 °), S _ a _1, S _ a _2, S _ B _1, S _ B _2, S _ R.
Asin alpha: the first proportional amplification differential shaping circuit 1 performs differential shaping and proportional amplification on a pair of sine incremental signals A + and A-output by the incremental sine and cosine encoder to generate an A-phase sine signal Asin alpha.
Bcos alpha: and the second proportional amplification differential shaping circuit 2 performs differential shaping and proportional amplification on a pair of cosine incremental signals B + and B-output by the incremental sine-cosine encoder to generate a B-phase cosine signal Bcos alpha, wherein the phase difference between the A-phase sine signal Asin alpha and the B-phase cosine signal Bcos alpha is 90 degrees.
Asin (α +45 degree) adder 7 adds A-phase sine signal Asin α and B-phase cosine signal Bcos α by analog quantity to form signal(α +45 deg.), and multiplying by a factorAn a-phase 45 ° phase-shifted signal Asin (α +45 °) shifted by 45 ° with respect to the a-phase sinusoidal signal Asin α is obtained.
Bcos (α +45 degrees), the subtracter 8 subtracts the A-phase sinusoidal signal Asin α from the B-phase sinusoidal signal Bcos α to form a signal by analog subtraction(α +45 deg.), and multiplying by a factorA B-phase 45 DEG phase shift signal Bcos (α +45 DEG) which is shifted by 45 DEG with respect to the B-phase cosine signal Bcos α is obtained and inverted by an inverter 9 to generate an inverted signal-Bcos (α +45 DEG).
S _ A _ 1: the first comparator converts the a-phase sinusoidal signal Asin α into an a-phase square wave signal S _ a _ 1.
S _ A _ 2: and S _ A _1 carries out redundancy to generate an A-phase square wave redundant signal S _ A _ 2.
S _ B _ 1: the second comparator converts the B-phase cosine signal Bcos alpha into a B-phase square wave signal S _ B _ 1.
S _ B _ 2: and S _ B _1 carries out redundancy to generate a B-phase square wave redundant signal S _ B _ 2.
S _ R: and a pair of reference point incremental signals R + and R-output by the three pairs of incremental sine and cosine encoders of the proportional amplification differential shaping circuit are subjected to differential shaping and proportional amplification and then converted into a reference point R square wave signal S _ R by a comparator III.
It should be noted that the present invention is not focused on these components such as the three proportional amplifying differential shaping circuits 1 to 3, the three comparators 4 to 6, the adder circuit 7, the subtracter 8, and the inverter 9, but means the concept of outputting the preprocessed signals with safety and redundancy functions, which is mainly composed of these components (the three proportional amplifying differential shaping circuits 1 to 3, the three comparators 4 to 6, the adder circuit 7, the subtracter 8, and the inverter 9). As with the circuits, the resistors, inductors, chips, etc. that make up the circuits are inherently present in the art, but their presence does not mean that the circuits made up of them must be obvious and must be a routine choice for those skilled in the art, otherwise the continued innovation of the circuits is hindered and the objectives of the patent laws are violated. The utility model is intended to express here that: by the utility model discloses before applying for, do not retrieve the utility model discloses a such electrical structure of incremental sine and cosine encoder signal's preprocessing circuit designs the utility model discloses an incremental sine and cosine encoder signal's preprocessing circuit need pay out creative work, at least the technical staff in the field has never done so.
According to the Heidenhain encoder interface definition, the typical amplitude of the output voltage signals A and B is 1VPP for a 1VPP sine and cosine delta, with a phase difference of 90 electrical degrees. The interface signals are three pairs of differential signals. In the preprocessing circuit of the present invention, in order to obtain A, B two-phase signals, i.e., a-phase sinusoidal signal Asin α and B-phase cosine signal Bcos α, differential shaping, proportional amplification, etc. is required for the differential signal. Meanwhile, in order to obtain square wave signals (mainly square wave signals) from A, B two-phase signals through a comparator respectively, the obtained high and low levels need to meet the requirements of a sampling chip or an FPGA pin and the like.
Referring to fig. 2, each of the up-scaling differential shaping circuits may include a differential shaping circuit for performing differential shaping on an input signal and a up-scaling circuit for performing up-scaling. In the embodiment, each of the proportional amplifying differential shaping circuits includes resistors R1 to R6, resistor R20, capacitors C1 to C5, capacitor C7, and operational amplifiers U1 to U3.
A sine increment signal A + is input into the in-phase end of an operational amplifier U1, a sine increment signal A-is input into the in-phase end of an operational amplifier U2, a resistor R1 is connected between the two in-phase ends of the operational amplifiers U1 and U2 in series, the two in-phase ends of the operational amplifiers U1 and U2 are respectively connected with capacitors C1 and C2 in parallel, first-order RC filtering is built, and the two inverting ends of the operational amplifiers U1 and U2 are respectively connected with respective output ends to form negative feedback. The output end of the operational amplifier U1 is connected with the non-inverting end of the operational amplifier U3 through a resistor R2, the output end of the operational amplifier U2 is connected with the inverting end of the operational amplifier U3 through a resistor R3, the non-inverting end of the operational amplifier U3 is grounded through capacitors C4 and C3, a resistor R4 is connected to the capacitor C4 in parallel, and a power supply is connected between the capacitors C4 and C3. The inverting end of the operational amplifier U3 is connected with the output end of the operational amplifier U3 through a capacitor C5, a resistor R5 is connected to the capacitor C5 in parallel, one end of a capacitor C7 is connected between a resistor R6 and the resistor 20, and the other end of the capacitor C7 is grounded; the output end of the operational amplifier U3 is also used as the output end of the proportional amplifying differential shaping circuit through a resistor R6 and a resistor R20.
The output end of the first proportional amplifying and differential shaping circuit 1 is connected with the non-inverting end of the first comparator 4, so that the non-inverting end of the first comparator receives the a-phase sinusoidal signal Asin α, the inverting end of the first comparator 4 is connected with a power supply Vcc on one hand and used as a bias voltage, and is connected with the ground through a capacitor C6 on the other hand, and the output end of the first comparator 4 outputs an a-phase square wave signal S _ a _ 1. Similarly, the output terminal of the second proportional amplifying and differential shaping circuit 2 is connected to the non-inverting terminal of the second comparator 5, so that the non-inverting terminal of the second comparator receives the B-phase cosine signal Bcos α, the inverting terminal of the second comparator 5 is connected to a power supply (not shown) for bias voltage, and is grounded via a capacitor (not shown), and the output terminal of the second comparator 5 outputs the B-phase square signal S _ B _ 1. The output end of the third circuit 3 is connected to the non-inverting end of the third comparator 6, the inverting end of the third comparator 6 is connected to a power supply (not shown) for bias voltage, and is grounded via a capacitor (not shown), and the output end of the third comparator 6 outputs the reference point R square-wave signal S _ R.
The A phase and the B phase of the sinusoidal incremental signals from the encoder interface are a pair of differential signals with 90-degree difference and 1V amplitude, and the A phase and the B phase of the differential signals are respectively processed. Taking differential signals A + and A-as an example, the differential signals are respectively amplified by two paths of amplifiers U1 and U2, then the amplified signals enter an amplifier U3 for differential integration, a path of sinusoidal signal Asin alpha is output, the amplitude range is 0V-3.3V, meanwhile, the sinusoidal signal Asin alpha is input into a comparator U4, and a path of signal similar to a square wave can be obtained through bias voltage of 1.5V according to characteristic parameters of the comparator, wherein the amplitude range is 0.4V-2.6V. Fig. 4 and 3 are waveforms of square signals and sine and cosine signals of a phase a and a phase B, which are different in phase by 90 degrees, respectively, obtained by simulating the differential shaping circuit in fig. 1 by MATLAB.
Referring to FIG. 5, the adder includes resistors R7-R11 and an operational amplifier U5. Asin alpha and Bcos alpha are respectively connected with the in-phase end of an operational amplifier U5 through resistors R7 and R8, the inverting end of the operational amplifier U5 is grounded through a resistor R10, the two ends of a resistor R9 are respectively connected with the inverting end and the output end of an operational amplifier U5, and the output end of the operational amplifier U5 outputs Asin (alpha +45 degrees) through a resistor R11.
The part of the circuit is a single circuit of differential shaping, proportional amplification and comparison to generate an A-phase sinusoidal signal Asin α, finally, the A-phase sinusoidal signal Asin α is compared through a bias voltage of 1.5V to output a square wave signal with a low level of 0.4V and a high level of 2.6V, namely the A-phase square wave signal S _ A, an inverting adder circuit 7 outputs a signal with a value of 0.707 (namely the A-phase square wave signal S _ A) through the resistance value of a feedback resistor) Multiplying by the ratio of (c).
Two paths of sine and cosine signals Asin alpha and Bcos alpha with the phase difference of 90 degrees output by the differential shaping circuit are input to the same-direction end of the adder U5, and the amplitudes of the two phases of sine and cosine signals are equal. To satisfy:
the above-described relation coefficients are satisfied by adjusting the resistance values of the resistors R8, R7, R10, and R9 in fig. 5.
According to the virtual break, no current passes through the equidirectional input terminal, so that the current passing through the resistors R8 and R7 is equal, and the current passing through the resistors R10 and R9 is also equal.
Thus:
according to the virtual break, the virtual break is determined,
V+＝V-
this gives:
fig. 6 shows the waveform of the output signal obtained by simulating the circuit by MATLAB, and it can be seen in fig. 6 that the waveform is phase-shifted by 45 ° and the amplitude is increased by about 1.414 times when the signals of the a-phase and the B-phase are input to the same direction end of the adder, and the amplitude is reduced by 0.707 time by adjusting the resistance values of the resistors R8, R7, R10 and R9, so that the waveform of the output signal Asin (α +45 °) can be obtained.
Referring to fig. 7, the subtractor includes resistors R12-R16, an operational amplifier U6. a phase sinusoidal signal Asin α connected to the inverting terminal of the operational amplifier U6 via a resistor R12, a B phase sinusoidal signal Bcos α connected to the inverting terminal of the operational amplifier U6 via a resistor R13, the inverting terminal of the operational amplifier U6 connected to the ground via a resistor R14, two terminals of the resistor R15 connected to the inverting terminal and the output terminal of the operational amplifier U6, respectively, and the output terminal of the operational amplifier U6 outputting a signal via a resistor R16(α+45°)。
The inverter comprises resistors R17-R19 and an operational amplifier U7. Signal(α +45 °) is input into the inverting terminal of operational amplifier U7, the non-inverting terminal of operational amplifier U7 is grounded via resistor R17, the two ends of resistor R18 are connected to the inverting terminal and output terminal of operational amplifier U7, respectively, and the output terminal of operational amplifier U7 outputs B-phase via resistor R19The 45 ° phase shift and inversion signal-Bcos (α +45 °).
For the precise position interpolation unit in the DSP, time division interpolation is performed on one period of the analog signal, for example, the period is divided into 8 equal parts, and then the resolution after interpolation is one period/8 of the analog signal 360 × 3600/(2048 × 8) 79.1015625 arc seconds, which is the resolution of the rotor position counting system obtained after 8 equal division interpolation subdivision is performed on one signal period, obviously, the resolution is improved by 1 time compared with the resolution of the coarse position counting. For another example, if a high-precision CNC machine requires a rotor position accuracy of ± 5 arc seconds, the number of interpolation sub-divisions of one signal period is 360 × 3600/(2 × 5 × 2048) ═ 63.28125, that is, only 64 equal divisions of interpolation processing need be performed on one signal period, so that a rotor position accuracy of less than ± 5 arc seconds can be obtained.
In addition to receiving the signals Asin alpha and Bcos alpha from the preprocessing circuit and performing real-time position and real-time speed calculation of the rotor according to the signals (providing a calculation function of rough position counting and precise position interpolation of the real-time position of the rotor of the motor), the DSP also receives safety signals Asin (alpha + 45) DEG and-Bcos (alpha +45 DEG) from the preprocessing circuit and performs real-time position and real-time speed calculation of the rotor again according to the safety signals, and the DSP performs cross comparison on two calculation results of the real-time position and the real-time speed of the rotor and performs safety operation on the comparison result.
Two paths of sine and cosine signals Asin alpha and Bcos alpha with the phase difference of 90 degrees output by the differential shaping circuit are input to different direction ends of the subtracter, the amplitudes of the two-phase sine and cosine signals are equal, and the obtained output signals are input to the phase inverter for phase inversion. To satisfy:
the above-described relation coefficients are satisfied by adjusting the resistance values of the resistors R13, R12, R14, and R15 in fig. 7.
According to the virtual break, no current passes through the U6 uni-directional input terminal, resulting in equal current through resistors R12 and R13 and equal current through resistors R14 and R15.
Thus:
according to the virtual break, the virtual break is determined,
V+＝V_
this gives:
the cosine signal with the amplitude increased by about 1.414 times is input into an inverter, the amplitude is reduced by 0.707 time by adjusting the resistance values of the resistors R16 and R18, and the phase is inverted by 180 degrees.
In U7, the equidirectional end of the operational amplifier is grounded. According to the virtual short, the reverse terminal voltage is 0V. According to the virtual break, a high resistor is input into the reverse input end, almost no current is input and output, the resistors R16 and R18 are connected in series, and the currents passing through the resistors R16 and R18 are equal.
Current through resistor R16:
current through resistor R18: i is7＝(V--Vout)/R18
According to the virtual interruption, V+＝V_
This gives:
FIG. 8 is a diagram of the output signal waveform obtained by simulating the circuit of FIG. 7 by MATLAB, in which it can be seen that the A-phase and B-phase two-phase signals are input to the subtracter at different terminals, and after being processed by the subtracter, the waveform is shifted by 45 °, and the amplitude is increased by about 1.414 times by adjusting the resistance values of R13, R12, R14 and R15, so as to obtain the output signalThe waveform of (α +45 °) the amplitude is reduced by 0.707 times by adjusting the resistance values of R16 and R18, and the phase is inverted, so that the waveform of the output signal-Bcos (α +45 °) can be obtained.
Fig. 9 is a diagram of comparing two final output signals Asin (α +45 °) and Bcos (α +45 °) in MATLAB, where the two sine and cosine signals Asin (α +45 °) and Bcos (α +45 °) have a phase difference of 135 ° after being processed by an adder, a subtractor, and an inverter from the starting point of the output signals, but the processed signals have a phase difference of 90 ° as well as the two phase signals of phase a and phase B from the continuity of the signals. Therefore, the phase difference at the beginning of the signal is negligible.
The processing of the encoder signals includes DSP processing (coarse position counting and fine position interpolation) and encoder signal pre-processing. Especially, the processing of the incremental sine and cosine encoder signals is a key and only way for obtaining the real-time position (especially the high-resolution real-time position) of the rotor of the servo motor, and is a necessary material basis for improving the precision of a servo shaft (comprising a linear shaft and a rotating shaft) by executing components such as a high-precision CNC machine tool, a servo manipulator, a numerical control rotary table, a multifunctional numerical control angle milling head, an electric spindle and the like. The processing (counting and safety) and digitization of encoder signals are always technical shortcuts in the national equipment manufacturing industry, and have been raised to the national height in order to break through the technical monopoly in the west and improve the position detection and feedback precision of high-grade numerical control machines and alternating current servo transmission in China. The document of the innovative development engineering implementation of intelligent manufacturing equipment (development technology 2014 2072) requires the realization of full digitalization of an internal control and measurement unit of an alternating current servo drive in the description of the full digital alternating current servo system. The internal control and measurement unit of the AC servo drive mentioned in the document refers to the AC servo permanent magnet synchronous motor and the sine and cosine signal encoder in the motor which are widely used in the CNC field. It can be seen that the significance of the processing of the sine and cosine signal encoder signal is important.
There are a lot of documents that propose circuits or methods for performing 4-fold frequency on square-wave signals of encoders (mainly TTL signal encoders) and then performing coarse position counting; there are few documents that perform squaring processing on the analog signal of the sine and cosine encoder, convert the processed analog signal into a square wave signal, and then perform coarse position counting by using a similar method for processing the square wave signal encoder, for example, patent documents ZL201520574867.8, ZL201520570360.5, 201510465550.5, 201510467898.8, 201510465547.3, 201610517319.0, 201610518856.7, 2016120690307.3 (hereinafter referred to as patent document combination) refer to a method for converting the analog signal of the sine and cosine encoder into a square wave signal and then performing coarse position counting; the patent literature combination also mentions a process flow of performing phase shift equal to preprocessing on the analog signal of the sine and cosine encoder and then performing accurate position interpolation by using a DSP (digital signal processor), so as to obtain a more accurate real-time position of the rotor of the servo motor; the patent literature group also mentions the process flow of the safety encoder signal. The patent literature combination does not suggest a detailed implementation method of the preprocessing circuit and a theoretical basis for its implementation.
In addition, in order to strengthen the secrecy of the preprocessing and post-processing of the encoder signals, developed countries adopt a more effective method than the patenting, namely, an IP core for the preprocessing and post-processing of the encoder signals is designed, a design circuit and an algorithm are packaged into the IP core, and a user can not know why the IP core is used when purchasing and using the IP core; even designing and manufacturing special ASIC chips.
The processing of the encoder signals comprises two parts, namely DSP processing and encoder signal preprocessing, wherein the two parts have very important functions and are absent. The DSP processing is mainly responsible for algorithm processing and is a theoretical basis; the encoder signal pre-processing is responsible for providing a suitable signal source for the DSP algorithm and is a material basis. The utility model provides a preliminary treatment to incremental sine and cosine encoder signal is responsible for providing the signal source for DSP handles (not describe in the present case), and concrete content is: the A +, A-, B +, B-, R +, R-six original paths (the symbol A, B, R used in the utility model is used in the text is only used for distinguishing signal phases, does not have amplitude meaning, and the following is the same), the incremental sine and cosine encoder differential signal (amplitude 1VPP) generates 9 paths of signals after passing through the preprocessing circuit of the encoder signal, and the signals are provided for the DSP processing unit, and the square wave signals S _ B _1 and S _ A _1 are provided for the first rough position counting (not in the present case) of the DSP processing unit and are used for roughly counting the real-time position of the rotor of the servo motor; square wave signals S _ B _2 and S _ A _2 are provided for a second rough position count (not in the present case) of the DSP processing unit, and are used for roughly counting the real-time position of the rotor of the servo motor, and performing safety operation and CRC redundancy check on the first and second rough position count results; s _ R is that a signal is added to the full circle of the rotor, each S-R comes, the rough position counts one and two and is cleared, and a full circle counter is + 1; the Asin alpha and the Bcos alpha are provided for interpolation I (not in the present case) of the precise position of the DSP processing unit, and are used for interpolation subdivision counting of the precise real-time position of the rotor of the servo motor; asin (alpha +45 degrees) and-Bcos (alpha +45 degrees) are provided for the precise position interpolation II (not in the present case) of the DSP processing unit, and are used for interpolation subdivision counting of the precise real-time position of the rotor of the servo motor; the precise position interpolation one and two pairs of count results perform a security operation and a CRC redundancy check.
The utility model has the advantages that: a practical implementation circuit is provided; not only is the signals of the incremental sine and cosine encoder preprocessed to obtain square signals for coarse position counting, but also the signals of the incremental sine and cosine encoder are conditioned to obtain analog quantity signals for accurate position interpolation; not only the normal rough position counting is carried out on the obtained square wave signals, but also another path of square wave signals used for DSP processing and executing safety operation are generated; not only the obtained analog signal is subjected to normal accurate position interpolation, but also the other analog signal used for DSP processing to execute safe operation is obtained through equal shift processing.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (9)
1. A preprocessing circuit of incremental sine and cosine encoder signals is used for outputting preprocessed signals with safety and redundancy functions; the method is characterized in that: the device comprises an adder, a subtracter, a phase inverter, three proportional amplification differential shaping circuits and three comparators; wherein,
the proportional amplification differential shaping circuit is used for carrying out differential shaping and proportional amplification on a pair of sine incremental signals A + and A-output by a pair of incremental sine and cosine encoders to generate an A-phase sine signal Asin alpha;
the proportional amplification differential shaping circuit carries out differential shaping and proportional amplification on a pair of cosine incremental signals B + and B-output by the two pairs of incremental sine and cosine encoders to generate a B-phase cosine signal Bcos alpha; the phase difference between the A-phase sinusoidal signal Asin alpha and the B-phase cosine signal Bcos alpha is 90 degrees;
the adder adds the A-phase sine signal Asin α and the B-phase cosine signal Bcos α to form an analog quantity addition operationThen multiplied by a coefficientObtaining an A-phase 45-degree phase-shifted signal Asin (α +45 degrees) which is phase-shifted by 45 degrees relative to the A-phase sinusoidal signal Asin α;
the subtracter subtracts the A-phase sinusoidal signal Asin α from the B-phase sinusoidal signal Bcos α to form an analog subtractionThen multiplied by a coefficientObtaining a B-phase 45-degree phase shift signal Bcos (α +45 degrees) which is shifted by 45 degrees relative to the B-phase complementary chord signal Bcos α;
the inverter inverts the B-phase 45 ° phase shift signal Bcos (α +45 °) to generate an inverted signal-Bcos (α +45 °);
the first comparator converts the A-phase sinusoidal signal Asin alpha into an A-phase rectangular wave signal S _ A _ 1; the A-phase rectangular wave signal S _ A _1 redundantly generates an A-phase rectangular wave redundant signal S _ A _ 2;
the second comparator converts the B-phase cosine signal Bcos alpha into a B-phase rectangular wave signal S _ B _ 1; b-phase rectangular wave signals S _ B _1 are generated redundantly to generate B-phase rectangular wave redundant signals S _ B _ 2;
and a pair of reference point incremental signals R + and R-output by the three pairs of incremental sine and cosine encoders of the proportional amplification differential shaping circuit are subjected to differential shaping and proportional amplification and then converted into a reference point R rectangular wave signal S _ R by a comparator III.
2. The incremental sine-cosine encoder signal preprocessing circuit of claim 1, wherein: each of the proportional amplifying differential shaping circuits includes a differential shaping circuit for performing differential shaping on an input signal and a proportional amplifying circuit for performing proportional amplification.
3. The incremental sine-cosine encoder signal preprocessing circuit of claim 1, wherein: each proportional amplification differential shaping circuit comprises resistors R1-R6, a resistor R20, capacitors C1-C5, a capacitor C7 and operational amplifiers U1-U3; a sine increment signal A + is input into the in-phase end of an operational amplifier U1, the sine increment signal A-is input into the in-phase end of an operational amplifier U2, a resistor R1 is connected in series between the two in-phase ends of the operational amplifiers U1 and U2, the two in-phase ends of the operational amplifiers U1 and U2 are respectively connected with capacitors C1 and C2 in parallel, first-order RC filtering is built, and the two inverting ends of the operational amplifiers U1 and U2 are respectively connected with respective output ends to form negative feedback; the output end of the operational amplifier U1 is connected with the in-phase end of the operational amplifier U3 through a resistor R2, the output end of the operational amplifier U2 is connected with the inverting end of the operational amplifier U3 through a resistor R3, the in-phase end of the operational amplifier U3 is grounded through capacitors C4 and C3, a resistor R4 is connected to the capacitor C4 in parallel, and a power supply is connected between the capacitors C4 and C3; the inverting end of the operational amplifier U3 is connected with the output end of the operational amplifier U3 through a capacitor C5, a resistor R5 is connected to the capacitor C5 in parallel, one end of a capacitor C7 is connected between a resistor R6 and the resistor 20, and the other end of the capacitor C7 is grounded; the output end of the operational amplifier U3 is also used as the output end of the proportional amplifying differential shaping circuit through a resistor R6 and a resistor R20.
4. The incremental sine-cosine encoder signal preprocessing circuit of claim 1, wherein: the in-phase terminal of the first comparator receives the a-phase sinusoidal signal Asin α, the out-phase terminal of the first comparator is connected to a power supply for bias voltage, and is connected to ground via a capacitor C6, and the output terminal of the first comparator outputs an a-phase square wave signal S _ a _ 1.
5. The incremental sine-cosine encoder signal preprocessing circuit of claim 1, wherein: the non-inverting terminal of the second comparator receives the B-phase cosine signal Bcos alpha, the inverting terminal of the second comparator is connected with a power supply and used as a bias voltage, the inverting terminal of the second comparator is connected with the ground through a capacitor, and the output terminal of the second comparator outputs a B-phase square wave signal S _ B _ 1.
6. The incremental sine-cosine encoder signal preprocessing circuit of claim 1, wherein: the output end of the third proportional amplifying and differential shaping circuit is connected with the in-phase end of the third comparator, the inverting end of the third comparator is connected with a power supply and used as a bias voltage, the inverting end of the third comparator is grounded through a capacitor, and the output end of the third comparator outputs a reference point R rectangular wave signal S _ R.
7. The incremental sine-cosine encoder signal preprocessing circuit of claim 1, wherein: the adder comprises resistors R7-R11 and an operational amplifier U5; the A-phase sinusoidal signal Asin alpha and the B-phase cosine signal Bcos alpha are respectively connected with the in-phase end of an operational amplifier U5 through a resistor R7 and a resistor R8, the inverting end of the operational amplifier U5 is grounded through a resistor R10, two ends of a resistor R9 are respectively connected with the inverting end and the output end of an operational amplifier U5, and the output end of the operational amplifier U5 outputs an A-phase 45-degree phase-shift signal Asin (alpha +45 degrees) through a resistor R11.
8. The pre-processing circuit of incremental sine-cosine encoder signal as claimed in claim 1, wherein the subtracter comprises resistors R12-R16 and an operational amplifier U6, the A-phase sine signal Asin α is connected to the inverting terminal of the operational amplifier U6 via the resistor R12, the B-phase cosine signal Bcos α is connected to the inverting terminal of the operational amplifier U6 via the resistor R13, the inverting terminal of the operational amplifier U6 is grounded via the resistor R14, the two terminals of the resistor R15 are connected to the inverting terminal and the output terminal of the operational amplifier U6, the output terminal of the operational amplifier U6 outputs signal via the resistor R16
9. The incremental sine-cosine encoder signal preprocessing circuit of claim 1, wherein: the inverter comprises resistors R17-R19 and an operational amplifier U7; signalThe input end of the operational amplifier U7 is the inverting end, the in-phase end of the operational amplifier U7 is grounded through a resistor R17, two ends of the resistor R18 are respectively connected with the inverting end and the output end of the operational amplifier U7, and the output end of the operational amplifier U7 outputs a B-phase 45-degree phase shift and an inversion signal Bcos (α +45 degrees) through a resistor R19.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788440A (en) * | 2017-01-22 | 2017-05-31 | 中工科安科技有限公司 | A kind of pretreatment circuit of increment type sine and cosine encoder signal |
| CN107517025A (en) * | 2017-08-30 | 2017-12-26 | 擎声自动化科技（上海）有限公司 | A kind of motor position feedback device and its signal processing method |
-
2017
- 2017-01-22 CN CN201720083492.4U patent/CN206389353U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788440A (en) * | 2017-01-22 | 2017-05-31 | 中工科安科技有限公司 | A kind of pretreatment circuit of increment type sine and cosine encoder signal |
| CN106788440B (en) * | 2017-01-22 | 2023-09-12 | 中工科安科技有限公司 | Preprocessing circuit of incremental sine and cosine encoder signal |
| CN107517025A (en) * | 2017-08-30 | 2017-12-26 | 擎声自动化科技（上海）有限公司 | A kind of motor position feedback device and its signal processing method |
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