CN206413000U - A kind of preprocessed chip of increment type sine and cosine encoder signal - Google Patents
A kind of preprocessed chip of increment type sine and cosine encoder signal Download PDFInfo
- Publication number
- CN206413000U CN206413000U CN201720083493.9U CN201720083493U CN206413000U CN 206413000 U CN206413000 U CN 206413000U CN 201720083493 U CN201720083493 U CN 201720083493U CN 206413000 U CN206413000 U CN 206413000U
- Authority
- CN
- China
- Prior art keywords
- phase
- signal
- output
- resistance
- cosine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Transmission And Conversion Of Sensor Element Output (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
Abstract
The utility model discloses a kind of preprocessed chip of increment type sine and cosine encoder signal, it includes multiple pins in global design, and wherein at least has six input pins and nine output pins.Part inside the preprocessed chip includes adder, subtracter, phase inverter, three scaling difference shaping circuits, three comparators.Two inputs of scaling difference shaping circuit one draw input pin one, two respectively, and output end draws output pin one.Two inputs of scaling difference shaping circuit two draw input pin three, four respectively, and output end draws output pin two.The output end of adder draws output pin three.The output end of phase inverter draws output pin four.The output end of comparator one draws the output pin five, six of redundancy.The output end of comparator two draws the output pin seven, eight of redundancy.Two inputs of scaling difference shaping circuit three draw input pin five, six respectively, and the output end of comparator three draws output pin nine.
Description
Technical field
The utility model is related to a kind of preprocessed chip, more particularly to a kind of pre- place of increment type sine and cosine encoder signal
Manage chip.
Background technology
Signal Pretreatment is to carry out early stage processing to various types of electric signals, is entered by various expected purposes and requirement
The general designation of row process, seeks to signal of the record on certain media to be handled, to extract useful information
Process, it is the general designation of the processing procedure such as being extracted, converted, analyzed, integrated to signal.
Increment type sine and cosine encoder is before coarse position counting or smart position interpolation is carried out, it is necessary to the original of encoder
Beginning signal is pre-processed.On the one hand, preprocessed chip is the coarse position counting unit in follow-up DSP (digital signal processor)
(coarse position is counted, i.e., first carry out 4 frequencys multiplication to square-wave signal, then calculates the real time position of rotor) provides preferable square wave
Signal source；On the other hand, preprocessed chip provides preferable simulation signal generator for the exact position interpolating unit in follow-up DSP.
So-called exact position interpolation, the i.e. a cycle to analog signal carry out time segmentation, are divided into several equal signals
Section, a cycle of original analog signal can only produce a trigger pulse, now pass through interpolation and be divided into several equal letters
Several trigger pulses will be produced after number section.Improve the resolution ratio of number system.For example, certain type increment type sine and cosine encoder
Line number be 2048 (often changing the line of production raw 2048 signal periods), after 4 frequencys multiplication its physical resolution=analog signal a cycle/
4=360*3600/ (2048*4)=158.203125 arcsecond, this numerical value be exactly in DSP coarse position counting unit to motor
Rotor carries out the resolution ratio of position counting.Traditional square-wave signal processing method and circuit to encoder is because 4 can not be broken through
This concept (more frequencys multiplication will cause position signalling distortion) of frequency multiplication, therefore higher rotor-position number system can not be obtained
Resolution ratio.
Utility model content
In order to solve the above-mentioned technical problem, the utility model proposes a kind of pre- place of increment type sine and cosine encoder signal
Chip is managed, it exports the preprocessed signal with safety and redundancy feature.
Solution of the present utility model is：A kind of preprocessed chip of increment type sine and cosine encoder signal, it is used for
Preprocessed signal of the output with safety and redundancy feature；It includes multiple pins in global design, and wherein at least has six
Input pin and nine output pins；Part inside the preprocessed chip includes adder, subtracter, phase inverter, three ratios
Example amplification difference shaping circuit, three comparators；
Two inputs of scaling difference shaping circuit one draw input pin one and input pin two respectively, to connect
A pair sinusoidal increment signal A+ and A- of increment type sine and cosine encoder output are received, are carried out by scaling difference shaping circuit one
Difference shaping, scaling, generation A phase sinusoidal signal Asin α；The output end of scaling difference shaping circuit one draws output
Pin one；
Two inputs of scaling difference shaping circuit two draw input pin three and input pin four respectively, to connect
A pair of cosine incremental signals B+ and B- of increment type sine and cosine encoder output are received, are carried out by scaling difference shaping circuit two
Difference shaping, scaling, generation B phase cosine signal Bcos α；Wherein, A phases sinusoidal signal Asin α and B phase cosine signals Bcos
Phase difference is 90 ° between α, and the output end of scaling difference shaping circuit two draws output pin two；
Adder is done analog quantity add operation plus B phase cosine signal Bcos α to A phase sinusoidal signal Asin α and formed(+45 ° of α), multiplied by with coefficientObtain 45 ° of phase shift signals of A phases of relative 45 ° of A phase sinusoidal signal Asin α phase shifts
Asin(α+45°)；The output end of adder draws output pin three；
Subtracter subtracts A phase sinusoidal signal Asin α to B phase cosine signal Bcos α to be done analog quantity subtraction and is formed(+45 ° of α), multiplied by with coefficientObtain 45 ° of phase shift signals of B phases of relative 45 ° of B phase cosine signal Bcos α phase shifts
Bcos(α+45°)；Phase inverter is inverted to 45 ° of phase shift signal Bcos of B phases (+45 ° of α), generation reverse signal-Bcos (+45 ° of α)；
The output end of phase inverter draws output pin four；
A phase sinusoidal signal Asin α are converted to A phase square-wave signal S_A_1 by comparator one, and the output end of comparator one is drawn
Go out the output pin five and output pin six of redundancy；
B phase cosine signal Bcos α are converted to B phase square-wave signal S_B_1 by comparator two, and the output end of comparator two is drawn
Go out the output pin seven and output pin eight of redundancy；
Two inputs of scaling difference shaping circuit three draw input pin five and input pin six to connect respectively
A pair of reference points increment signal R+ and R- of increment type sine and cosine encoder output are received, are entered by scaling difference shaping circuit three
The shaping of row difference, it is scaling after reference point R square-wave signal S_R, the output end of comparator three are converted to by comparator three again
Draw output pin nine.
As the further improvement of such scheme, it is poor to input signal realization that each scaling difference shaping circuit includes
Divide the difference shaping circuit of shaping and realize scaling scaling circuit.
As the further improvement of such scheme, each scaling difference shaping circuit includes resistance R1~R6, resistance
R20, electric capacity C1~C5, electric capacity C7, operational amplifier U1~U3；Sinusoidal increment signal A+ input operational amplifiers U1 same phase
Gone here and there between end, sinusoidal increment signal A- input operational amplifiers U2 in-phase end, operational amplifier U1, U2 two in-phase ends
Join resistance R1, and operational amplifier U1, U2 two in-phase ends difference shunt capacitance C1, C2, build single order RC filtering, computing is put
Big device U1, U2 two end of oppisite phase connect respective output end respectively, form negative-feedback；Operational amplifier U1 output end via
Resistance R2 concatenation operation amplifiers U3 in-phase end, operational amplifier U2 output end is via resistance R3 concatenation operation amplifiers U3
End of oppisite phase, operational amplifier U3 in-phase end is also grounded via electric capacity C4, C3, and resistance R4 is connected in parallel on electric capacity C4, electric capacity C4,
Power supply is accessed between C3；Operational amplifier U3 end of oppisite phase is via electric capacity C5 concatenation operation amplifiers U3 output end, and resistance R5 is simultaneously
It is associated on electric capacity C5, electric capacity C7 one end is connected between resistance R6 and resistance 20, electric capacity C7 other end ground connection；Operation amplifier
Device U3 output end is also via the output end after resistance R6, resistance R20 as scaling difference shaping circuit.
As the further improvement of such scheme, the in-phase end of the comparator one receives A phase sinusoidal signal Asin α, the ratio
On the one hand end of oppisite phase compared with device one connects power supply, as bias voltage, is on the other hand grounded via an electric capacity C6, the comparator one
Output end output A phase square-wave signals S_A_1.
As the further improvement of such scheme, the in-phase end of the comparator two receives B phase cosine signal Bcos α, the ratio
On the one hand end of oppisite phase compared with device two connects power supply, as bias voltage, on the other hand via a capacity earth, the comparator two
Output end output B phase square-wave signals S_B_1.
As the further improvement of such scheme, the output end of the scaling difference shaping circuit three connects the comparator
On the one hand three in-phase end, the end of oppisite phase of the comparator three connects power supply, as bias voltage, is on the other hand connect via an electric capacity
Ground, the output end output reference point R square-wave signals S_R of the comparator three.
As the further improvement of such scheme, the adder includes resistance R7~R11, operational amplifier U5；A phases are sinusoidal
Signal Asin α, B phase cosine signal Bcos α are respectively via resistance R7, resistance R8 concatenation operation amplifiers U5 in-phase end, computing
Amplifier U5 end of oppisite phase is grounded via resistance R10, resistance R9 two ends difference concatenation operation amplifier U5 end of oppisite phase and defeated
Go out end, operational amplifier U5 output end exports 45 ° of phase shift signal Asin of A phases (+45 ° of α) via resistance R11.
As the further improvement of such scheme, the subtracter includes resistance R12~R16, operational amplifier U6；A phases are just
String signal Asin α are via resistance R12 concatenation operation amplifiers U6 end of oppisite phase, and B phases cosine signal Bcos α are via resistance R13 companies
Operational amplifier U6 in-phase end is connect, operational amplifier U6 in-phase end is grounded via resistance R14, resistance R15 two ends difference
Concatenation operation amplifier U6 end of oppisite phase and output end, operational amplifier U6 output end is via resistance R16 output signals(α+45°)。
As the further improvement of such scheme, the phase inverter includes resistance R17~R19, operational amplifier U7；Signal(+45 ° of α) input operational amplifier U7 end of oppisite phase, operational amplifier U7 in-phase end is grounded via resistance R17,
Resistance R18 two ends difference concatenation operation amplifier U7 end of oppisite phase and output end, operational amplifier U7 output end is via electricity
Hinder R19 output 45 ° of phase shifts of B phases and reverse signal-Bcos (+45 ° of α).
It is used as the further improvement of such scheme, sinusoidal increment signal A+ and A-, cosine incremental signals B+ and B-, reference point
Increment signal R+ and R- are transmitted in differential signal mode.
In the utility model, by the multifunctional signal exported to increment type sine and cosine encoder Signal Pretreatment,
Multiple choices are provided for downstream DSP processing, the different degrees of demand of different user is disclosure satisfy that, can be retouched in FPGA with hardware
Predicate speech is IP core circuit design of the present utility model, or even can also manufacture and design the asic chip as a standard,
The utility model is basic research of this area in the national equipment manufacture of lifting, especially to improving AC servo permanent-magnet synchronous
The rotor real time position precision of the execution units such as motor, has made maximum contribution.
Brief description of the drawings
Fig. 1 is the circuit structure diagram of the pretreatment circuit of increment type sine and cosine encoder signal.
Fig. 2 is that scaling difference shaping circuit one and comparator one are electrically schemed in succession in Fig. 1.
Fig. 3 is emulated respectively by MATLAB to difference shaping circuit one in Fig. 1 and difference shaping circuit two
Phase differs 90 degree of A phases and the cosine and sine signal oscillogram of B phases.
Fig. 4 is emulate obtained A phase square-wave signal figures to comparator in Fig. 1 one by MATLAB.
Fig. 5 is the circuit diagram of adder in Fig. 1.
Fig. 6 is that circuit in Fig. 4 is carried out by MATLAB to emulate obtained signal output waveform figure.
Fig. 7 is the circuit connection diagram of subtracter and phase inverter in Fig. 1.
Fig. 8 is that circuit in Fig. 7 is carried out by MATLAB to emulate obtained signal output waveform figure.
Fig. 9 is that the two paths of signals ASin (a+45 °) and-Bcos (a+45 °) of final output are compared in MATLAB
Signal waveforms.
Embodiment
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation
Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only to explain
The utility model, is not used to limit the utility model.
Also referring to Fig. 1 to Fig. 9, the preprocessed chip of increment type sine and cosine encoder signal of the present utility model is used for
Preprocessed signal of the output with safety and redundancy feature, this is the larger difference existed between conventional pretreatment signal
Place.Referring to Fig. 1, the preprocessed chip of increment type sine and cosine encoder signal includes multiple pins in global design, wherein
At least six input pins and nine output pins.Part that should be inside preprocessed chip includes three scaling difference
Shaping circuit 1~3, three comparators 4~6, adder 7, subtracter 8, phase inverters 9.
Two inputs of scaling difference shaping circuit 1 draw input pin one and input pin two respectively, with
A pair sinusoidal increment signal A+ and A- of increment type sine and cosine encoder output are received, by scaling difference shaping circuit 1
The shaping of progress difference, scaling, generation A phase sinusoidal signal Asin α；The output end of scaling difference shaping circuit 1 is drawn
Go out output pin one；
Two inputs of scaling difference shaping circuit 22 draw input pin three and input pin four respectively, with
A pair of cosine incremental signals B+ and B- of increment type sine and cosine encoder output are received, by scaling difference shaping circuit 22
The shaping of progress difference, scaling, generation B phase cosine signal Bcos α；Wherein, A phases sinusoidal signal Asin α and B phase cosine signals
Phase difference is 90 ° between Bcos α, and the output end of scaling difference shaping circuit 22 draws output pin two；
Adder 7 is done analog quantity add operation plus B phase cosine signal Bcos α to A phase sinusoidal signal Asin α and formed(+45 ° of α), multiplied by with coefficientObtain 45 ° of phase shift signals of A phases of relative 45 ° of A phase sinusoidal signal Asin α phase shifts
Asin(α+45°)；The output end of adder 7 draws output pin three；
Subtracter 8 subtracts A phase sinusoidal signal Asin α to B phase cosine signal Bcos α to be done analog quantity subtraction and is formed(+45 ° of α), multiplied by with coefficientObtain 45 ° of phase shift signals of B phases of relative 45 ° of B phase cosine signal Bcos α phase shifts
Bcos(α+45°)；Phase inverter 9 is inverted to 45 ° of phase shift signal Bcos of B phases (+45 ° of α), generation reverse signal-Bcos (+45 ° of α)；
The output end of phase inverter 9 draws output pin four；
A phase sinusoidal signal Asin α are converted to A phase square-wave signal S_A_1, the output end of comparator 1 by comparator 1
Draw the output pin five and output pin six of redundancy；
B phase cosine signal Bcos α are converted to B phase square-wave signal S_B_1, the output end of comparator 25 by comparator 25
Draw the output pin seven and output pin eight of redundancy；
Two inputs of scaling difference shaping circuit 33 draw input pin five and input pin six to connect respectively
A pair of reference points increment signal R+ and R- of increment type sine and cosine encoder output are received, by scaling difference shaping circuit 33
Carry out difference shaping, it is scaling after reference point R square-wave signal S_R are converted to by comparator 36 again, comparator 36 it is defeated
Go out end and draw output pin nine.
Accordingly it is also possible to so say, each frame of the preprocessed signal include signals below Asin α, Bcos α, Asin (α+
45 °) ,-Bcos (+45 ° of α), S_A_1, S_A_2, S_B_1, S_B_2, S_R.
Asinα：A pair of sinusoidal increment letters of scaling one 1 pairs of increment type sine and cosine encoder output of difference shaping circuit
Number A+ and A-, carries out difference shaping, scaling, generation A phase sinusoidal signal Asin α.
Bcosα：The 22 pairs of increment type sine and cosine encoders outputs of scaling difference shaping circuit and phase difference is 90 °
A pair of cosine incremental signals B+ and B-, carry out difference shaping, scaling, generation B phase cosine signal Bcos α.
Asin(α+45°)：Adder 7 does analog quantity addition to A phase sinusoidal signal Asin α plus B phase cosine signal Bcos α
Computing forms signal(+45 ° of α), multiplied by with coefficientObtain the A phases of relative 45 ° of A phase sinusoidal signal Asin α phase shifts
45 ° of phase shift signal Asin (+45 ° of α).
- Bcos (+45 ° of α)：Subtracter 8 subtracts A phase sinusoidal signal Asin α to B phase cosine signal Bcos α to be done analog quantity and subtracts
Method computing forms signal(+45 ° of α), multiplied by with coefficientObtain the B of relative 45 ° of B phase cosine signal Bcos α phase shifts
45 ° of phase shift signal Bcos of phase (+45 ° of α), then inverted via phase inverter 9, generation reverse signal-Bcos (+45 ° of α).
S_A_1：A phase sinusoidal signal Asin α are converted to A phase square-wave signals S_A_1 by comparator one.
S_A_2：S_A_1 carries out crossing redundancy generation A phase square wave redundant signals S_A_2.
S_B_1：B phase cosine signal Bcos α are converted to B phase square-wave signals S_B_1 by comparator two.
S_B_2：S_B_1 carries out crossing redundancy generation B phase square wave redundant signals S_B_2.
S_R：A pair of reference point increments letter that scaling difference shaping circuit three is exported to increment type sine and cosine encoder
Number R+ and R-, carry out difference shaping, it is scaling after reference point R square-wave signals S_R is converted to by comparator three again.
It is pointed out that emphasis of the present utility model and not lying in three scaling difference shaping circuits 1~3, three
These parts such as individual comparator 4~6, adder circuit 7, subtracter 8, phase inverter 9 in itself, and refer to main by these parts
The structure such as (three scaling difference shaping circuits 1~3, three comparators 4~6, adder circuit 7, subtracter 8, phase inverter 9)
Into this design for completing preprocessed signal of the output with safety and redundancy feature required for the utility model.Just as
Circuit, resistance, inductance, the chip of built-up circuit etc. inherently exist in the prior art, but not because they being deposited
, it is meant that the circuit being made up of them must be obvious, must be the conventional selection of those skilled in the art, no
Constantly bringing forth new ideas for circuit is then just hindered, the purpose of Patent Law has just been run counter to.The utility model is intended by herein：Cut-off
Before the present utility model application, do not retrieve increment type sine and cosine encoder signal of the present utility model preprocessed chip this
The electrical structure of sample, designing the preprocessed chip of increment type sine and cosine encoder signal of the present utility model needs to pay creation
Property work, at least those skilled in the art, which never have, so did.
Defined according to Heidenhain encoder interfaces, for 1VPP sine and cosine increment output voltage signals A and B typical amplitude
For 1VPP, phase difference is 90 ° of Electron Angular.Interface signal is three pairs of differential signals.In preprocessed chip of the present utility model,
In order to obtain the phase signals of A, B two i.e. A phases sinusoidal signal Asin α, B phases cosine signal Bcos α, it is necessary to carry out difference to differential signal
Shaping, scaling etc..(it is primarily referred to as in order to each obtain square-wave signal by comparator by the phase signals of A, B two simultaneously
Square-wave signal), the low and high level of acquisition need to meet the requirement such as sampling A/D chip or FPGA pins.Sinusoidal increment signal A+ and A-,
Cosine incremental signals B+ and B-, reference point increment signal R+ and R- are transmitted in differential signal mode.
Incorporated by reference to Fig. 2, each scaling difference shaping circuit may include the difference that difference shaping is realized to input signal
Shaping circuit and realize scaling scaling circuit.In the present embodiment, each scaling difference shaping circuit bag
Include resistance R1~R6, resistance R20, electric capacity C1~C5, electric capacity C7, operational amplifier U1~U3.
Sinusoidal increment signal A+ input operational amplifiers U1 in-phase end, sinusoidal increment signal A- input operational amplifiers
Series resistance R1 between U2 in-phase end, operational amplifier U1, U2 two in-phase ends, and two of operational amplifier U1, U2
In-phase end distinguishes shunt capacitance C1, C2, and operational amplifier U1, U2 two end of oppisite phase connect respective output end respectively.Computing
Amplifier U1 output end is via resistance R2 concatenation operation amplifiers U3 in-phase end, and operational amplifier U2 output end is via electricity
R3 concatenation operation amplifiers U3 end of oppisite phase is hindered, operational amplifier U3 in-phase end is also grounded via electric capacity C4, C3, and resistance R4 is simultaneously
It is associated on electric capacity C4, power supply is accessed between electric capacity C4, C3.Operational amplifier U3 end of oppisite phase is via electric capacity C5 concatenation operation amplifiers
U3 output end, resistance R5 is connected in parallel on electric capacity C5, and electric capacity C7 one end is connected between resistance R6 and resistance 20, electric capacity C7's
The other end is grounded；Operational amplifier U3 output end is also used as scaling difference shaping circuit via resistance R6, resistance R20
Output end.
The output end of scaling difference shaping circuit 1 connects the in-phase end of the comparator 1, makes the comparator one
In-phase end receives A phase sinusoidal signal Asin α, and on the one hand the end of oppisite phase of the comparator 1 connects power Vcc, as bias voltage, separately
On the one hand it is grounded via an electric capacity C6, the output end output A phase square-wave signals S_A_1 of the comparator 1.Similarly, ratio is put
The output end of big difference shaping circuit 22 connects the in-phase end of the comparator 25, the in-phase end of the comparator two is received B phases
On the one hand cosine signal Bcos α, the end of oppisite phase of the comparator 25 connects power supply (not shown), as bias voltage, on the other hand passes through
It is grounded by an electric capacity (not shown), the output end output B phase square-wave signals S_B_1 of the comparator 25.Scaling difference is whole
The output end of shape circuit 33 connects the in-phase end of the comparator 36, and on the one hand the end of oppisite phase of the comparator 36, which connects power supply, (schemes not
Show), as bias voltage, on the other hand it is grounded via an electric capacity (not shown), the output end output reference of the comparator 36
Point R square-wave signals S_R.
The sinusoidal increment signal A phases and B phases come out by encoder interfaces, is that the amplitude of a pair of 90 degree of differences is 1V difference
Differential signal A phases, are respectively processed by signal with B phases here.By taking differential signal A+ and A- as an example, amplify respectively through two-way
Device U1 and U2 are amplified, and are entered back into amplifier U3 and are carried out difference integration, export sinusoidal signal Asin α all the way, amplitude range is
0V~3.3V, while by sinusoidal signal Asin α input comparator U4, by 1.5V bias voltage, being joined according to comparator characteristic
Number, is similar to the signal of square wave all the way, and amplitude range is 0.4V~2.6V.Fig. 4 and Fig. 3 are to figure respectively by MATLAB
Difference shaping circuit carries out emulating obtained square-wave signal in 1 and phase differs 90 degree of A phases and the cosine and sine signal ripple of B phases
Shape.
Incorporated by reference to Fig. 5, adder includes resistance R7~R11, operational amplifier U5.Asin α, Bcos α are respectively via resistance
R7, R8 concatenation operation amplifier U5 in-phase end, operational amplifier U5 end of oppisite phase are grounded via resistance R10, and the two of resistance R9
End difference concatenation operation amplifier U5 end of oppisite phase and output end, operational amplifier U5 output end is exported via resistance R11
Asin(α+45°)。
This partial circuit is difference shaping, scaling and compare single channel, generation A phase sinusoidal signal Asin α.Finally lead to
The bias voltage for crossing 1.5V is compared, and output low level is that the square-wave signal that 0.4V, high level are 2.6V, i.e. A phases square wave are believed
Number S_A.Anti-phase adder circuit 7 is by the resistance of feedback resistance, with 0.707 (i.e.) ratio carry out product.
90 degree of cosine and sine signal Asin α and Bcos α, input are differed in the two-way phase exported by difference shaping circuit
Adder U5 end in the same direction, while two-phase cosine and sine signal amplitude is equal.To meet：
Make to meet above-mentioned relation coefficient by adjusting resistance R8, R7, R10 and R9 resistance value in Fig. 5.
Disconnected according to void, input in the same direction does not have electric current to pass through, and causes the electric current by resistance R8 and R7 equal, passes through resistance
R10 and R9 electric current is also equal.
Therefore：
It is disconnected according to void,
V+=V_
It can thus be concluded that going out：
Fig. 6 is that circuit is carried out by MATLAB to emulate obtained signal output waveform, in figure 6 it can be seen that in addition
Device holds input A phases and the phase signals of B phases two in the same direction, after adder is handled, and waveform can 45 ° of phase shift, amplitude increase about 1.414
Times, by adjusting resistance R8, R7, R10 and R9 resistance value, amplitude is reduced 0.707 times, just can obtain output signal Asin
The waveform of (+45 ° of α).
Incorporated by reference to Fig. 7, the subtracter includes resistance R12~R16, operational amplifier U6.A phases sinusoidal signal Asin α via
Resistance R12 concatenation operation amplifiers U6 end of oppisite phase, B phases cosine signal Bcos α are via resistance R13 concatenation operation amplifiers U6's
In-phase end, operational amplifier U6 in-phase end is grounded via resistance R14, resistance R15 two ends difference concatenation operation amplifier U6
End of oppisite phase and output end, operational amplifier U6 output end is via resistance R16 output signals(α+45°)。
The phase inverter includes resistance R17~R19, operational amplifier U7.Signal(+45 ° of α) inputs operation amplifier
Device U7 end of oppisite phase, operational amplifier U7 in-phase end is grounded via resistance R17, and concatenation operation is put respectively at resistance R18 two ends
Big device U7 end of oppisite phase and output end, operational amplifier U7 output end exports the 45 ° of phase shifts of B phases via resistance R19 and reversion is believed
Number-Bcos (+45 ° of α).
And for the exact position interpolating unit in DSP, a cycle progress time segmentation to analog signal is inserted
Value, for example, be divided into 8 equal portions, then resolution ratio=analog signal a cycle/8=360*3600/ (2048*8) after interpolation
=79.1015625 arcseconds, this numerical value is the rotor-position for carrying out obtaining after 8 grades point interpolation subdividing to a signal period
Number system resolution ratio, it is clear that this resolution ratio coarse position count resolution improves 1 times.Illustrate again, one high-accuracy
CNC machine requires the arcsecond of rotor-position precision ± 5, then need to carry out signal period the quantity of interpolation subdividing=
360*3600/ (2*5*2048)=63.28125, i.e., need to only carry out the interpolation processing of 64 deciles to a signal period, it is possible to
It is less than the rotor-position precision of ± 5 arcseconds.
DSP except receiving signal Asin α and the Bcos α from preprocessed chip, and carry out accordingly rotor real time position and
Real-time speed calculates outer (rough position counting and the computing function of exact position interpolation of the offer to the rotor real time position of motor
It), DSP also receives safety signal Asin (+45 ° of α) and-Bcos (+45 ° of α) from preprocessed chip, and safety letter accordingly
Rotor real time position is carried out number again and real-time speed is calculated, and DSP is to rotor real time position and two groups of calculating knots of real-time speed
Fruit carries out intersection comparison, and compared result performs safety operation.
90 degree of cosine and sine signal Asin α and Bcos α, input are differed in the two-way phase exported by difference shaping circuit
Subtracter is not held in the same direction, and two-phase cosine and sine signal amplitude is equal, while obtained output signal input inverter is carried out anti-phase.
To meet：
Make to meet above-mentioned relation coefficient by adjusting resistance R13, R12, R14 and R15 resistance value in Fig. 7.
Disconnected according to void, U6 inputs in the same direction do not have electric current to pass through, and cause the electric current by resistance R12 and R13 equal, pass through
Resistance R14 and R15 electric current are also equal.
Therefore：
It is disconnected according to void,
V+=V_
It can thus be concluded that going out：
In the cosine signal input inverter that obtained amplitude is increased to about 1.414 times, by adjusting resistance R16 and R18
Resistance size, make amplitude reduce 0.707 times, reverse-phase 180 degree.
In U7, the end in the same direction ground connection of amplifier.According to short, the reverse terminal voltage 0V of void.It is disconnected according to void, reverse input end input
High resistance, does not almost have electric current input and output, and resistance R16 and R18 series connection, the electric current by resistance R16 and R18 are equal.
Pass through resistance R16 electric current：
Pass through resistance R18 electric current：I7=(V_-Vout)/R18
Disconnected, the V according to void+=V_
It can thus be concluded that going out：
Fig. 8 is that Fig. 7 circuits are carried out by MATLAB to emulate obtained signal output waveform, can see, is subtracting in figure
The musical instruments used in a Buddhist or Taoist mass not end input A phases and phase signals of B phases two in the same direction, after subtracter is handled, waveform can 45 ° of phase shift, by adjust R13,
R12, R14 and R15 resistance value, make amplitude increase about 1.414 times, obtain output signalThe waveform of (+45 ° of α) leads to
Overregulate R16 and R18 resistance value, amplitude is reduced 0.707 times, while carry out is anti-phase, just can obtain output signal-
Bcos (+45 ° of α) waveform.
Fig. 9 is that the two paths of signals Asin (+45 ° of α) and-Bcos (+45 ° of α) of final output are compared in MATLAB
Compared with, from the point of view of the starting point of output signal, after adder and subtracter are handled with phase inverter, two-way cosine and sine signal Asin
(+45 ° of α) and-Bcos (+45 ° of α) have 135 ° of phase difference, but connect from the continuity of signal, signal after treatment
All it is to have 90 degree of phase difference as A phases and the phase signals of B phases two.So, the phase difference of signal section start is negligible.
Processing to code device signal, including DSP processing (rough position is counted and exact position interpolation) and encoder letter
Number pretreatment.Processing especially to increment type sine and cosine encoder signal is that acquisition servo motor rotor real time position is (especially high
Resolution ratio rotor real time position) crucial and unique approach, be high-accuracy CNC machine, servo manipulator, numerical control rotary work
The execution units such as platform, multifunctional numerical control angular milling head, electro spindle improve necessity of axis servomotor (containing linear axis and rotary shaft) precision
Material base.The technology of processing (counting and safety) and the always national equipment manufacture of digitlization to code device signal is short
Plate, in order to break technical monopoly, lifting China high-grade, digitally controlled machine tools, the position detection of AC servo transmission and the feedback essence in west
Degree, has risen to national height.《Intelligent manufacturing equipment innovation and development engineering construction scheme》(hair changes high skill [2014] 2072
Number) file requires to realize AC synchronous sampling internal control and measuring unit in the description as described in Whole Digit AC Servo System
Total digitalization.What the AC synchronous sampling internal control mentioned in file and measuring unit referred to is exactly that CNC fields are widely used
AC servo permagnetic synchronous motor and motor in cosine and sine signal encoder.It can be seen that, to cosine and sine signal code device signal
Processing meaning importance.
There is considerable document to propose and 4 frequencys multiplication are carried out to the square-wave signal of encoder (mainly TTL signal encoder)
Then the circuit or method of rough position counting are carried out again；There is seldom document to point out, to the mould of increment type sine and cosine encoder
Intend signal and carry out squared processing, be converted into square-wave signal, then using the method for similar process square-wave signal encoder, carry out
Rough position is counted, such as patent document ZL201520574867.8, ZL201520570360.5,201510465550.5,
201510467898.8,201510465547.3,201610517319.0,201610518856.7,2016120690307.3
(hereinafter referred to as patent document combination) all refer to the analog signal of increment type sine and cosine encoder to be converted into square-wave signal right
The method for carrying out rough position counting again afterwards；Patent document combination also refers to the analog signal to increment type sine and cosine encoder
Carry out phase shift to be equal to pretreatment and then recycle DSP to carry out exact position interpolation, so as to obtain more accurate servo motor rotor
The technological process of real time position；In addition patent document combination also refer to the technological process of safe coding device signal.Patent document
Theoretical foundation of the combination without the detailed implementation method for proposing preprocessed chip and with its realization.
In addition, in order to strengthen the secrecy for pre-processing and post-processing to code device signal, developed country takes more special than applying
Sharp more effective way, that is, design the IP core of code device signal pretreatment and post processing, design circuit and algorithm packaging arrived
In IP core, user's purchase is used, it is impossible to know why so use；Even manufacture and design special asic chip.
Processing to code device signal, including DSP processing and code device signal pre-process two parts, and two parts all have ten
Divide important effect, it is indispensable.Algorithm process is mainly responsible in DSP processing, is theoretical foundation；Code device signal pretreatment is responsible for
Suitable signal source is provided for DSP algorithm, is material base.The utility model proposes to increment type sine and cosine encoder signal
Pretreatment be responsible for DSP processing (not in the present case describe) signal source be provided, particular content is：A+、A-、B+、B-、R+、R-
Six tunnels are original (the utility model symbol A, B, R used herein are only used for distinguishing signal phase, as follows without amplitude implication)
The encoded device signal of increment type sine and cosine encoder differential signal (amplitude 1VPP) preprocessed chip after generate 9 roads letter
Number there is provided DSP processing units are given, square-wave signal S_B_1 and S_A_1 are supplied to the rough position of DSP processing units to count one (no
In the present case), for the rough counting to servo motor rotor real time position；Square-wave signal S_B_2 and S_A_2 are supplied to DSP
The rough position of processing unit counts two (not in the present case), for the rough counting to servo motor rotor real time position, slightly
Slightly position counting one and two pairs of count results performs safety operation and CRC redundancy checks；S_R is that rotor is completely enclosed plus a signal, often
Individual S-R arrives, and rough position counts one and two and reset, and completely encloses counter+1；Asin α and Bcos α are supplied to DSP processing units
Exact position interpolation one (not in the present case), for the interpolation subdividing counting to the accurate real time position of servo motor rotor；
Asin (+45 ° of α) and-Bcos (+45 ° of α) are supplied to the exact position interpolation two (not in the present case) of DSP processing units, are used for
The interpolation subdividing of the accurate real time position of servo motor rotor is counted；Exact position interpolation one and two pairs of count results perform peace
Full operation and CRC redundancy checks.
The utility model advantage is：There is provided a practical implementing circuit；Not only to increment type sine and cosine encoder
Signal Pretreatment carries out coarse position counting to obtain square-wave signal, and also increment type sine and cosine encoder signal is nursed one's health to obtain
Analog signalses are obtained, for exact position interpolation；Normal rough position counting not only is carried out to the square-wave signal of acquisition, also given birth to
It is used for the square-wave signal that DSP handles execution safety operation into another road；Not only the analog signal to acquisition carries out normal essence
True position interpolation, is also handled by phase shift etc. and obtains the analog signal that another road performs safety operation for DSP processing.
Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model
Any modifications, equivalent substitutions and improvements made within the spirit and principle of utility model etc., should be included in the utility model
Protection domain within.
Claims (10)
1. a kind of preprocessed chip of increment type sine and cosine encoder signal, it is used to exporting pre- with safety and redundancy feature
Process signal；It is characterized in that：Its in global design include multiple pins, wherein at least have six input pins and nine it is defeated
Go out pin；Part inside the preprocessed chip includes adder, subtracter, phase inverter, three scaling difference shaping electricity
Road, three comparators；
Two inputs of scaling difference shaping circuit one draw input pin one and input pin two respectively, to receive increasing
A pair sinusoidal increment signal A+ and A- of amount formula sine and cosine encoder output, difference is carried out by scaling difference shaping circuit one
Shaping, scaling, generation A phase sinusoidal signal Asin α；The output end of scaling difference shaping circuit one draws output pin
One；
Two inputs of scaling difference shaping circuit two draw input pin three and input pin four respectively, to receive increasing
A pair of cosine incremental signals B+ and B- of amount formula sine and cosine encoder output, difference is carried out by scaling difference shaping circuit two
Shaping, scaling, generation B phase cosine signal Bcos α；Wherein, A phases sinusoidal signal Asin α and B phase cosine signal Bcos α it
Between phase difference be 90 °, the output end of scaling difference shaping circuit two draws output pin two；
Adder is done analog quantity add operation plus B phase cosine signal Bcos α to A phase sinusoidal signal Asin α and formedMultiplied by with coefficientObtain 45 ° of phase shift letters of A phases of relative 45 ° of A phase sinusoidal signal Asin α phase shifts
Number Asin (+45 ° of α)；The output end of adder draws output pin three；
Subtracter subtracts A phase sinusoidal signal Asin α to B phase cosine signal Bcos α to be done analog quantity subtraction and is formedMultiplied by with coefficientObtain 45 ° of phase shift letters of B phases of relative 45 ° of B phase cosine signal Bcos α phase shifts
Number Bcos (+45 ° of α)；Phase inverter is inverted to 45 ° of phase shift signal Bcos of B phases (+45 ° of α), generation reverse signal-Bcos (α+
45°)；The output end of phase inverter draws output pin four；
A phase sinusoidal signal Asin α are converted to A phase square-wave signal S_A_1 by comparator one, and the output end of comparator one draws superfluous
Remaining output pin five and output pin six；
B phase cosine signal Bcos α are converted to B phase square-wave signal S_B_1 by comparator two, and the output end of comparator two draws superfluous
Remaining output pin seven and output pin eight；
Two inputs of scaling difference shaping circuit three draw input pin five and input pin six to receive increasing respectively
A pair of reference points increment signal R+ and R- of amount formula sine and cosine encoder output, difference is carried out by scaling difference shaping circuit three
Point shaping, it is scaling after reference point R square-wave signal S_R are converted to by comparator three again, the output end of comparator three is drawn
Output pin nine.
2. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：Each ratio
Amplification difference shaping circuit includes realizing input signal the difference shaping circuit of difference shaping and realizes scaling ratio
Amplifying circuit.
3. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：Each ratio
Amplifying difference shaping circuit includes resistance R1~R6, resistance R20, electric capacity C1~C5, electric capacity C7, operational amplifier U1~U3；Just
String increment signal A+ input operational amplifiers U1 in-phase end, sinusoidal increment signal A- input operational amplifiers U2 in-phase end,
Series resistance R1 between operational amplifier U1, U2 two in-phase ends, and operational amplifier U1, U2 two in-phase ends respectively simultaneously
Join electric capacity C1, C2, build single order RC filtering, operational amplifier U1, U2 two end of oppisite phase connect respective output end, shape respectively
Into negative-feedback；Operational amplifier U1 output end is via resistance R2 concatenation operation amplifiers U3 in-phase end, operational amplifier U2
Output end via resistance R3 concatenation operation amplifiers U3 end of oppisite phase, operational amplifier U3 in-phase end also via electric capacity C4,
C3 is grounded, and resistance R4 is connected in parallel on electric capacity C4, and power supply is accessed between electric capacity C4, C3；Operational amplifier U3 end of oppisite phase is via electric capacity
C5 concatenation operation amplifiers U3 output end, resistance R5 is connected in parallel on electric capacity C5, and electric capacity C7 one end is connected to resistance R6 and electricity
Between resistance 20, electric capacity C7 other end ground connection；Operational amplifier U3 output end is also used as ratio via resistance R6, resistance R20
Amplify the output end of difference shaping circuit.
4. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The comparator
One in-phase end receives A phase sinusoidal signal Asin α, and on the one hand the end of oppisite phase of the comparator one connects power supply, as bias voltage, separately
On the one hand it is grounded via an electric capacity C6, the output end output A phase square-wave signals S_A_1 of the comparator one.
5. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The comparator
Two in-phase end receives B phase cosine signal Bcos α, and on the one hand the end of oppisite phase of the comparator two connects power supply, as bias voltage, separately
On the one hand via a capacity earth, the output end output B phase square-wave signals S_B_1 of the comparator two.
6. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The ratio is put
The output end of big difference shaping circuit three connects the in-phase end of the comparator three, and on the one hand the end of oppisite phase of the comparator three connects electricity
Source, as bias voltage, on the other hand via a capacity earth, the output end output reference point R square waves of the comparator three
Signal S_R.
7. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The adder
Including resistance R7~R11, operational amplifier U5；A phase sinusoidal signal Asin α, B phase cosine signal Bcos α respectively via resistance R7,
Resistance R8 concatenation operation amplifiers U5 in-phase end, operational amplifier U5 end of oppisite phase is grounded via resistance R10, and the two of resistance R9
End difference concatenation operation amplifier U5 end of oppisite phase and output end, operational amplifier U5 output end exports A phases via resistance R11
45 ° of phase shift signal Asin (+45 ° of α).
8. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The subtracter
Including resistance R12~R16, operational amplifier U6；A phases sinusoidal signal Asin α are anti-via resistance R12 concatenation operation amplifiers U6's
Xiang Duan, B phase cosine signal Bcos α are via resistance R13 concatenation operation amplifiers U6 in-phase end, operational amplifier U6 in-phase end
It is grounded via resistance R14, resistance R15 two ends difference concatenation operation amplifier U6 end of oppisite phase and output end, operational amplifier
U6 output end is via resistance R16 output signals
9. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The phase inverter
Including resistance R17~R19, operational amplifier U7；SignalInput operational amplifier U7 end of oppisite phase,
Operational amplifier U7 in-phase end is grounded via resistance R17, resistance R18 two ends difference concatenation operation amplifier U7 end of oppisite phase
And output end, operational amplifier U7 output end via resistance R19 export the 45 ° of phase shifts of B phases and reverse signal-Bcos (α+
45°)。
10. the preprocessed chip of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：Sine increases
Amount signal A+ and A-, cosine incremental signals B+ and B-, reference point increment signal R+ and R- are passed in differential signal mode
It is defeated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720083493.9U CN206413000U (en) | 2017-01-22 | 2017-01-22 | A kind of preprocessed chip of increment type sine and cosine encoder signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720083493.9U CN206413000U (en) | 2017-01-22 | 2017-01-22 | A kind of preprocessed chip of increment type sine and cosine encoder signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206413000U true CN206413000U (en) | 2017-08-15 |
Family
ID=59556498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720083493.9U Active CN206413000U (en) | 2017-01-22 | 2017-01-22 | A kind of preprocessed chip of increment type sine and cosine encoder signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206413000U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108801301A (en) * | 2018-05-31 | 2018-11-13 | 苏州汇川技术有限公司 | Encoder system |
| CN111669153A (en) * | 2020-06-18 | 2020-09-15 | 长春汇通光电技术有限公司 | Circuit for improving resolution of sine and cosine encoder |
-
2017
- 2017-01-22 CN CN201720083493.9U patent/CN206413000U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108801301A (en) * | 2018-05-31 | 2018-11-13 | 苏州汇川技术有限公司 | Encoder system |
| CN108801301B (en) * | 2018-05-31 | 2024-02-27 | 苏州汇川技术有限公司 | Encoder system |
| CN111669153A (en) * | 2020-06-18 | 2020-09-15 | 长春汇通光电技术有限公司 | Circuit for improving resolution of sine and cosine encoder |
| CN111669153B (en) * | 2020-06-18 | 2023-06-23 | 长春汇通光电技术有限公司 | Resolution improving circuit of sine and cosine encoder |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106788440A (en) | A kind of pretreatment circuit of increment type sine and cosine encoder signal | |
| CN106803758A (en) | A kind of preprocess method of increment type sine and cosine encoder signal | |
| CN202041221U (en) | Subdividing device of sine/cosine encoder | |
| CN101521480B (en) | Resolution method and resolver for signals of rotating transformer | |
| CN101709983B (en) | On-line actual error compensation system of sine and cosine encoder | |
| CN206413000U (en) | A kind of preprocessed chip of increment type sine and cosine encoder signal | |
| Sun | Analysis and improvement on the structure of variable reluctance resolvers | |
| CN206389353U (en) | A kind of pretreatment circuit of increment type sine and cosine encoder signal | |
| CN106556342B (en) | A kind of grating subdivision device and method based on FPGA | |
| CN204425298U (en) | A kind of faint AC signal amplitude lock-in amplifier | |
| CN201858990U (en) | Device for subdividing sine-cosine signals and encoding data of position sensor | |
| CN108155910A (en) | A kind of high speed sine and cosine encoder coding/decoding method based on FPGA | |
| CN111193453A (en) | Method for realizing rotary soft decoding excitation sine wave by digital signal | |
| CN104567955A (en) | Grating subdivision device and method based on FPGA | |
| CN101093234A (en) | Amplitude calculation apparatus of output signal of encoder and amplitude calculation program of output signal of encoder | |
| CN105676780A (en) | XY motion platform contour control method and device on the basis of fuzzy cerebellum model joint controller | |
| CN206671826U (en) | Brshless DC motor AC signal real-time sampling system | |
| CN101949684B (en) | Movement comparison-based dual-frequency laser interferometer signal high multiple-frequency subdivision system | |
| CN101729071B (en) | High speed sine and cosine subdividing device | |
| Feng et al. | Development of a combined magnetic encoder | |
| CN204925684U (en) | Control device compatible with incremental encoder interface | |
| CN101847996B (en) | Method and device for converting direct-current B code into alternating-current B code | |
| CN205450016U (en) | Motor for electric vehicle rotor speed detector | |
| CN106357172A (en) | Sine-cosine signal processing circuit for speed and positon feedback | |
| LongFei et al. | Optimization of absolute variable reluctance resolver with Taguchi and FEM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |