CN106788440A - A kind of pretreatment circuit of increment type sine and cosine encoder signal - Google Patents
A kind of pretreatment circuit of increment type sine and cosine encoder signal Download PDFInfo
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- CN106788440A CN106788440A CN201710046797.2A CN201710046797A CN106788440A CN 106788440 A CN106788440 A CN 106788440A CN 201710046797 A CN201710046797 A CN 201710046797A CN 106788440 A CN106788440 A CN 106788440A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/64—Analogue/digital converters with intermediate conversion to phase of sinusoidal or similar periodical signals
- H03M1/645—Analogue/digital converters with intermediate conversion to phase of sinusoidal or similar periodical signals for position encoding, e.g. using resolvers or synchros
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Abstract
The invention discloses a kind of pretreatment circuit of increment type sine and cosine encoder signal.Preprocessed signal of the pretreatment circuit output with safety and redundancy feature.Two scaling difference shaping circuits are respectively to sinusoidal increment signal A+ and A, cosine incremental signals B+ and B, 90 ° of Asin α, Bcos α is differed and carries out difference shaping, a pair of phases of scaling generation, then corresponding analog quantity add operation is done by adder, subtracter, phase inverter exporting Asin (+45 ° of α) and-Bcos (+45 ° of α).Asin α and Bcos α are converted to corresponding square-wave signal by two comparators, and carry out crossing redundancy respectively.Last scaling difference shaping circuit coordinates last comparator that a pair of reference point increment signals R+ and R are converted into reference point R square-wave signals.Each frame of preprocessed signal includes nine signals above.
Description
Technical field
It is electric the present invention relates to one kind pretreatment circuit, more particularly to a kind of pretreatment of increment type sine and cosine encoder signal
Road.
Background technology
Signal Pretreatment is to carry out early stage treatment to various types of electric signals, is entered by various expected purposes and requirement
The general designation of row process, seeks to the signal record on certain media and is processed, to extract useful information
Process, it be signal is extracted, is converted, being analyzed, the general designation of the processing procedure such as comprehensive.
Increment type sine and cosine encoder is before coarse position counting or smart position interpolation is carried out, it is necessary to the original of encoder
Beginning signal is pre-processed.On the one hand, pretreatment circuit is the coarse position counting unit in follow-up DSP (digital signal processor)
(coarse position is counted, i.e., first carry out 4 frequencys multiplication to square-wave signal, then calculates the real time position of rotor) provides preferable square wave
Signal source；On the other hand, circuit is pre-processed for the exact position interpolating unit in follow-up DSP provides preferable simulation signal generator.
So-called exact position interpolation, the i.e. a cycle to analog signal carry out time division, are divided into several equal signals
Section, a cycle of original analog signal can only produce a trigger pulse, now pass through interpolation and be divided into several equal letters
Several trigger pulses will be produced after number section.Improve the resolution ratio of number system.For example, certain type increment type sine and cosine encoder
Line number be 2048 (often changing the line of production raw 2048 signal periods), after 4 frequencys multiplication its physical resolution=analog signal a cycle/
4=360*3600/ (2048*4)=158.203125 arcsecond, this numerical value be exactly in DSP coarse position counting unit to motor
Rotor carries out the resolution ratio of position counting.Traditional square-wave signal processing method and circuit to encoder is because 4 cannot be broken through
Frequency multiplication this concept (more frequencys multiplication will cause position signalling distortion), therefore rotor-position number system higher cannot be obtained
Resolution ratio.
The content of the invention
In order to solve the above-mentioned technical problem, the present invention proposes a kind of pretreatment electricity of increment type sine and cosine encoder signal
Road, preprocessed signal of its output with safety and redundancy feature.
Solution of the invention is：A kind of pretreatment circuit of increment type sine and cosine encoder signal, it includes addition
Device, subtracter, phase inverter, three scaling difference shaping circuits, three comparators；The pretreatment circuit is carried for output
The preprocessed signal of safety and redundancy feature, each frame of the preprocessed signal includes signals below：
Asinα：A pair of a pair of the output of increment type sine and cosine encoder sinusoidal increment letters of scaling difference shaping circuit
Number A+ and A-, carries out difference shaping, scaling, generation A phase sinusoidal signal Asin α；
Bcosα：A pair of cosine incrementals letter that scaling difference shaping circuit two is exported to increment type sine and cosine encoder
Number B+ and B-, carries out difference shaping, scaling, generation B phase cosine signal Bcos α；Wherein, A phases sinusoidal signal Asin α and B
The phase of phase cosine signal Bcos α differs 90 °；
Asin(α+45°)：Adder does analog quantity addition to A phase sinusoidal signal Asin α plus B phase cosine signal Bcos α
Computing forms signalMultiplied by with coefficientObtain 45 ° of relative A phase sinusoidal signal Asin α phase shifts
45 ° of phase shift signal Asin of A phases (+45 ° of α)；
- Bcos (+45 ° of α)：Subtracter subtracts A phase sinusoidal signal Asin α to B phase cosine signal Bcos α to be done analog quantity and subtracts
Method computing forms signalMultiplied by with coefficientObtain relative B phase cosine signal Bcos α phase shifts
45 ° of 45 ° of phase shift signal Bcos of B phases (+45 ° of α), then inverted via phase inverter, generation reverse signal-Bcos (+45 ° of α)；
S_A_1：A phase sinusoidal signal Asin α are converted to A phase square-wave signals S_A_1 by comparator one；
S_A_2：S_A_1 carries out the redundancy generation A phase square wave redundant signals S_A_2 that reports to the leadship after accomplishing a task；
S_B_1：B phase cosine signal Bcos α are converted to B phase square-wave signals S_B_1 by comparator two；
S_B_2：S_B_1 carries out the redundancy generation B phase square wave redundant signals S_B_2 that reports to the leadship after accomplishing a task；
S_R：A pair of reference point increments letter that scaling difference shaping circuit three is exported to increment type sine and cosine encoder
Number R+ and R-, carry out difference shaping, it is scaling after reference point R square-wave signals S_R is converted to by comparator three again.
Used as the further improvement of such scheme, it is poor to input signal realization that each scaling difference shaping circuit includes
Divide the difference shaping circuit of shaping and realize scaling scaling circuit.
Used as the further improvement of such scheme, each scaling difference shaping circuit includes resistance R1~R6, resistance
R20, electric capacity C1~C5, electric capacity C7, operational amplifier U1~U3；The same phase of sinusoidal increment signal A+ input operational amplifiers U1
End, the in-phase end of sinusoidal increment signal A- input operational amplifiers U2 is gone here and there between two in-phase ends of operational amplifier U1, U2
Connection resistance R1, and two in-phase ends of operational amplifier U1, U2 distinguish shunt capacitance C1, C2, build single order RC filtering, computing is put
Two end of oppisite phase of big device U1, U2 connect respective output end respectively, form negative-feedback；The output end of operational amplifier U1 via
The in-phase end of resistance R2 concatenation operation amplifiers U3, the output end of operational amplifier U2 is via resistance R3 concatenation operation amplifiers U3
End of oppisite phase, the in-phase end of operational amplifier U3 is also grounded via electric capacity C4, C3, and resistance R4 is connected in parallel on electric capacity C4, electric capacity C4,
Power supply is accessed between C3；Operational amplifier U3 end of oppisite phase via electric capacity C5 concatenation operation amplifiers U3 output end, resistance R5 is simultaneously
It is associated on electric capacity C5, one end of electric capacity C7 is connected between resistance R6 and resistance 20, the other end ground connection of electric capacity C7；Operation amplifier
The output end of device U3 also via resistance R6, resistance R20 as scaling difference shaping circuit output end.
Used as the further improvement of such scheme, the in-phase end of the comparator one receives A phase sinusoidal signal Asin α, the ratio
On the one hand end of oppisite phase compared with device one connects power supply, as bias voltage, is on the other hand grounded via an electric capacity C6, the comparator one
Output end output A phase square-wave signals S_A_1.
Used as the further improvement of such scheme, the in-phase end of the comparator two receives B phase cosine signal Bcos α, the ratio
On the one hand end of oppisite phase compared with device two connects power supply, as bias voltage, on the other hand via a capacity earth, the comparator two
Output end output B phase square-wave signals S_B_1.
Used as the further improvement of such scheme, the output end of the scaling difference shaping circuit three connects the comparator
On the one hand three in-phase end, the end of oppisite phase of the comparator three connects power supply, as bias voltage, is on the other hand connect via an electric capacity
Ground, the output end output reference point R square-wave signals S_R of the comparator three.
Used as the further improvement of such scheme, the adder includes resistance R7~R11, operational amplifier U5；A phases are sinusoidal
Signal Asin α, B phase cosine signal Bcos α are respectively via resistance R7, the in-phase end of resistance R8 concatenation operation amplifiers U5, computing
The end of oppisite phase of amplifier U5 is grounded via resistance R10, the end of oppisite phase of the two ends of resistance R9 difference concatenation operation amplifiers U5 and defeated
Go out end, the output end of operational amplifier U5 exports 45 ° of phase shift signal Asin of A phases (+45 ° of α) via resistance R11.
Used as the further improvement of such scheme, the subtracter includes resistance R12~R16, operational amplifier U6；A phases are just
String signal Asin α via resistance R12 concatenation operation amplifiers U6 end of oppisite phase, B phases cosine signal Bcos α via resistance R13 connect
The in-phase end of operational amplifier U6 is connect, the in-phase end of operational amplifier U6 is grounded via resistance R14, the two ends difference of resistance R15
The end of oppisite phase and output end of concatenation operation amplifier U6, the output end of operational amplifier U6 is via resistance R16 output signals
Used as the further improvement of such scheme, the phase inverter includes resistance R17~R19, operational amplifier U7；SignalThe end of oppisite phase of input operational amplifier U7, the in-phase end of operational amplifier U7 connects via resistance R17
Ground, the end of oppisite phase and output end of the two ends difference concatenation operation amplifier U7 of resistance R18, the output end of operational amplifier U7 via
Resistance R19 exports reverse signal-Bcos (+45 ° of α).
As the further improvement of such scheme, sinusoidal increment signal A+ and A-, cosine incremental signals B+ and B-, reference point
Increment signal R+ and R- are transmitted in differential signal mode.
In the present invention, by the multifunctional signal exported to increment type sine and cosine encoder Signal Pretreatment, under
Trip DSP treatment provides multiple choices, disclosure satisfy that the different degrees of demand of different user.The present invention relates to pretreatment electricity
Road can with hardware description language circuit design of the invention be IP core in FPGA, or even can also manufacture and design as one
The asic chip of individual standard, the present invention is basic research of this area in the national equipment manufacture of lifting, especially to improving friendship
The rotor real time position precision of the execution units such as stream servo permagnetic synchronous motor, has made maximum contribution.
Brief description of the drawings
Fig. 1 is the circuit structure diagram of the pretreatment circuit of increment type sine and cosine encoder signal.
Fig. 2 is that scaling difference shaping circuit one and comparator one are electrically schemed in succession in Fig. 1.
Fig. 3 is emulated respectively by MATLAB to difference shaping circuit one in Fig. 1 and difference shaping circuit two
Phase differs 90 degree of A phases and the cosine and sine signal oscillogram of B phases.
Fig. 4 is emulate the A phase square-wave signal figures for obtaining to comparator in Fig. 1 one by MATLAB.
Fig. 5 is the circuit diagram of adder in Fig. 1.
Fig. 6 is emulate the signal output waveform figure for obtaining to circuit in Fig. 4 by MATLAB.
Fig. 7 is the circuit connection diagram of subtracter and phase inverter in Fig. 1.
Fig. 8 is emulate the signal output waveform figure for obtaining to circuit in Fig. 7 by MATLAB.
Fig. 9 is that the two paths of signals ASin (a+45 °) and-Bcos (a+45 °) of final output are compared in MATLAB
Signal waveforms.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Also referring to Fig. 1 to Fig. 9, the pretreatment circuit of increment type sine and cosine encoder signal of the invention is used to export
Preprocessed signal with safety and redundancy feature, this is the larger difference existed and conventional pretreatment signal between.
Fig. 1 is referred to, should pre-process circuit includes three scaling difference shaping circuits, 1~3, three comparators 4~6, addition
Device 7, subtracter 8, phase inverter 9.
Each frame of the preprocessed signal include signals below Asin α, Bcos α, Asin (+45 ° of α) ,-Bcos (α+
45°)、S_A_1、S_A_2、S_B_1、S_B_2、S_R。
Asinα：A pair of a pair of the output of increment type sine and cosine encoder sinusoidal increment letters of scaling difference shaping circuit
Number A+ and A-, carries out difference shaping, scaling, generation A phase sinusoidal signal Asin α.
Bcosα：A pair of cosine incrementals letter that scaling difference shaping circuit two is exported to increment type sine and cosine encoder
Number B+ and B-, carries out difference shaping, scaling, generation B phase cosine signal Bcos α；Wherein, A phases sinusoidal signal Asin α and B
The phase of phase cosine signal Bcos α differs 90 °.
Asin(α+45°)：Adder 7 does analog quantity addition to A phase sinusoidal signal Asin α plus B phase cosine signal Bcos α
Computing forms signalMultiplied by with coefficientObtain 45 ° of relative A phase sinusoidal signal Asin α phase shifts
45 ° of phase shift signal Asin of A phases (+45 ° of α).
- Bcos (+45 ° of α)：Subtracter 8 subtracts A phase sinusoidal signal Asin α to B phase cosine signal Bcos α to be done analog quantity and subtracts
Method computing forms signalMultiplied by with coefficientObtain relative B phase cosine signal Bcos α phase shifts
45 ° of 45 ° of phase shift signal Bcos of B phases (+45 ° of α), then inverted via phase inverter 9, generation reverse signal-Bcos (+45 ° of α).
S_A_1：A phase sinusoidal signal Asin α are converted to A phase square-wave signals S_A_1 by comparator one.
S_A_2：S_A_1 carries out crossing redundancy generation A phase square wave redundant signals S_A_2.
S_B_1：B phase cosine signal Bcos α are converted to B phase square-wave signals S_B_1 by comparator two.
S_B_2：S_B_1 carries out redundancy generation B phase square wave redundant signals S_B_2.
S_R：A pair of reference point increments letter that scaling difference shaping circuit three is exported to increment type sine and cosine encoder
Number R+ and R-, carry out difference shaping, it is scaling after reference point R square-wave signals S_R is converted to by comparator three again.Wherein, just
String increment signal A+ and A-, cosine incremental signals B+ and B-, reference point increment signal R+ and R- are entered in differential signal mode
Row transmission.
It is pointed out that emphasis of the invention and not lying in three scaling difference shaping circuits, 1~3, three ratios
Compared with these parts such as device 4~6, adder circuit 7, subtracter 8, phase inverters 9 in itself, refer to main by these parts (three
Scaling difference shaping circuit 1~3, three comparators 4~6, adder circuit 7, subtracter 8, phase inverters 9 etc.) constitute
This design of preprocessed signal of the output with safety and redundancy feature required for completing the present invention.Just as circuit, group
Resistance, inductance, chip into circuit etc. inherently exist in the prior art, but not because the presence of which, just anticipate
Taste the circuit being made up of them must be obvious, must be the conventional selection of those skilled in the art, otherwise just be hindered
Hinder constantly bringing forth new ideas for circuit, just run counter to the purpose of Patent Law.The present invention is intended by herein：Cut-off the present patent application
Before, electrical structure as the pretreatment circuit of increment type sine and cosine encoder signal of the invention is not retrieved, is designed
Going out the pretreatment circuit of increment type sine and cosine encoder signal of the invention needs to pay creative work, at least art technology
Personnel never have do so mistake.
Defined according to Heidenhain encoder interfaces, for the typical amplitude of 1VPP sine and cosine increment output voltage signals A and B
It is 1VPP, phase difference is 90 ° of Electron Angular.Interface signal is three pairs of differential signals.In pretreatment circuit of the invention, in order to
The phase signals of A, B two i.e. A phases sinusoidal signal Asin α, B phases cosine signal Bcos α are obtained, it is necessary to carry out difference to differential signal whole
Shape, scaling etc..Simultaneously in order to each obtain the square-wave signal (side of being primarily referred to as by comparator by the phase signals of A, B two
Ripple signal), the low and high level of acquisition need to meet the requirement such as sampling A/D chip or FPGA pins.
Incorporated by reference to Fig. 2, each scaling difference shaping circuit may include to realize input signal the difference of difference shaping
Shaping circuit and realize scaling scaling circuit.In the present embodiment, each scaling difference shaping circuit bag
Include resistance R1~R6, resistance R20, electric capacity C1~C5, electric capacity C7, operational amplifier U1~U3.
The in-phase end of sinusoidal increment signal A+ input operational amplifiers U1, sinusoidal increment signal A- input operational amplifiers
Two of the in-phase end of U2, series resistance R1 between two in-phase ends of operational amplifier U1, U2, and operational amplifier U1, U2
In-phase end distinguishes shunt capacitance C1, C2, builds single order RC filtering, and two end of oppisite phase of operational amplifier U1, U2 are connected respectively respectively
From output end, formed negative-feedback.The output end of operational amplifier U1 via resistance R2 concatenation operation amplifiers U3 in-phase end,
The output end of operational amplifier U2 via resistance R3 concatenation operation amplifiers U3 end of oppisite phase, the in-phase end of operational amplifier U3 is also
It is grounded via electric capacity C4, C3, resistance R4 is connected in parallel on electric capacity C4, and power supply is accessed between electric capacity C4, C3.Operational amplifier U3 is anti-phase
Hold via the output end of electric capacity C5 concatenation operation amplifiers U3, resistance R5 is connected in parallel on electric capacity C5, and one end of electric capacity C7 is connected to
Between resistance R6 and resistance 20, the other end ground connection of electric capacity C7.The output end of operational amplifier U3 is also via resistance R6, resistance
R20 as scaling difference shaping circuit output end.
The output end of scaling difference shaping circuit 1 connects the in-phase end of the comparator 1, makes the comparator one
In-phase end receives A phase sinusoidal signal Asin α, and on the one hand the end of oppisite phase of the comparator 1 connects power Vcc, as bias voltage, separately
On the one hand it is grounded via an electric capacity C6, the output end output A phase square-wave signals S_A_1 of the comparator 1.Similarly, ratio is put
The output end of big difference shaping circuit 22 connects the in-phase end of the comparator 25, the in-phase end of the comparator two is received B phases
On the one hand cosine signal Bcos α, the end of oppisite phase of the comparator 25 connects power supply (not shown), as bias voltage, on the other hand passes through
It is grounded by an electric capacity (not shown), the output end output B phase square-wave signals S_B_1 of the comparator 25.Scaling difference is whole
The output end of shape circuit 33 connects the in-phase end of the comparator 36, and on the one hand the end of oppisite phase of the comparator 36 connects power supply (schemes not
Show), as bias voltage, on the other hand it is grounded via an electric capacity (not shown), the output end output reference of the comparator 36
Point R square-wave signals S_R.
It is that a pair of amplitudes of 90 degree of difference are the difference of 1V by encoder interfaces sinusoidal increment signal A phases and B phases out
, with B phases be respectively processed differential signal A phases here by signal.By taking differential signal A+ and A- as an example, amplify respectively through two-way
Device U1 and U2 are amplified, and entering back into amplifier U3 carries out difference integration, exports sinusoidal signal Asin α all the way, and amplitude range is
0V~3.3V, while by sinusoidal signal Asin α input comparator U4, by the bias voltage of 1.5V, being joined according to comparator characteristic
Number, is similar to the signal of square wave all the way, and amplitude range is 0.4V~2.6V.Fig. 4 and Fig. 3 are respectively to figure by MATLAB
Difference shaping circuit emulate the A phases and the cosine and sine signal ripple of B phases of square-wave signal and 90 degree of the phase difference for obtaining in 1
Shape.
Incorporated by reference to Fig. 5, adder includes resistance R7~R11, operational amplifier U5.Asin α, Bcos α are respectively via resistance
The in-phase end of R7, R8 concatenation operation amplifier U5, the end of oppisite phase of operational amplifier U5 is grounded via resistance R10, and the two of resistance R9
The output end of the end of oppisite phase and output end of concatenation operation amplifier U5 respectively, operational amplifier U5 is held to be exported via resistance R11
Asin(α+45°)。
This partial circuit is difference shaping, scaling and compare single channel, generation A phase sinusoidal signal Asin α.Finally lead to
The bias voltage for crossing 1.5V is compared, the square-wave signal that output low level is 0.4V, high level is 2.6V, i.e. A phases square wave letter
Number S_A.The resistance that anti-phase adder circuit 7 passes through feedback resistance, with 0.707 (i.e.) ratio carry out product.
90 degree of cosine and sine signal Asin α and Bcos α, input are differed in the two-way phase exported by difference shaping circuit
The end in the same direction of adder U5, while two-phase cosine and sine signal amplitude is equal.To meet：
Make to meet above-mentioned relation coefficient by adjusting the resistance value of resistance R8, R7, R10 and R9 in Fig. 5.
Disconnected according to void, input in the same direction does not have electric current to pass through, and causes the electric current by resistance R8 and R7 equal, by resistance
The electric current of R10 and R9 is also equal.
Therefore：
It is disconnected according to void,
V+=V-
It can thus be concluded that going out：
Fig. 6 is emulate the signal output waveform for obtaining to circuit by MATLAB, in figure 6 it can be seen that in addition
Device holds input A phases and the phase signals of B phases two in the same direction, by after adder treatment, waveform can 45 ° of phase shift, amplitude increase about 1.414
Times, by adjusting the resistance value of resistance R8, R7, R10 and R9, amplitude is reduced 0.707 times, just can obtain output signal Asin
The waveform of (+45 ° of α).
Incorporated by reference to Fig. 7, the subtracter includes resistance R12~R16, operational amplifier U6.A phases sinusoidal signal Asin α via
The end of oppisite phase of resistance R12 concatenation operation amplifiers U6, B phases cosine signal Bcos α are via resistance R13 concatenation operation amplifiers U6's
In-phase end, the in-phase end of operational amplifier U6 is grounded via resistance R14, and concatenation operation amplifier U6 is distinguished at the two ends of resistance R15
End of oppisite phase and output end, the output end of operational amplifier U6 is via resistance R16 output signals
The phase inverter includes resistance R17~R19, operational amplifier U7.SignalInput computing
The end of oppisite phase of amplifier U7, the in-phase end of operational amplifier U7 is grounded via resistance R17, and the two ends of resistance R18 connect fortune respectively
Calculate the end of oppisite phase and output end of amplifier U7, the output end of operational amplifier U7 is via resistance R19 output 45 ° of phase shifts of B phases and anti-
Rotaring signal-Bcos (+45 ° of α).
And for the exact position interpolating unit in DSP, time division is carried out to a cycle of analog signal and is inserted
Value, for example, be divided into 8 equal portions, then the resolution ratio=analog signal a cycle/8=360*3600/ (2048*8) after interpolation
=79.1015625 arcseconds, this numerical value is the rotor-position for carrying out being obtained after 8 grades point interpolation subdividing to a signal period
Number system resolution ratio, it is clear that this resolution ratio coarse position count resolution improves 1 times.Illustrate again, one high-accuracy
CNC machine requirement rotor-position precision ± 5 arcsecond, then need to carry out a signal period quantity of interpolation subdividing=
360*3600/ (2*5*2048)=63.28125, i.e., need to only carry out the interpolation processing of 64 deciles to a signal period, it is possible to
It is less than the rotor-position precision of ± 5 arcseconds.
DSP except receive from pretreatment circuit signal Asin α and Bcos α, and carry out accordingly rotor real time position and
Real-time speed calculates outer (the rough position counting of rotor real time position of the offer to motor and the computing function of exact position interpolation
It), DSP also receives safety signal Asin (+45 ° of α) and-Bcos (+45 ° of α) from pretreatment circuit, and safety letter accordingly
Rotor real time position number being carried out again and real-time speed being calculated, DSP is to rotor real time position and two groups of calculating knots of real-time speed
Fruit carries out intersection comparing, and compared result performs safety operation.
90 degree of cosine and sine signal Asin α and Bcos α, input are differed in the two-way phase exported by difference shaping circuit
Subtracter is not held in the same direction, and two-phase cosine and sine signal amplitude is equal, at the same the output signal input inverter that will be obtained carry out it is anti-phase.
To meet：
Make to meet above-mentioned relation coefficient by adjusting the resistance value of resistance R13, R12, R14 and R15 in Fig. 7.
Disconnected according to void, U6 inputs in the same direction do not have electric current to pass through, and cause the electric current by resistance R12 and R13 equal, pass through
The electric current of resistance R14 and R15 is also equal.
Therefore：
It is disconnected according to void,
V+=V-
It can thus be concluded that going out：
The amplitude that will be obtained increases in about 1.414 times of cosine signal input inverter, by adjusting resistance R16 and R18
Resistance size, make amplitude reduce 0.707 times, reverse-phase 180 degree.
In U7, the end in the same direction ground connection of amplifier.According to short, the reverse terminal voltage 0V of void.It is disconnected according to void, reverse input end input
High resistance, does not almost have electric current input and output, and resistance R16 and R18 series connection, the electric current by resistance R16 and R18 are equal.
By the electric current of resistance R16：
By the electric current of resistance R18：I7=(V_-Vout)/R18
Disconnected, the V according to void+=V_
It can thus be concluded that going out：
Fig. 8 is emulate the signal output waveform for obtaining to Fig. 7 circuits by MATLAB, be can see in figure, is being subtracted
Musical instruments used in a Buddhist or Taoist mass not in the same direction end input A phases and the phase signals of B phases two, by subtracter treatment after, waveform can 45 ° of phase shift, by adjust R13,
The resistance value of R12, R14 and R15, makes amplitude increase about 1.414 times, obtains output signalWaveform
By adjusting the resistance value of R16 and R18, make amplitude reduce 0.707 times, while carry out it is anti-phase, just can obtain output signal-
The waveform of Bcos (+45 ° of α).
Fig. 9 is that the two paths of signals Asin (+45 ° of α) and-Bcos (+45 ° of α) of final output are compared in MATLAB
Compared with, from the point of view of the starting point of output signal, after adder and subtracter are processed with phase inverter, two-way cosine and sine signal Asin
(+45 ° of α) and-Bcos (+45 ° of α) have 135 ° of phase difference, but connect from the continuity of signal, signal after treatment
All it is have 90 degree of phase difference as A phases and the phase signals of B phases two.So, the phase difference of signal section start can be what is ignored.
Treatment to code device signal, including DSP treatment (rough position is counted and exact position interpolation) and encoder letter
Number pretreatment.Treatment especially to increment type sine and cosine encoder signal is that acquisition servo motor rotor real time position is (especially high
Resolution ratio rotor real time position) crucial and unique approach, be high-accuracy CNC machine, servo manipulator, numerical control rotary work
The execution units such as platform, multifunctional numerical control angular milling head, electro spindle improve necessity of axis servomotor (containing linear axis and rotary shaft) precision
Material base.The technology for the treatment of (counting and safety) and the always national equipment manufacture of digitlization to code device signal is short
Plate, in order to break technical monopoly, lifting China high-grade, digitally controlled machine tools, the position detection of AC servo transmission and the feedback essence in west
Degree, has risen to national height.《Intelligent manufacturing equipment innovation and development engineering construction scheme》(hair changes skill high [2014] 2072
Number) file requires to realize AC synchronous sampling internal control and measuring unit in the description on Whole Digit AC Servo System
Total digitalization.What the AC synchronous sampling internal control mentioned in file and measuring unit referred to is exactly that CNC fields widely use
AC servo permagnetic synchronous motor and motor in cosine and sine signal encoder.It can be seen that, to cosine and sine signal code device signal
Treatment meaning importance.
Have considerable document to propose carries out 4 frequencys multiplication to the square-wave signal of encoder (mainly TTL signal encoder)
Then the circuit or method of rough position counting are carried out again；There is little document to point out, to the mould of increment type sine and cosine encoder
Intending signal carries out squared treatment, is converted into square-wave signal, then using the method for similar process square-wave signal encoder, carries out
Rough position is counted, such as patent document ZL201520574867.8, ZL201520570360.5,201510465550.5,
201510467898.8,201510465547.3,201610517319.0,201610518856.7,2016120690307.3
(hereinafter referred to as patent document combination) all refer to the analog signal of increment type sine and cosine encoder to be converted into square-wave signal right
The method for carrying out rough position counting again afterwards；Patent document combination also refers to the analog signal to increment type sine and cosine encoder
Carry out phase shift carries out exact position interpolation equal to pretreatment and then recycling DSP, so as to obtain more accurate servo motor rotor
The technological process of real time position；In addition patent document combination also refer to the technological process of safe coding device signal.Patent document
Combination is without the theoretical foundation for proposing the detailed implementation method of pretreatment circuit and realize with it.
In addition, for the secrecy for strengthening pre-processing code device signal and post-processing, developed country takes more special than applying
Sharp more effective way, that is, design the IP core of code device signal pretreatment and post processing, and design circuit and algorithm packaging are arrived
In IP core, user's purchase is used, it is impossible to know why so use；Even manufacture and design special asic chip.
Treatment to code device signal, including DSP treatment and code device signal pre-process two parts, and two parts all have ten
Divide important effect, it is indispensable.Algorithm process is mainly responsible in DSP treatment, is theoretical foundation；Code device signal pretreatment is responsible for
It is material base for DSP algorithm provides suitable signal source.It is proposed by the present invention to the pre- of increment type sine and cosine encoder signal
Treatment is responsible for DSP treatment (not describing in the present case) and provides signal source, and particular content is：The tunnel of A+, A-, B+, B-, R+, R- six
The increment type of original (symbol A, B, R used herein of the invention are only used for distinguishing signal phase, as follows without amplitude implication)
9 road signals are generated after the pretreatment circuit of the encoded device signal of sine and cosine encoder differential signal (amplitude 1VPP), there is provided give
DSP processing units, square-wave signal S_B_1 and S_A_1 are supplied to the rough position of DSP processing units to count one (not in this case
In), for the rough counting to servo motor rotor real time position；It is single that square-wave signal S_B_2 and S_A_2 are supplied to DSP to process
The rough position of unit counts two (not in the present case), for the rough counting to servo motor rotor real time position, rough position
Count one and two pair of count results and perform safety operation and CRC redundancy checks；S_R is that rotor is completely enclosed plus a signal, and each S-R is arrived
Come, rough position counts one and two and resets, and completely encloses counter+1；Asin α and Bcos α are supplied to the accurate position of DSP processing units
Interpolation one (not in the present case) is put, is counted for the interpolation subdividing to the accurate real time position of servo motor rotor；Asin(α+
45 °) and-Bcos (+45 ° of α) be supplied to the exact position interpolation two (not in the present case) of DSP processing units, for servo electricity
The interpolation subdividing of the accurate real time position of machine rotor is counted；Exact position interpolation one and the two pairs of count results perform safety operations and
CRC redundancy checks.
The invention has the advantages that：Not only propose a kind of side pre-processed to increment type sine and cosine encoder signal
Method, additionally provides an implementing circuit for practicality；Not only increment type sine and cosine encoder Signal Pretreatment is believed with obtaining square wave
Number coarse position counting is carried out, also increment type sine and cosine encoder signal is nursed one's health to obtain analog signalses, for accurate
Position interpolation；Normal rough position counting not only is carried out to the square-wave signal for obtaining, another road is also generated for DSP treatment
Perform the square-wave signal of safety operation；Normal exact position interpolation not only is carried out to the analog signal for obtaining, also by phase shift
The analog signal that another road performs safety operation for DSP treatment is obtained Deng treatment.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of pretreatment circuit of increment type sine and cosine encoder signal, it is characterised in that：It include adder, subtracter,
Phase inverter, three scaling difference shaping circuits, three comparators；The pretreatment circuit is used to export with safety and redundancy
The preprocessed signal of function, each frame of the preprocessed signal includes signals below：
Asinα：A pair of a pair of the output of increment type sine and cosine encoder sinusoidal increment signal A+ of scaling difference shaping circuit
And A-, carry out difference shaping, scaling, generation A phase sinusoidal signal Asin α；
Bcosα：A pair of cosine incremental signals B+ that scaling difference shaping circuit two is exported to increment type sine and cosine encoder
And B-, carry out difference shaping, scaling, generation B phase cosine signal Bcos α；Wherein, more than A phases sinusoidal signal Asin α and B phases
The phase of string signal Bcos α differs 90 °；
Asin(α+45°)：Adder does analog quantity add operation to A phase sinusoidal signal Asin α plus B phase cosine signal Bcos α
Form signalMultiplied by with coefficientObtain the A phases of 45 ° of relative A phase sinusoidal signal Asin α phase shifts
45 ° of phase shift signal Asin (+45 ° of α)；
- Bcos (+45 ° of α)：Subtracter subtracts A phase sinusoidal signal Asin α to B phase cosine signal Bcos α and does analog quantity subtraction fortune
Calculation forms signalMultiplied by with coefficientObtain 45 ° of relative B phase cosine signal Bcos α phase shifts
45 ° of phase shift signal Bcos of B phases (+45 ° of α), then inverted via phase inverter, generation reverse signal-Bcos (+45 ° of α)；
S_A_1：A phase sinusoidal signal Asin α are converted to A phase square-wave signals S_A_1 by comparator one；
S_A_2：S_A_1 carries out crossing redundancy generation A phase square wave redundant signals S_A_2；
S_B_1：B phase cosine signal Bcos α are converted to B phase square-wave signals S_B_1 by comparator two；
S_B_2：S_B_1 carries out crossing redundancy generation B phase square wave redundant signals S_B_2；
S_R：A pair of reference point increment signal R+ that scaling difference shaping circuit three is exported to increment type sine and cosine encoder
And R-, carry out difference shaping, it is scaling after reference point R square-wave signals S_R is converted to by comparator three again.
2. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：Each ratio
Amplifying difference shaping circuit includes realizing input signal the difference shaping circuit of difference shaping and realizes scaling ratio
Amplifying circuit.
3. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：Each ratio
Amplifying difference shaping circuit includes resistance R1~R6, resistance R20, electric capacity C1~C5, electric capacity C7, operational amplifier U1~U3；Just
The in-phase end of string increment signal A+ input operational amplifiers U1, the in-phase end of sinusoidal increment signal A- input operational amplifiers U2,
Series resistance R1 between two in-phase ends of operational amplifier U1, U2, and operational amplifier U1, U2 two in-phase ends respectively simultaneously
Connection electric capacity C1, C2, build single order RC filtering, and two end of oppisite phase of operational amplifier U1, U2 connect respective output end, shape respectively
Into negative-feedback；The output end of operational amplifier U1 via resistance R2 concatenation operation amplifiers U3 in-phase end, operational amplifier U2
Output end via resistance R3 concatenation operation amplifiers U3 end of oppisite phase, the in-phase end of operational amplifier U3 also via electric capacity C4,
C3 is grounded, and resistance R4 is connected in parallel on electric capacity C4, and power supply is accessed between electric capacity C4, C3；Operational amplifier U3 end of oppisite phase is via electric capacity
The output end of C5 concatenation operation amplifiers U3, resistance R5 is connected in parallel on electric capacity C5, and one end of electric capacity C7 is connected to resistance R6 and electricity
Between resistance 20, the other end ground connection of electric capacity C7；The output end of operational amplifier U3 is also via resistance R6, resistance R20 as ratio
Amplify the output end of difference shaping circuit.
4. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The comparator
One in-phase end receives A phase sinusoidal signal Asin α, and on the one hand the end of oppisite phase of the comparator one connects power supply, as bias voltage, separately
On the one hand it is grounded via an electric capacity C6, the output end output A phase square-wave signals S_A_1 of the comparator one.
5. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The comparator
Two in-phase end receives B phase cosine signal Bcos α, and on the one hand the end of oppisite phase of the comparator two connects power supply, as bias voltage, separately
On the one hand via a capacity earth, the output end output B phase square-wave signals S_B_1 of the comparator two.
6. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The ratio is put
The output end of big difference shaping circuit three connects the in-phase end of the comparator three, and on the one hand the end of oppisite phase of the comparator three connects electricity
Source, as bias voltage, on the other hand via a capacity earth, the output end output reference point R square waves of the comparator three
Signal S_R.
7. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The adder
Including resistance R7~R11, operational amplifier U5；A phase sinusoidal signal Asin α, B phase cosine signal Bcos α respectively via resistance R7,
The in-phase end of resistance R8 concatenation operation amplifiers U5, the end of oppisite phase of operational amplifier U5 is grounded via resistance R10, and the two of resistance R9
The output end of the end of oppisite phase and output end of concatenation operation amplifier U5 respectively, operational amplifier U5 is held to export A phases via resistance R11
45 ° of phase shift signal Asin (+45 ° of α).
8. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The subtracter
Including resistance R12~R16, operational amplifier U6；A phases sinusoidal signal Asin α are anti-via resistance R12 concatenation operation amplifiers U6's
Xiang Duan, B phase cosine signal Bcos α via resistance R13 concatenation operation amplifiers U6 in-phase end, the in-phase end of operational amplifier U6
It is grounded via resistance R14, the end of oppisite phase and output end of concatenation operation amplifier U6, operational amplifier are distinguished in the two ends of resistance R15
The output end of U6 is via resistance R16 output signals
9. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：The phase inverter
Including resistance R17~R19, operational amplifier U7；SignalThe end of oppisite phase of input operational amplifier U7,
The in-phase end of operational amplifier U7 is grounded via resistance R17, and the end of oppisite phase of concatenation operation amplifier U7 is distinguished at the two ends of resistance R18
And output end, the output end of operational amplifier U7 is via resistance R19 outputs reverse signal-Bcos (+45 ° of α).
10. the pretreatment circuit of increment type sine and cosine encoder signal as claimed in claim 1, it is characterised in that：Sine increases
Amount signal A+ and A-, cosine incremental signals B+ and B-, reference point increment signal R+ and R- are passed in differential signal mode
It is defeated.
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