CN206364778U - A kind of electric capacity based on latch is to difference dynamic comparer - Google Patents
A kind of electric capacity based on latch is to difference dynamic comparer Download PDFInfo
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- CN206364778U CN206364778U CN201621374068.7U CN201621374068U CN206364778U CN 206364778 U CN206364778 U CN 206364778U CN 201621374068 U CN201621374068 U CN 201621374068U CN 206364778 U CN206364778 U CN 206364778U
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Abstract
The utility model discloses a kind of electric capacity based on latch to difference dynamic comparer, belong to the technical field of Digital Analog Hybrid Circuits.Dynamic comparer includes：Latched comparator, controlling switch unit and coupled capacitor unit.Controlling switch unit is entirely only comprising six switches, coupled capacitor unit is only comprising two electric capacity, the function of difference dynamic comparer is realized with the circuit structure comprising fewer number of electric capacity and switch, while input offset voltage is substantially reduced to coupled capacitor sensitivity, the precision of comparator is improved.
Description
Technical field
The utility model discloses a kind of electric capacity based on latch to difference dynamic comparer, belong to Digital Analog Hybrid Circuits
Technical field.
Background technology
In the design of digital-to-analogue mixed signal processing chip, analog-to-digital conversion module is used widely, particularly pipeline organization
Advantage in ADC structures makes main selection in the industry.High-speed comparator as pipeline ADC module core list
Member, its speed, power consumption, precision and noiseproof feature directly determine the quality of A/D converter with high speed and high precision quality.Based on lock
The electric capacity difference of storage is contrasted compared with device because the advantage that its is low in energy consumption, speed is fast, precision is high is used widely in the adc.
Traditional dynamic latch comparator is as shown in Figure 1.Circuit is by latched comparator 1, controlling switch unit 2 and coupling electricity
Hold the composition of Unit 3.Latched comparator 1 is by first to fourth PMOS PM1~PM4 and first to the 5th NMOS tube NM1~NM5 groups
Into.First PMOS PM1 grid meets clock signal CK, and source electrode connects supply voltage, and drain electrode meets positive polarity output terminal mouthful Vop；The
Two PMOS PM2 grid meets negative polarity output mouthful Von, and source electrode connects supply voltage, and drain electrode meets positive polarity output terminal mouthful Vop；
3rd PMOS PM3 grid meets positive polarity output terminal mouthful Vop, and source electrode connects supply voltage, and drain electrode connects negative polarity output mouthful
Von；4th PMOS PM4 grid meets clock signal CK, and source electrode connects supply voltage, and drain electrode meets negative polarity output mouthful Von；The
One NMOS tube NM1 grid meets negative polarity output mouthful Von, and source electrode connects the 3rd NMOS tube NM3 drain electrode, and it is defeated that drain electrode connects positive polarity
Exit port Vop；Second NMOS tube NM2 grid meets positive polarity output terminal mouthful Vop, and source electrode connects the 4th NMOS tube NM4 drain electrode, leaks
Pole meets negative polarity output mouthful Von；3rd NMOS tube NM3 grid meets the first input capacitance Cin1Bottom crown, source electrode connects the 5th
NMOS tube NM5 drain electrode, drain electrode connects the first NMOS tube NM1 source electrode；4th NMOS tube NM4 grid connects the second input capacitance
Cin2Bottom crown, source electrode connects the 5th NMOS tube NM5 drain electrode, and drain electrode connects the second NMOS tube NM2 source electrode；5th NMOS tube NM5
Grid meet clock signal CK, source ground, drain electrode and the 3rd NMOS tube NM3 source electrode and the 4th NMOS tube NM4 source electrode
It is connected.
Controlling switch unit 2 is made up of first to the tenth switch K1~K10, a first switch K1 termination negative polarity differential
Signal input port Vin, another the first input capacitance of termination Cin1Top crown；Second switch K2 termination the first input electricity
Hold Cin1Top crown, the other end ground connection；A 3rd switch K3 second reference voltage signal input port V of terminationref-, it is another
Terminate the first reference capacitance Cref1Top crown；A 4th switch K4 first reference capacitance C of terminationref1Top crown, the other end
Ground connection；A 5th switch K5 first reference capacitance C of terminationref1Bottom crown, the other end ground connection；A 6th switch K6 termination
Positive polarity differential signal input port Vip, another the second input capacitance of termination Cin2Top crown；A 7th switch K7 termination
Second input capacitance Cin2Top crown, the other end ground connection；A 8th switch K8 first reference voltage signal input port of termination
Vref+, the second reference capacitance C of another terminationref2Top crown；A 9th switch K9 second reference capacitance C of terminationref2Upper pole
Plate, other end ground connection；A tenth switch K10 second reference capacitance C of terminationref2Bottom crown, the other end ground connection.
Coupled capacitor unit 3 is by the first input capacitance Cin1, the second input capacitance Cin2, the first reference capacitance Cref1, second
Reference capacitance Cref2Composition.First input capacitance Cin1Top crown be connected with first switch K1 and second switch K2 tie point,
Bottom crown connects the 3rd NMOS tube NM3 grid；Second input capacitance Cin2Top crown and the 6th switch K6 and the 7th switch K7
Tie point is connected, and bottom crown connects the 4th NMOS tube NM4 grid；First reference capacitance Cref1Top crown and the 3rd switch K3 and
4th switch K4 tie point is connected, and bottom crown connects the 3rd NMOS tube NM3 grid；Second reference capacitance Cref2Top crown with
8th switch K8 and the 9th switch K9 tie point are connected, and bottom crown connects the 4th NMOS tube NM4 grid.
Traditional latched comparator can realize relatively low power consumption and relatively high conversion speed, but the circuit is maximum
Have the disadvantage mismatch.The factor of the traditional latched comparator mismatch of influence has external factor and internal factor.Internal factor is divided at random
Property and systemic mismatch；The mismatch of the factor such as control signal that external factor is primarily input and configuration, includes input clock letter
Number and reference voltage, the mismatch of current reference etc..
As Fig. 1, φ 1 and φ 2 be a pair of non-overlapping clock signals, it is assumed that second switch K2, the 4th K4, the 7th K7 and
9th K9 is turned on when φ 1 is high level, and first switch K1, the 3rd switch K3, the 5th switch K5, the 6th switch K6, the 8th open
The switch K10 of K8 and the tenth are closed to turn on when φ 2 is high level.When φ 1 is that low level, φ 2 are high level, the first input capacitance
The quantity of electric charge at Cin1 two ends is：QCin1=VinCcin1, the quantity of electric charge at the first reference capacitance Cref1 two ends is：QCref1=Vref-
Cref1, can similarly obtain, the quantity of electric charge at the second input capacitance Cin2 two ends is：QCin2=VipCcin2, the second reference capacitance Cref2 two
The quantity of electric charge at end is：QCref2=Vref+Cref2；When φ 2 is that low level, φ 1 are high level, the 3rd can be obtained by charge conservation
NMOS tube NM3 grid voltage is：4th NMOS tube NM4 grid voltage is：Ignoring the first input capacitance Cin1With the second input capacitance Cin2Mismatch and the first reference capacitance Cref1
With the second reference capacitance Cref2On the premise of mismatch, it is assumed that Cin1=Cin2=Cin, Cref1=Cref2=Cref, then：Then obtain comparing threshold point voltage be：
Comparing threshold point can be by adjusting CrefAnd CinValue enter Mobile state adjustment, but note that and compare threshold point
Magnitude of voltage obtained on the premise of capacitance mismatch is ignored, have in practice consider mismatch to performances such as circuit precision
Influence.Another drawback is exactly the controlling switch unit and coupled capacitor unit of the conventional dynamic latched comparator shown in Fig. 1
Employ 4 electric capacity and 10 switches altogether, and electric capacity can occupy sizable area in domain, so directly result in chip into
This rising.
Utility model content
Goal of the invention of the present utility model is that there is provided a kind of electricity based on latch for above-mentioned background technology not enough
Hold to difference dynamic comparer, the work(of difference dynamic comparer is realized with the circuit structure comprising fewer number of electric capacity and switch
Can, solve the technical problem that existing electric capacity has capacitance mismatch to difference dynamic comparer.
The utility model is adopted the following technical scheme that for achieving the above object：
A kind of electric capacity based on latch to difference dynamic comparer, including：
Latched comparator, with in-phase input end, inverting input, clock signal input terminal, positive polarity output terminal and negative
Polarity output terminal,
Controlling switch unit, comprising：Control the sampling of negative polarity differential signal and adjusted according to external reference signal to latch
First subelement of comparator anti-phase input terminal voltage, controls the sampling of positive polarity differential signal and is adjusted according to external reference signal
The second subelement of latched comparator homophase input terminal voltage is saved, and,
Coupled capacitor unit, comprising：The first isolation that the negative polarity differential signal born to its top crown is sampled
Under the second isolation capacitance that electric capacity, the positive polarity differential signal born to its top crown are sampled, the first isolation capacitance
Pole plate connects the inverting input of latched comparator, and the bottom crown of the second isolation capacitance connects the in-phase input end of latched comparator.
It is used as further prioritization scheme of the electric capacity based on latch to difference dynamic comparer, the first of the first subelement
Input termination negative polarity differential signal, second input the first reference voltage signal of termination, the 3rd input termination common mode voltage signal,
The top crown of first, second output the first isolation capacitance of termination, the bottom crown of the 3rd output the first isolation capacitance of termination.
Further, the electric capacity based on latch includes to the first subelement in difference dynamic comparer：First switch,
Second switch, the 3rd switch, the electric current of the first switch flow into termination negative polarity differential signal, and the electric current of second switch is flowed into
Terminate the first reference voltage signal, the electric current of the 3rd switch flows into termination common mode voltage signal, first switch and second switch
Top crown of the electric current outflow end with the first isolation capacitance is connected, under electric current outflow the first isolation capacitance of termination of the 3rd switch
Pole plate.
Further, the electric capacity based on latch is in the first subelement of difference dynamic comparer, first, second,
3rd switch is single PMOS or single NMOS tube or the transmission gate being made up of PMOS and NMOS tube.
It is used as further prioritization scheme of the electric capacity based on latch to difference dynamic comparer, the first of the second subelement
Input termination positive polarity differential signal, second input the second reference voltage signal of termination, the 3rd input termination common mode voltage signal,
The top crown of first, second output the second isolation capacitance of termination, the bottom crown of the 3rd output the second isolation capacitance of termination.
Further, the electric capacity based on latch includes to the second subelement in difference dynamic comparer：4th switch,
5th switch, the 6th switch, the electric current of the 4th switch flow into termination positive polarity differential signal, and the electric current of the 5th switch is flowed into
The second reference voltage signal is terminated, the electric current of the 6th switch flows into termination common mode voltage signal, the 4th switch and the 5th switch
Top crown of the electric current outflow end with the second isolation capacitance is connected, under electric current outflow the second isolation capacitance of termination of the 6th switch
Pole plate.
Further, the electric capacity based on latch is in the second subelement of difference dynamic comparer, the four, the 5th,
6th switch is single PMOS or single NMOS tube or the transmission gate being made up of PMOS and NMOS tube.
As further prioritization scheme of the electric capacity based on latch to difference dynamic comparer, latched comparator includes：
First to fourth PMOS, the first to the 5th NMOS tube, the grid of the first PMOS, the grid of the 4th PMOS, the 5th NMOS
The grid of pipe and the clock signal input terminal after connecing as latched comparator, the source electrode of first to fourth PMOS simultaneously connect and are followed by electricity
Source, the drain electrode of the first PMOS, the drain electrode of the second PMOS, the drain electrode of the first NMOS tube, the grid of the 3rd POMS pipes, second
The grid of NMOS tube and the positive polarity output terminal after connecing as latched comparator, the grid of the second PMOS, the first NMOS tube
Grid, the drain electrode of the 3rd PMOS, the drain electrode of the second NMOS tube, the drain electrode of the 4th PMOS connect together and compared as latch
The negative polarity output of device, the source electrode of the first NMOS tube connects the drain electrode of the 3rd NMOS tube, and the source electrode of the second NMOS tube connects the 4th
The drain electrode of NMOS tube, the source electrode of the 3rd NMOS tube is connected with the source electrode of the 4th NMOS tube, the drain electrode of the 5th NMOS tube, and the 3rd
The grid of NMOS tube is as the inverting input of latched comparator, and the grid of the 4th NMOS tube is used as the same mutually defeated of latched comparator
Enter end, the source electrode of the 5th NMOS tube is with connecing power supply.
The utility model uses above-mentioned technical proposal, has the advantages that：
(1) in the dynamic comparer that the utility model is related to, coupled capacitor unit is only comprising two electric capacity, controlling switch list
Member only comprising six switches, realizes external reference signal and differential signal to lock by the conductings of six switches of control with shut-off
The transmission of comparator input terminal is deposited, compares threshold point voltage by adjusting differential signal reference value and can adjust, reduces electric capacity
The influence of paired comparisons threshold point voltage is lost, the comparison precision of comparator is improved, input imbalance is substantially reduced to coupled capacitor
Sensitivity；
(2) external reference signal introduces common mode voltage signal so that the voltage of the input of latched comparator two is in common mode
Swung near voltage, be conducive to the steady operation of latched comparator；
(3) coupled capacitor unit is isolated to external reference signal and differential signal, it is to avoid input signal and benchmark
Signal is coupled via the feedthrough of NMOS gate-source capacitances, is conducive to lifting a circuit performance for high speed dynamic comparer.
Brief description of the drawings
Fig. 1 is conventional dynamic latched comparator.
Fig. 2 is electric capacity differential pair dynamic comparer of the utility model based on latch.
Label declaration in figure：1 is latched comparator, and 2 be controlling switch unit, and 3 be coupled capacitor unit, and PM1 to PM4 is
First to fourth PMOS, NM1 to NM5 is the first to the 5th NMOS tube, and K1 to K10 is the first to the tenth switch, Cin1And Cin2
For the first and second input capacitances, Cref1And Cref2For the first and second reference capacitances, C1 and C2 are the first and second coupling electricity
Hold, φ 1 and φ 2 are a pair of non-overlapping clock signals.
Embodiment
The technical scheme to utility model is described in detail below in conjunction with the accompanying drawings.
The comparator that the utility model is related to is as shown in Fig. 2 by latched comparator 1, controlling switch unit 2 and coupling electricity
Hold unit 3 to constitute.Latched comparator 1 is by first to fourth PMOS PM1~PM4 and first to the 5th NMOS tube NM1~NM5 groups
Into.First PMOS PM1 grid meets clock signal CK, and source electrode connects supply voltage, and drain electrode meets positive polarity output terminal mouthful Vop；The
Two PMOS PM2 grid meets negative polarity output mouthful Von, and source electrode connects supply voltage, and drain electrode meets positive polarity output terminal mouthful Vop；
3rd PMOS PM3 grid meets positive polarity output terminal mouthful Vop, and source electrode connects supply voltage, and drain electrode connects negative polarity output mouthful
Von；4th PMOS PM4 grid meets clock signal CK, and source electrode connects supply voltage, and drain electrode meets negative polarity output mouthful Von；The
One NMOS tube NM1 grid meets negative polarity output mouthful Von, and source electrode connects the 3rd NMOS tube NM3 drain electrode, and it is defeated that drain electrode connects positive polarity
Exit port Vop；Second NMOS tube NM2 grid meets positive polarity output terminal mouthful Vop, and source electrode connects the 4th NMOS tube NM4 drain electrode, leaks
Pole meets negative polarity output mouthful Von；3rd NMOS tube NM3 grid connects the first isolation capacitance C1 bottom crown, and source electrode connects the 5th
NMOS tube NM5 drain electrode, drain electrode connects the first NMOS tube NM1 source electrode；4th NMOS tube NM4 grid meets the second isolation capacitance C2
Bottom crown, source electrode connects the 5th NMOS tube NM5 drain electrode, and drain electrode connects the second NMOS tube NM2 source electrode；5th NMOS tube NM5's
Grid meets clock signal CK, and source ground, drain electrode is connected with the 3rd NMOS tube NM3 source electrode and the 4th NMOS tube NM4 source electrode
Connect.Controlling switch unit 2 is made up of first to the 6th switch K1~K6, wherein, a first switch K1 termination negative polarity differential
Signal input port Vin, another the first isolation capacitance of termination C1 top crown；Second switch K2 first reference voltage of termination
Signal input port Vref+, the first isolation capacitance C1 of another termination top crown；A 3rd switch K3 termination common-mode signal is defeated
Inbound port Vcom, another the first isolation capacitance of termination C1 bottom crown；A 4th K4 termination positive polarity differential signal input part
Mouth Vin, another the second isolation capacitance of termination C2 top crown；A 5th switch K5 second reference voltage signal input of termination
Mouth Vref-, the second isolation capacitance C2 of another termination top crown；A 6th switch K6 termination common-mode signal input port Vcom,
The first isolation capacitance C1 of another termination bottom crown.Controlling switch can be separately formed by PMOS or NMOS, also can by PMOS and
The transmission gate of NMOS compositions is constituted.Coupled capacitor unit 3 is made up of the first isolation capacitance C1 and the second isolation capacitance C2, wherein,
First isolation capacitance C1 top crown is connected with first switch K1 and second switch K2 tie point, and bottom crown connects the 3rd NMOS tube
NM3 grid；Second isolation capacitance C2 top crown is connected with the 4th switch K4 and the 5th switch K5 tie point, and bottom crown connects
4th NMOS tube NM4 grid.
In Fig. 2, φ 1 and φ 2 and be a pair of non-overlapping clock signals, it is assumed that first switch K1 and the 4th K4 are in φ 2
Turned on during for high level, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 are led when φ 1 is high level
It is logical.When φ 1 is that high level, φ 2 are low level, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 are led
Logical, the switches of first switch K1 and the 4th K4 ends, and the first isolation capacitance C1 two ends quantity of electric charge is：Q1=(Vref+-Vcom)C1, second
The isolation capacitance C2 two ends quantity of electric charge is：Q2=(Vref--Vcom)C2；When φ 1 is that low level, φ 2 are high level, second switch
K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 cut-offs, the switch K4 conductings of first switch K1 and the 4th are kept according to electric charge
Perseverance, can obtain C1 bottom crown voltages is：V1=Vcom-(Vref+-Vin), can similarly obtain C2 bottom crown terminal voltages is：V2=
Vcom-(Vref--Vip), two formulas are subtracted each other, and are obtained：
V1-V2=(Vin-Vip)-(Vref+-Vref-),
It is hereby achieved that comparing threshold point voltage and being：Vip-Vin=Vref--Vref+。
From above formula it can be found that：
(1) compare threshold point voltage unrelated with electric capacity, only have relation with two input reference voltages, compared to tradition
Dynamic latch comparator, the mismatch of electric capacity is unrelated compared with threshold point (influenceing very little in other words) by contrast, and this can greatly improve ratio
Compared with the comparison precision of device.
(2) quantity of MOS switch is reduced to six, and the use of electric capacity is reduced to two, and the electric capacity can be set
Smaller, compared to the domain of traditional circuit, the area that electric capacity is occupied in domain is substantially reduced, and reduces being manufactured into for circuit
This.
(3) by isolation capacitance C1 and C2, input signal and reference signal are isolated, it is to avoid input signal and benchmark
Signal is coupled via the feedthrough of NMOS gate-source capacitances, and in high speed applications, this point is very heavy for the lifting of circuit performance
Want.In addition, from analysis above it is recognised that V1 and V2 value is simply swung near common-mode voltage, this compares for latching
Steady operation compared with device is very good.
Above content is preferred embodiment of the present utility model, but it cannot be assumed that specific implementation of the present utility model
It is confined to this, it is noted that on the premise of the utility model principle is not departed from, simple modifications and modification to circuit all should
It is considered as protection domain of the present utility model.
Claims (8)
1. a kind of electric capacity based on latch is to difference dynamic comparer, it is characterised in that including：
Latched comparator（1）, with in-phase input end, inverting input, clock signal input terminal, positive polarity output terminal and negative pole
Property output end,
Controlling switch unit（2）, comprising：Control the sampling of negative polarity differential signal and ratio is latched according to external reference signal regulation
Compared with the first subelement of device anti-phase input terminal voltage, control the sampling of positive polarity differential signal and adjusted according to external reference signal
Second subelement of latched comparator homophase input terminal voltage, and,
Coupled capacitor unit（3）, comprising：The first isolation electricity that the negative polarity differential signal born to its top crown is sampled
The second isolation capacitance that the positive polarity differential signal hold, born to its top crown is sampled, the lower pole of the first isolation capacitance
Plate connects the inverting input of latched comparator, and the bottom crown of the second isolation capacitance connects the in-phase input end of latched comparator.
2. a kind of electric capacity based on latch is to difference dynamic comparer according to claim 1, it is characterised in that described
The first input end of one subelement connects negative polarity differential signal, second input the first reference voltage signal of termination, the 3rd input
Connect common mode voltage signal, the top crown of first, second output the first isolation capacitance of termination, the 3rd output the first isolation capacitance of termination
Bottom crown.
3. a kind of electric capacity based on latch is to difference dynamic comparer according to claim 2, it is characterised in that described
One subelement includes：First switch, second switch, third switch, the electric current of the first switch flows into termination negative polarity differential
Signal, the electric current of second switch flows into the first reference voltage signal of termination, and the electric current of the 3rd switch flows into termination common-mode voltage letter
Number, the top crown of the electric current outflow end of first switch and second switch with the first isolation capacitance is connected, the electric current of the 3rd switch
The bottom crown of outflow the first isolation capacitance of termination.
4. a kind of electric capacity based on latch is to difference dynamic comparer according to claim 3, it is characterised in that described
First, second, third switch is single PMOS or single NMOS tube or the transmission gate being made up of PMOS and NMOS tube.
5. a kind of electric capacity based on latch is to difference dynamic comparer according to claim 1, it is characterised in that described
The first input end of two subelements connects positive polarity differential signal, second input the second reference voltage signal of termination, the 3rd input
Connect common mode voltage signal, the top crown of first, second output the second isolation capacitance of termination, the 3rd output the second isolation capacitance of termination
Bottom crown.
6. a kind of electric capacity based on latch is to difference dynamic comparer according to claim 5, it is characterised in that described
Two subelements include：4th switch, the 5th switch, the 6th switch, the electric current of the 4th switch flow into termination positive polarity differential
Signal, the electric current of the 5th switch flows into the second reference voltage signal of termination, and the electric current of the 6th switch flows into termination common-mode voltage letter
Number, the top crown of the 4th switch and the 5th electric current outflow end switched with the second isolation capacitance is connected, the electric current of the 6th switch
The bottom crown of outflow the second isolation capacitance of termination.
7. a kind of electric capacity based on latch is to difference dynamic comparer according to claim 6, it is characterised in that described
4th, the five, the 6th switches are single PMOS or single NMOS tube or the transmission gate being made up of PMOS and NMOS tube.
8. a kind of electric capacity based on latch is to difference dynamic comparer according to claim 1, it is characterised in that the lock
Deposit comparator（1）Including：First to fourth PMOS, the first to the 5th NMOS tube, the grid of the first PMOS, the 4th PMOS
Grid, the grid of the 5th NMOS tube and the clock signal input terminal after connecing as latched comparator, first to fourth PMOS
Source electrode and connect and be followed by power supply, the drain electrode of the first PMOS, the drain electrode of the second PMOS, the drain electrode of the first NMOS tube, the 3rd
The grid of POMS pipes, the grid of the second NMOS tube and the positive polarity output terminal after connecing as latched comparator, the second PMOS
Grid, the grid of the first NMOS tube, the drain electrode of the 3rd PMOS, the drain electrode of the second NMOS tube, the drain electrode of the 4th PMOS simultaneously connect
Together as the negative polarity output of latched comparator, the source electrode of the first NMOS tube connects the drain electrode of the 3rd NMOS tube, second
The source electrode of NMOS tube connects the drain electrode of the 4th NMOS tube, the source electrode of the 3rd NMOS tube and source electrode, the 5th NMOS tube of the 4th NMOS tube
Drain electrode be connected, the grid of the 3rd NMOS tube is used as the inverting input of latched comparator, the grid conduct of the 4th NMOS tube
The in-phase input end of latched comparator, the source electrode of the 5th NMOS tube is with connecing power supply.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201621374068.7U CN206364778U (en) | 2016-12-14 | 2016-12-14 | A kind of electric capacity based on latch is to difference dynamic comparer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788352A (en) * | 2016-12-14 | 2017-05-31 | 无锡芯响电子科技有限公司 | A kind of electric capacity based on latch is to difference dynamic comparer |
| CN108667447A (en) * | 2018-04-13 | 2018-10-16 | 上海华力集成电路制造有限公司 | Latch circuit |
| CN108806757A (en) * | 2018-06-19 | 2018-11-13 | 广州领知信息技术有限公司 | High-speed boosting type signal sampling transmitting switch |
-
2016
- 2016-12-14 CN CN201621374068.7U patent/CN206364778U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788352A (en) * | 2016-12-14 | 2017-05-31 | 无锡芯响电子科技有限公司 | A kind of electric capacity based on latch is to difference dynamic comparer |
| CN108667447A (en) * | 2018-04-13 | 2018-10-16 | 上海华力集成电路制造有限公司 | Latch circuit |
| CN108806757A (en) * | 2018-06-19 | 2018-11-13 | 广州领知信息技术有限公司 | High-speed boosting type signal sampling transmitting switch |
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