CN206363894U - A kind of low ESL surface-mount types array of capacitors - Google Patents
A kind of low ESL surface-mount types array of capacitors Download PDFInfo
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- CN206363894U CN206363894U CN201621350581.2U CN201621350581U CN206363894U CN 206363894 U CN206363894 U CN 206363894U CN 201621350581 U CN201621350581 U CN 201621350581U CN 206363894 U CN206363894 U CN 206363894U
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Abstract
The utility model discloses a kind of low ESL surface-mount types array of capacitors, including：Ceramic capacitor body, electrode, the second inner electrode, the first external electrode and the second external electrode in first；Ceramic capacitor body includes being printed with multi-layer ceramics diaphragm, neighbouring two-layer ceramic diaphragm in electrode and the second inner electrode in first be arranged alternately；One end of electrode from ceramic diaphragm length direction extends to the other end in first, and one end of the second inner electrode from ceramic diaphragm width extends to the other end；The first external electrode coats the exit of electrode in all first, and the second external electrode coats the exit of all the second inner electrodes.The utility model effectively realizes the miniaturization and densification of electronic circuit, can effectively reduce cost of manufacture and suppresses the too low phenomenons of product E SR.
Description
Technical field
The utility model is related to MLCC capacitor technologies field, more particularly to a kind of low ESL surface-mount types array of capacitors.
Background technology
In the power circuit for being equipped with large scale compound integration (LSI), between reduction power line and ground connection
Impedance, reduces the voltage pulsation brought by impedance, need between power line and ground connection decoupling capacitor in parallel.And then remove power line
Middle parasitic noise, and can quickly be powered in power supply voltage variation, make circuit stability.
Common solution：In LSI neighbouring configuration tens or even hundred capacitors, which improves the number of element
Amount, adds installing space, while adding production cost.
Feed-through capacitor in LSI vicinity generally has inter-digitated capacitor (IDC) and length and width to reverse capacitor (LICC),
With relatively low ESL, but it is only a single capacitor, it is impossible to reduce component usage quantity.
Other increasing with the electrode for capacitors number of plies, product E SR is further reduced, with large scale compound integration
(LSI) chip causes resonance point impedance nearby to increase extremely, influences the stabilization of circuit in use, can have parallel resonance phenomenon.
With the miniaturization and densification of electronic circuit, such as mobile phone, the miniaturization of PAD mobile devices, high frequency are needed
Ask, demand can not be met using such scheme.
Utility model content
Weak point present in regarding to the issue above, the utility model provides a kind of low ESL surface-mount types array of capacitors.
To achieve the above object, the utility model provides a kind of low ESL surface-mount types array of capacitors, including：Ceramic condenser
Device main body, electrode, the second inner electrode, the first external electrode and the second external electrode in first；
The ceramic capacitor body includes being printed with multi-layer ceramics diaphragm, neighbouring two-layer ceramic diaphragm in alternating
Electrode and the second inner electrode in the first of arrangement；One end of electrode from ceramic diaphragm length direction extends to another in described first
End, one end of the second inner electrode from ceramic diaphragm width extends to the other end；
The first external electrode coats the exit of electrode in all described first, and the second external electrode coats all institutes
State the exit of the second inner electrode.
As further improvement of the utility model, the first external electrode and the second external electrode by the first conductive layer,
Second conductive layer and the 3rd conductive layer are constituted；
The exit of electrode or the second inner electrode and ceramic capacitor master is extended in first conductive layer cladding first
Body side surface is attached on the end face of ceramic capacitor body；
Second conductive layer is coated on first conductive layer；
3rd conductive layer is coated on second conductive layer.
As further improvement of the utility model, the thickness of first conductive layer is 5~50um；
Second conductive layer, the thickness of the 3rd conductive layer are 3~10um, wherein：In low ESL surface-mount types capacitor battle array
In the case that row are installed using scolding tin, second conductive layer selects electroplated Ni layer, and the 3rd conductive layer is from plating Sn or Sn-Pb
Rotating fields；In the case where low ESL surface-mount types array of capacitors is using electrically conductive adhesive or wire bonding installation, described second
Conductive layer selects electroplated Ni layer, and the 3rd conductive layer is from Au layers of plating on Ni layers.
Being provided with as further improvement of the utility model, between second conductive layer and the 3rd conductive layer is used to relax
The conductive resin layer of stress.
As further improvement of the utility model, the turning of the ceramic capacitor body and seamed edge are arc-shaped.
As further improvement of the utility model, the thickness of the ceramic diaphragm is 3um~10um；
Electrode, the thickness of the second inner electrode are 0.5~2.0um in described first.
Compared with prior art, the beneficial effects of the utility model are：
A kind of low ESL surface-mount types array of capacitors disclosed in the utility model, it effectively realizes the small-sized of electronic circuit
Change and densification, can effectively reduce cost of manufacture and suppress the too low phenomenon of product E SR.
Brief description of the drawings
Fig. 1 is low ESL surface-mount types array of capacitors structure chart disclosed in a kind of embodiment of the utility model；
Fig. 2 is the sectional view of Fig. 1 length directions；
Fig. 3 is the sectional view of Fig. 1 widths；
Fig. 4 is Fig. 1 internal breakup figure.
1st, ceramic capacitor body；2nd, ceramic diaphragm；3rd, electrode in first；4th, the second inner electrode；5th, the first external electrode；6、
The second external electrode；7th, the first conductive layer；8th, the second conductive layer；9th, the 3rd conductive layer.
Embodiment
It is new below in conjunction with this practicality to make the purpose, technical scheme and advantage of the utility model embodiment clearer
Accompanying drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that retouched
The embodiment stated is a part of embodiment of the present utility model, rather than whole embodiments.Based on the reality in the utility model
Apply example, the every other embodiment that those of ordinary skill in the art are obtained on the premise of creative work is not made, all
Belong to the scope of the utility model protection.
The utility model is described in further detail below in conjunction with the accompanying drawings：
Embodiment 1：
As Figure 1-4, in order to solve existing issue, the utility model provides a kind of low ESL surface-mount types array of capacitors,
The low ESL surface-mount types array of capacitors is 6 termination capacitors, and it includes：Electrode 3, second in ceramic capacitor body 1, first
Interior electrode 4, the first external electrode 5 and the second external electrode 6.
As shown in figure 1, the utility model ceramic capacitor body 1 symmetrical cube structure, ceramic condenser for around
The turning of device main body 1 and seamed edge are arc-shaped.As Figure 2-3, ceramic capacitor body 1 of the present utility model is by multi-layer ceramics
Submission is printed with the stepped construction that electrode 3, the second inner electrode 4 are constituted in diaphragm 2, first, neighbouring two-layer ceramic diaphragm 2
For electrode 3 and the second inner electrode 4 in the first of arrangement；I.e.：Electrode 3 in first, lower floor's ceramics are printed with upper strata ceramic diaphragm 2
The second inner electrode 4 is printed with diaphragm 2, then other be printed with the ceramic diaphragm 2 of electrode 3 or the second inner electrode 4 in first with
This is alternately arranged.Wherein, one end of electrode 3 from the length direction of ceramic diaphragm 2 extends to the other end, the second inner electrode 4 in first
The other end is extended to from one end of the width of ceramic diaphragm 2.Electrode 3 is monolithic electrode, second in first in the utility model
Interior electrode 4 is three side-by-side electrodes, as shown in Figure 4.
Preferred 3um~the 10um of thickness of the utility model ceramic diaphragm 2, is used as the ceramic material for constituting ceramic diaphragm 2, energy
It is enough to use for example with BaTiO3、CaTiO3、SrTiO3、CaZrO3Deng the dielectric ceramics diaphragm as principal component.In addition, also may be used
With first using Mn compounds, Mg compounds, Si compounds, Co compounds, Ni compounds, terres rares is added in these principal components
The material of the accessory ingredients such as plain compound.
Thickness preferably 0.5~2.0um of electrode 3, the second inner electrode 4 in the utility model first, as in composition first
The conductive material of electrode 3, the second inner electrode 4, such as can use Ni, Cu, Ag, Pd, Ag-Pd alloy, Au.
As Figure 1-3, the first external electrode 5 of the present utility model is coated outside the exit of electrode 3 in all first, first
Electrode 5 is provided with two altogether, is respectively coated by the left end and right-hand member of electrode 3 in first, as shown in Figure 1, 2；The second external electrode 6 coats institute
There is the exit of the second inner electrode 4, the second external electrode 6 is according to the number of the second inner electrode 4 altogether provided with outside six and adjacent second
It is placed equidistant between electrode 6, is respectively coated by the front-end and back-end of the second inner electrode 4, as shown in Figure 1,3.Wherein：
The first external electrode 5 and the second external electrode 6 of the present utility model are by the first conductive layer 7, the second conductive layer 8 and the 3rd
Conductive layer 9 is constituted；First conductive layer 7 cladding first in electrode 3 or the second inner electrode 4 exit and extend to ceramic capacitor
The side attachment of main body 1 is on the end face of ceramic capacitor body 1, and the second conductive layer 8 is coated on the first conductive layer 7, and the 3rd leads
Electric layer 9 is coated on the second conductive layer 8.
Thickness preferably 5~50um of the first conductive layer of the utility model 7, the first conductive layer 7 is the layer that conductive material is made
Shape structure, conductive material includes the one or more in Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, or Cu, Ni, Ag, Pd, Ag-Pd
One or more, glass and metal oxide in alloy, Au.I.e.：First conductive layer 7 is closed using Cu, Ni, Ag, Pd, Ag-Pd
Gold, Au etc..In other the first external electrode 5 and the second external electrode 6 dispatch from foreign news agency of the first external electrode 5 and second can be improved comprising glass etc.
The connection reliability of electrode 3 and the second inner electrode 4, adds metal oxide in addition in especially the first conductive layer 7 and first of pole 6
To improve the compactness of the first conductive layer 7, to improve the moisture-proof of product.
The utility model the second conductive layer 8, the thickness of the 3rd conductive layer 9 are preferably 3~10um, wherein：In low ESL Surface Mounts
In the case that formula array of capacitors is installed using scolding tin, the second conductive layer 8 selects electroplated Ni layer, and the 3rd conductive layer 9 is from plating
Sn or Sn-Pb Rotating fields；Situation about being installed in low ESL surface-mount types array of capacitors using electrically conductive adhesive or wire bonding
Under, the second conductive layer 8 selects electroplated Ni layer, and the 3rd conductive layer 9 is from Au layers of plating on Ni layers.
The utility model can be also provided between the second conductive layer 8 and the 3rd conductive layer 9 is used for the conductive tree for relaxing stress
Lipid layer.
Embodiment 2：
The utility model provides a kind of preparation method of low ESL surface-mount types array of capacitors, including：Porcelain slurry is scattered, curtain coating
Electrode, cross laminates, even pressure, cutting, plastic removal, sintering, chamfering, painting end and burning end process in ceramic diaphragm, printing；It is wherein specific
Including：
Step 1, porcelain slurry are scattered, curtain coating ceramic diaphragm；Porcelain slurry is used for example with BaTiO3、CaTiO3、SrTiO3、CaZrO3
Deng being used as principal component；In addition it is also possible to using addition Mn compounds, Mg compounds, Si compounds, Coization in these principal components
The material of the accessory ingredients such as compound, Ni compounds, rare-earth element compound；The ceramics of 3um~10um thickness are prepared by curtain coating
Diaphragm.
Step 2, electrode or the second inner electrode, and alternately laminated obtained green compact in printing first on ceramic diaphragm；Wherein：
Step 21, on ceramic diaphragm by pattern printing electrocondution slurry of the screen printing mode according to determination, form the
Electrode or the second inner electrode in one；Electrocondution slurry forms thick using the slurry of the formation such as Ni, Cu, Ag, Pd, Ag-Pd alloy, Au
Spend for electrode and the second inner electrode in 0.5~2.0um first；
Step 22, by without printing first in electrode or the second inner electrode protection cap with ceramic diaphragm stack specified layer
Number, the ceramic diaphragm for being printed with internal electrode pattern (electrode or the second inner electrode in first) is stacked gradually thereon, and at it
The protection cap ceramic diaphragm of upper stacking specified layer number, to make green compact.
Step 3, green compact are carried out to even pressure, cutting, plastic removal, sintering, chamfering ceramic capacitor body is made；Wherein：
Green compact are subjected to even pressure by the method for isostatic pressed；
Green compact after even pressure are cut into defined size, unprocessed green bodies are cut out；Now pass through roller chamfering
Deng, make unprocessed green bodies corner part or rib portion carry arc, chamfered can be also carried out after sintering；
Green bodies are fired, firing temperature is determined by the material of ceramic diaphragm or interior electrode, but preferably 900 DEG C
~1300 DEG C.
Step 4, painting end is carried out to electrode leads to client, the second inner electrode exit in the first of ceramic capacitor body, burnt
The first external electrode and the second external electrode is made in end；Wherein：
Step 41, electrode leads to client in the first of ceramic capacitor body abutted against with being covered with the platform of electrocondution slurry,
Ceramic capacitor is immersed in slurry and sintered, the first conductive layer of the first external electrode is made；Wherein, electrocondution slurry using Ni,
The slurry of the formation such as Cu, Ag, Pd, Ag-Pd alloy, Au, sintering temperature be 700~900 DEG C, as sintering when atmosphere, suitably
Use air or N2Etc. atmosphere；
Step 42, by the second inner electrode exit of ceramic capacitor body with conductive paste to each in second
Electrode leads to client is coated and sintered, and the first conductive layer of the second external electrode is made；Applying end herein and using makes ceramic capacitor
Main body is contacted with the extruding of fixture narrow slit, electrocondution slurry is adhered to porcelain body via narrow slit, and then be applied to banding.Wherein, lead
Plasma-based material is using the slurry of the formation such as Ni, Cu, Ag, Pd, Ag-Pd alloy, Au, and the sintering temperature is for 700~900 DEG C and higher than step
Rapid 41 sintering temperature, is air or N as atmosphere during sintering2Etc. atmosphere；
Step 43, the second conductive layer of formation is electroplated on all first conductive layers according to electroplating technology, in the second conductive layer
Upper plating forms the 3rd conductive layer；Wherein, in the case where low ESL surface-mount types array of capacitors is installed using scolding tin, second leads
Electric layer selects electroplated Ni layer, and the 3rd conductive layer is from plating Sn or Sn-Pb Rotating fields；Adopted in low ESL surface-mount types array of capacitors
In the case of being installed with electrically conductive adhesive or wire bonding, the second conductive layer selects electroplated Ni layer, and the 3rd conductive layer selects Ni
Au layers are electroplated on layer.
Step 5, the preparation for completing low ESL surface-mount types array of capacitors.
Embodiment 3：
Can diminish with the increase product E SR of the electrode number of plies, as a result the small capacitance itself having with LSI chips it
Between produced by parallel resonance resonance point on impedance uprise.If the ESR reductions of capacitor are excessive, exist due to antiresonance
Influence and function is decoupled in specific frequency band the problem of reduce.
In the present embodiment, the first conductive layer includes resistance components；Thus, resistant series are in low ESL surface-mount types electric capacity
The electric capacity of device array capacitor, so as to improve the ESR of low ESL surface-mount types array of capacitors capacitor.It is preferred that low ESL surface-mount types electricity
The ESR of vessel array capacitor is 10m Ω~1000m Ω, more preferably 50m Ω~500m Ω.Furthermore it is preferred that the first conductive layer
Ratio resistance be the Ω cm of 0.005 Ω cm~1.0, the Ω cm of more preferably 0.01 Ω cm~0.1.
Above-mentioned resistance components are higher including the metal and glass included in general outer electrode, in addition to ratio resistance
Composition, metal oxide such as than glass.
It is used as metal oxide, such as In-Sn oxides, La-Cu oxides, Sr-Fe oxides, Ca-Sr-Ru oxides
Composite oxides.Because these oxides and Ni reactivity are good, therefore in the case of using these oxides, preferably adopt
It is used as the conductive material for above-mentioned interior electrode 3,4 with Ni or Ni alloys.Improve external electrode 5 and 6, especially first
The connection reliability of conductive layer and interior electrode 3,4.
The purpose of this utility model is to provide a kind of low ESL surface-mount types array of capacitors and preparation method thereof, its have with
Lower advantage：
The utility model effectively realizes the miniaturization and densification of electronic circuit；
The utility model can effectively reduce cost of manufacture；
The utility model can effectively suppress the too low phenomenons of product E SR.
The utility model is not limited to low ESL surface-mount types array of capacitors described above, can also be applied to other layers
Folded ceramic electronic components.For example, can be to be sent out as current-limiting components in the case where constituting ceramic main body by based varistor
The monolithic ceramic electronic component of function is waved, can be to be used as temperature-sensitive in the case where constituting ceramic main body by thermistor ceramics
The monolithic ceramic electronic component of resistance function.
Preferred embodiment of the present utility model is these are only, the utility model is not limited to, for this area
Technical staff for, the utility model can have various modifications and variations.It is all it is of the present utility model spirit and principle within,
Any modification, equivalent substitution and improvements made etc., should be included within protection domain of the present utility model.
Claims (6)
1. a kind of low ESL surface-mount types array of capacitors, it is characterised in that including：Ceramic capacitor body (1), electrode in first
(3), the second inner electrode (4), the first external electrode (5) and the second external electrode (6)；
The ceramic capacitor body (1) includes being printed with submission on multi-layer ceramics diaphragm (2), neighbouring two-layer ceramic diaphragm
For electrode (3) and the second inner electrode (4) in the first of arrangement；Electrode (3) is from ceramic diaphragm (2) length direction in described first
One end extends to the other end, and the second inner electrode (4) extends to the other end from one end of ceramic diaphragm (2) width；
The first external electrode (5) coats the exit of electrode (3) in all described first, the second external electrode (6) cladding
The exit of all the second inner electrodes (4).
2. low ESL surface-mount types array of capacitors as claimed in claim 1, it is characterised in that the first external electrode (5) and the
Two external electrodes (6) are constituted by the first conductive layer (7), the second conductive layer (8) and the 3rd conductive layer (9)；
The exit of electrode (3) or the second inner electrode (4) and ceramic condenser is extended in first conductive layer (7) cladding first
Device main body (1) side attachment is on the end face of ceramic capacitor body (1)；
Second conductive layer (8) is coated on first conductive layer (7)；
3rd conductive layer (9) is coated on second conductive layer (8).
3. low ESL surface-mount types array of capacitors as claimed in claim 2, it is characterised in that the thickness of first conductive layer (7)
Spend for 5~50um；
Second conductive layer (8), the thickness of the 3rd conductive layer (9) they are 3~10um, wherein：In low ESL surface-mount types capacitor
In the case that array is installed using scolding tin, second conductive layer (8) selects electroplated Ni layer, and the 3rd conductive layer (9) is from plating
Sn or Sn-Pb Rotating fields；Situation about being installed in low ESL surface-mount types array of capacitors using electrically conductive adhesive or wire bonding
Under, second conductive layer (8) selects electroplated Ni layer, and the 3rd conductive layer (9) is from Au layers of plating on Ni layers.
4. low ESL surface-mount types array of capacitors as claimed in claim 2, it is characterised in that second conductive layer (8) and the
The conductive resin layer for being used for relaxing stress is provided between three conductive layers (9).
5. low ESL surface-mount types array of capacitors as claimed in claim 1, it is characterised in that the ceramic capacitor body (1)
Turning and seamed edge be arc-shaped.
6. low ESL surface-mount types array of capacitors as claimed in claim 1, it is characterised in that the thickness of the ceramic diaphragm (2)
For 3um~10um；
Electrode (3), the thickness of the second inner electrode (4) are 0.5~2.0um in described first.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621350581.2U CN206363894U (en) | 2016-12-09 | 2016-12-09 | A kind of low ESL surface-mount types array of capacitors |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621350581.2U CN206363894U (en) | 2016-12-09 | 2016-12-09 | A kind of low ESL surface-mount types array of capacitors |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106710879A (en) * | 2016-12-09 | 2017-05-24 | 北京元六鸿远电子科技股份有限公司 | Low ESL surface mount capacitor array and preparation method thereof |
| CN111739734A (en) * | 2019-03-25 | 2020-10-02 | Tdk株式会社 | Electronic component |
-
2016
- 2016-12-09 CN CN201621350581.2U patent/CN206363894U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106710879A (en) * | 2016-12-09 | 2017-05-24 | 北京元六鸿远电子科技股份有限公司 | Low ESL surface mount capacitor array and preparation method thereof |
| CN111739734A (en) * | 2019-03-25 | 2020-10-02 | Tdk株式会社 | Electronic component |
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