CN206332035U - A kind of photovoltaic cell and photovoltaic module - Google Patents
A kind of photovoltaic cell and photovoltaic module Download PDFInfo
- Publication number
- CN206332035U CN206332035U CN201621474467.0U CN201621474467U CN206332035U CN 206332035 U CN206332035 U CN 206332035U CN 201621474467 U CN201621474467 U CN 201621474467U CN 206332035 U CN206332035 U CN 206332035U
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- China
- Prior art keywords
- line electrode
- silicon chip
- gate line
- main grid
- grid line
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Photovoltaic Devices (AREA)
Abstract
The utility model discloses a kind of photovoltaic cell and photovoltaic module, including photovoltaic cell, silicon chip, main grid line electrode, secondary gate line electrode and middle gate line electrode, the photovoltaic cell includes silicon chip, main grid line electrode, secondary gate line electrode and middle gate line electrode, some secondary gate line electrodes are evenly distributed with the top of the silicon chip, it is connected between the multiple silicon chip by main grid line electrode, the main grid line electrode is located between the top of silicon chip, the adjacent rows silicon chip to be connected by middle gate line electrode.The photovoltaic cell and photovoltaic module set middle gate line electrode between adjacent rows silicon chip in gap, improve the surface area utilization rate of photovoltaic cell, and it is arranged on the middle gate line electrode in gap between adjacent rows silicon chip, reduce the consumption of electrode, the masked area of electrode pair silicon chip is reduced, the utilization rate of silicon chip, above-mentioned two measures is improved, the generating efficiency of solar energy photovoltaic panel can be effectively improved, and reduces production cost.
Description
Technical field
The utility model is related to field of photovoltaic technology, specially a kind of photovoltaic cell and photovoltaic module.
Background technology
With the extensive use of solar energy, solar energy photovoltaic panel industry also flourishes.
Traditional, solar panel is in production, due to the characteristic of battery chip architecture, be required to polylith cell piece and
Welding is welded into battery strings, then battery strings and other assembling components are integrated.
As shown in Figure of description Fig. 1, in current manufacturing process, two main gate lines are laid with every silicon chip 2 '
Electrode 3', main grid line electrode 3' cover silicon chip 2 ', the illuminating area of silicon chip 2 ' are reduced, so as to reduce effective electric surface
Product, reduces the generating efficiency of silicon chip 2 ';In addition, there is certain gap between adjacent rows silicon chip 2 ', the gap can not rise
To the effect of generating, the effective area on photovoltaic cell 1 ' is wasted, the volume of photovoltaic cell 1 ' is added.
Utility model content
The purpose of this utility model is to provide a kind of photovoltaic cell and photovoltaic module, to solve in above-mentioned background technology
Electrode on the photovoltaic cell of proposition covers silicon chip and influences generating efficiency, also, there is spacing between adjacent rows silicon chip,
The problem of adding the volume of photovoltaic battery panel.
To achieve the above object, the utility model provides following technical scheme:A kind of photovoltaic cell and photovoltaic module, bag
Include photovoltaic cell, silicon chip, main grid line electrode, secondary gate line electrode and middle gate line electrode, the photovoltaic cell include silicon chip,
Some secondary gate line electrodes, institute are evenly distributed with the top of main grid line electrode, secondary gate line electrode and middle gate line electrode, the silicon chip
State and be connected by main grid line electrode between multiple silicon chips, the main grid line electrode is located at the top of silicon chip, the adjacent rows
It is connected between silicon chip by middle gate line electrode.
It is preferred that, the main grid line electrode on the middle row silicon chip is located at the centre position of silicon chip.
It is preferred that, the main grid line electrode up and down on two row silicon chips located at silicon chip close to the side at edge, and main gate line
Electrode is by silicon chip with 1:2 ratio is separated.
It is preferred that, the width of the middle gate line electrode is more than the width of main grid line electrode.
Compared with prior art, the beneficial effects of the utility model are:The photovoltaic cell and photovoltaic module are adjacent two
Gate line electrode in the middle of being set between row silicon chip in gap, is effectively utilized gap between adjacent rows silicon chip, improves photovoltaic electric
The surface area utilization rate of pond piece, in equal area, photovoltaic power plant can put more photovoltaic battery panels, and be arranged on adjacent two
Middle gate line electrode between row silicon chip in gap, reduces the consumption of electrode, reduces the masked area of electrode pair silicon chip, carries
The high utilization rate of silicon chip, above-mentioned two measures can effectively improve the generating efficiency of solar energy photovoltaic panel, and reduce and be produced into
This.
Brief description of the drawings
Fig. 1 is the structural representation of photovoltaic cell in the prior art;
Fig. 2 is the utility model structural representation;
Fig. 3 is the utility model partial side structural representation.
In Fig. 1:1 ', photovoltaic cell, 2 ', silicon chip, 3 ', main grid line electrode.
In Fig. 2:1st, photovoltaic cell, 2, silicon chip, 3, main grid line electrode, 4, secondary gate line electrode, 5, middle gate line electrode.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belongs to the scope of the utility model protection.
Fig. 1-3 are referred to, the utility model provides a kind of technical scheme:A kind of photovoltaic cell and photovoltaic module, including
Photovoltaic cell 1, silicon chip 2, main grid line electrode 3, secondary gate line electrode 4 and middle gate line electrode 5, photovoltaic cell 1 include silicon chip
2nd, main grid line electrode 3, secondary gate line electrode 4 and middle gate line electrode 5, the top of silicon chip 2 are evenly distributed with some secondary gate line electrodes
4, it is connected by main grid line electrode 3 between multiple silicon chips 2, main grid line electrode 3 is located at the top of silicon chip 2, adjacent rows silicon chip 2
Between be connected by middle gate line electrode 5.
In above-described embodiment, specifically, the main grid line electrode 3 on middle row silicon chip 2 is located at the centre position of silicon chip 2,
Because the both sides of middle row silicon chip 2 are equipped with middle gate line electrode 5, the electric current that silicon chip 2 is produced can be simultaneously to the centre of both sides
Gate line electrode 5 and middle main grid line electrode 3 collect, therefore are in centre position one main grid line electrode 3 of setting of silicon chip 2 only
Can.
In above-described embodiment, specifically, the main grid line electrode 3 on two row silicon chips 2 is located at silicon chip 2 close to the one of edge up and down
Side, and main grid line electrode 3 by silicon chip 2 with 1:2 ratio is separated, and the electric current that the silicon chip 2 in the outside of main grid line electrode 3 is produced is to master
Gate line electrode 3 collects, and the electric current that main grid line electrode 3 is produced with the silicon chip 2 of inner side can be simultaneously to main grid line electrode 3 and middle grid line
Electrode 5 collects.
In above-described embodiment, specifically, the width of middle gate line electrode 5 is more than the width of main grid line electrode 3, in widening
Between gate line electrode 5 can bear bigger current load, the electrode of width section is covered between adjacent rows silicon chip 2.
Operation principle:When using the photovoltaic cell and photovoltaic module, need first to whole photovoltaic cell and photovoltaic
Component has in the understanding in a structure, the present embodiment, and the silicon chip 2 being arranged on photovoltaic cell 1 is preferably three rows, silicon chip 2
The electric current of generation is collected by secondary gate line electrode 4 to main grid line electrode 3 and middle gate line electrode 5, the master on middle row silicon chip 2
Gate line electrode 3 is located at the centre position of silicon chip 2, because the both sides of middle row silicon chip 2 are equipped with middle gate line electrode 5, silicon chip 2
The electric current of generation can collect to the middle gate line electrode 5 and middle main grid line electrode 3 of both sides simultaneously, therefore only in silicon chip 2
Centre position sets a main grid line electrode 3, and the main grid line electrode 3 on two row silicon chips 2 is located at silicon chip 2 close to edge up and down
Side, and main grid line electrode 3 by silicon chip 2 with 1:2 ratio is separated, the electric current of the generation of silicon chip 2 in the outside of main grid line electrode 3
Collect to main grid line electrode 3, the electric current that main grid line electrode 3 is produced with the silicon chip 2 of inner side can be simultaneously to main grid line electrode 3 and centre
Gate line electrode 5 collects, and the width of middle gate line electrode 5 is more than the width of main grid line electrode 3, and the middle gate line electrode 5 widened can
Bigger current load is born, the electrode of width section is covered between adjacent rows silicon chip 2, effectively utilize adjacent rows silicon chip
Gap between 2, improves the effective rate of utilization of photovoltaic cell 1.
In summary, general principle of the present utility model, principal character and advantage has been shown and described above.The industry
Technical staff it should be appreciated that the utility model is not restricted to the described embodiments, described in above-described embodiment and specification only
It is to illustrate principle of the present utility model, on the premise of the utility model spirit and scope are not departed from, the utility model also has
Various changes and modifications, these changes and improvements are both fallen within the range of claimed the utility model.The utility model requirement
Protection domain is defined by appending claims and its effect thing.
Claims (4)
1. a kind of photovoltaic cell and photovoltaic module, including photovoltaic cell (1), silicon chip (2), main grid line electrode (3), secondary grid line
Electrode (4) and middle gate line electrode (5), it is characterised in that:The photovoltaic cell (1) includes silicon chip (2), main grid line electrode
(3) some secondary gate line electrodes are evenly distributed with the top of, secondary gate line electrode (4) and middle gate line electrode (5), the silicon chip (2)
(4), it is connected between the multiple silicon chip (2) by main grid line electrode (3), the main grid line electrode (3) is located at silicon chip (2)
It is connected between top, the adjacent rows silicon chip (2) by middle gate line electrode (5).
2. a kind of photovoltaic cell according to claim 1 and photovoltaic module, it is characterised in that:The middle row silicon chip
(2) the main grid line electrode (3) on is located at the centre position of silicon chip (2).
3. a kind of photovoltaic cell according to claim 1 and photovoltaic module, it is characterised in that:The two row silicon chips up and down
(2) main grid line electrode (3) on located at silicon chip (2) close to the side at edge, and main grid line electrode (3) by silicon chip (2) with 1:2
Ratio is separated.
4. a kind of photovoltaic cell according to claim 1 and photovoltaic module, it is characterised in that:The middle gate line electrode
(5) width is more than the width of main grid line electrode (3).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201621474467.0U CN206332035U (en) | 2016-12-30 | 2016-12-30 | A kind of photovoltaic cell and photovoltaic module |
Applications Claiming Priority (1)
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CN201621474467.0U CN206332035U (en) | 2016-12-30 | 2016-12-30 | A kind of photovoltaic cell and photovoltaic module |
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CN206332035U true CN206332035U (en) | 2017-07-14 |
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CN201621474467.0U Expired - Fee Related CN206332035U (en) | 2016-12-30 | 2016-12-30 | A kind of photovoltaic cell and photovoltaic module |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107547040A (en) * | 2017-10-12 | 2018-01-05 | 福建省电力勘测设计院 | Solar photovoltaic cell panel with LED illumination lamp |
-
2016
- 2016-12-30 CN CN201621474467.0U patent/CN206332035U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107547040A (en) * | 2017-10-12 | 2018-01-05 | 福建省电力勘测设计院 | Solar photovoltaic cell panel with LED illumination lamp |
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GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170714 Termination date: 20171230 |
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CF01 | Termination of patent right due to non-payment of annual fee |