CN206251105U

CN206251105U - For the VCXO soft-lock phase devices of base station

Info

Publication number: CN206251105U
Application number: CN201621417346.2U
Authority: CN
Inventors: 王盼; 湛秀平; 霍幸
Original assignee: Wuhan Hongxin Telecommunication Technologies Co Ltd
Current assignee: CICT Mobile Communication Technology Co Ltd
Priority date: 2016-12-22
Filing date: 2016-12-22
Publication date: 2017-06-13
Anticipated expiration: 2026-12-22

Abstract

The utility model provides a kind of VCXO soft-lock phase devices for base station, and the VCXO is voltage controlled crystal oscillator, it is characterised in that：Including 1588 time servers, ethernet physical layer device, 1588 protocol analysis chips, CPU, FPGA, analog-digital converter and VCXO, 1588 time servers connect 1588 protocol analysis chips through ethernet physical layer device, 1588 protocol analysis chips connect CPU and FPGA respectively, FPGA connects the input of VCXO, the output end connection FPGA of VCXO through analog-digital converter.Cost of implementation of the present utility model is low, and volume requirement is small, and output accuracy is high, the miniaturization base station market demand is disclosure satisfy that, with important market value.

Description

For the VCXO soft-lock phase devices of base station

Technical field

The utility model is related to communication base station equipment field, and more specifically, the utility model is related in a kind of base station products Realize the device of VCXO soft-lock phases.

Background technology

It is usually used in common base station products because the required precision to time synchronized is very high in base station products OCXO (oven controlled crystal oscillator) thermostat control crystal oscillator is used as system clock Source.Because of it in high precision, with auto thermal compensation characteristic, price is costly for OCXO.General OCXO, according to the excellent of its performance Bad, price is between hundreds of to thousands of RMB.As the market demand of miniaturization base station is increasing, to the small of base station products Typeization and low cost propose requirement higher.How to become a key by the cost of technical scheme reduction OCXO to ask Topic.

Utility model content

The device of VCXO soft-lock phases is provided in a kind of base station products of the utility model offer, is supported using the same of 1588 outputs Step information calibrates VCXO, to provide accurately rate-adaptive pacemaker.

Technical solutions of the utility model provide a kind of VCXO soft-lock phase devices for base station, and the VCXO is voltage control Crystal oscillator, including 1588 time servers, ethernet physical layer device, 1588 protocol analysis chips, CPU, FPGA, modulus Converter and VCXO, 1588 time servers connect 1588 protocol analysis chips, 1588 agreement solutions through ethernet physical layer device Analysis chip connects the input that CPU and FPGA, FPGA connect VCXO through analog-digital converter, the output end connection of VCXO respectively FPGA。

And, 1588 time servers connect ethernet physical layer device, ethernet physical layer device by network interface 1588 protocol analysis chips are connected by SGMII interfaces.

And, 1588 temporal informations are sent to ethernet physical layer device by 1588 time servers by network interface, 1588 protocol analysis chips, the output of 1588 protocol analysis chips are sent to by SGMII interfaces by ethernet physical layer device again 1PPS signals are in FPGA.

And, CPU connects 1588 protocol analysis chips by SPI interface, and FPGA is connected by localbus buses.

And, FPGA connects analog-digital converter by SPI interface.

And, 1588 protocol analysis chips use ACS9521 chips.

And, analog-digital converter uses DAC8551 chips.

The utility model is on the basis of VCXO, there is provided the 1pps of 1588 outputs supports to count as clock source using FPGA The voltage-controlled end of evaluation time difference adjustment VCXO.Cost of implementation of the present utility model is low, and volume requirement is small, and output accuracy is high, Neng Gouman The foot miniaturization base station market demand, with important market value.

Brief description of the drawings

Fig. 1 is the structure chart of the utility model embodiment.

Fig. 2 is the fundamental diagram of the utility model embodiment.

Specific embodiment

The utility model is implemented below according to drawings and Examples is illustrated.

Referring to Fig. 1, the utility model provides the VCXO soft-lock phase devices for base station, including 1588 time servers, Ethernet physical layer device, 1588 protocol analysis chips, CPU, FPGA, analog-digital converter, VCXO, 1588 time servers pass through with Too net physical layer device connects 1588 protocol analysis chips, and 1588 protocol analysis chips connect CPU and FPGA, FPGA through mould respectively Number converter connects the input of VCXO, the output end connection FPGA of VCXO.

Further,

1588 time servers connect ethernet physical layer device by network interface, and ethernet physical layer device passes through SGMII interfaces connect 1588 protocol analysis chips；

VCXO is Voltage Control X-tal [Crystal] Oscillator, voltage controlled crystal oscillator.

For the sake of ease of implementation, there is provided the working method using the utility model institute offer device is as follows：

1. 1588 information are obtained from 1588 time servers by network, by the parsing of ACS9521 chips, output 1pps and TOD Time of Day information.Pulse per second (PPS) (1pps) signal that will be received is sent to FPGA.

2.FPGA (Field-Programmable Gate Array）That is field programmable gate array, using system clock 1pps is counted, analysis obtains the time difference, the voltage-controlled terminal voltage of VCXO is adjusted according to the time difference, realize the tune to frequency It is whole.

3. when the time difference certain limit is narrowed down to, you can assert that VCXO has been locked, output lock locking configured informations.

1588 temporal informations are sent to ethernet physical layer by 1588 time servers as clock source by network interface Device PHY, then ACS9521 chips are sent to by SGMII interfaces by ethernet PHY.ACS9521 after signal resolution to exporting 1PPS signals, and be sent in FPGA.SPI interface is left between CPU and ACS9521（Serial communication interface）, CPU can be with 1588 status information is inquired about by SPI interface.ACS9521 chips are a special chip for being used as 1588 protocol analysis, tool Body can also be using the chip of the agreement of parsing 1588 of other same types when implementing.

After CPU detects the locking of 1588 states, by localbus（A kind of lump communication bus interface）Bus writes FPGA Internal register, FPGA detected after register value changes, and starts the 19.2M system clocks exported with VCXO to 1pps Rising edge is counted.Between two 1pps signal rising edges, it should count 19.2M clock（Clock）, referring to Fig. 2.

If counting number less than 19.2M, illustrate that system clock cycle is bigger than normal, i.e., output frequency is less than standard frequency. If counting number more than 19.2M, illustrate that system clock cycle is less than normal, that is, frequency is more than standard frequency.According to VCXO handbooks, during standard frequency, the voltage-controlled terminal voltage values of VC are 1.65V, and voltage is tuned up, and frequency increase, voltage reduces, and frequency also subtracts It is small.

FPGA writes the register of analog-digital converter DAC8551 by spi bus, the analog voltage of DAC8551 outputs with The change of register value and change.FPGA is adjusted according to the deviation situation for counting number to the register value of DAC8551. Frequency after change is fed back in count difference again, forms a negative-feedback, and final result is exactly that output frequency will stabilise at mark In the deviation range of quasi- frequency or so very little, a kind of frequency relatively steady state is reached.DAC8551 chip interfaces are simple, essence Degree is higher, can also be replaced with high performance other chips of same type during specific implementation.

VCXO realizes that the system of frequency soft-lock phase is realized using 1588 calibrations.The specific reality that VCXO is adjusted by DAC8551 It is now prior art.

During specific implementation, FPGA and CPU can select specific chip model by those skilled in the art according to performance requirement, Power module can also be arranged as required to, be powered to each active device.The utility model only requires changing for protection hardware aspect Enter, each component working mode can be set by those skilled in the art according to prior art.

Above content is to combine specific embodiment further detailed description of the utility model, it is impossible to assert Specific implementation of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field For, without departing from the concept of the premise utility, some simple deduction or replace can also be made, should all be considered as category In protection domain of the present utility model.

Claims

1. a kind of VCXO soft-lock phase devices for base station, the VCXO is voltage controlled crystal oscillator, it is characterised in that：Bag 1588 time servers, ethernet physical layer device, 1588 protocol analysis chips, CPU, FPGA, analog-digital converter and VCXO are included, 1588 time servers connect 1588 protocol analysis chips through ethernet physical layer device, and 1588 protocol analysis chips are connected respectively CPU and FPGA, FPGA connect the input of VCXO, the output end connection FPGA of VCXO through analog-digital converter.

2. the VCXO soft-lock phase devices of base station are used for according to claim 1, it is characterised in that：1588 time servers pass through Network interface connects ethernet physical layer device, and ethernet physical layer device connects 1588 protocol analysis cores by SGMII interfaces Piece.

3. the VCXO soft-lock phase devices of base station are used for according to claim 2, it is characterised in that：1588 time servers pass through 1588 temporal informations are sent to ethernet physical layer device by network interface, then are connect by SGMII by ethernet physical layer device Mouth is sent to 1588 protocol analysis chips, in 1588 protocol analysis chips output 1PPS signals to FPGA.

4. the VCXO soft-lock phase devices of base station are used for according to claim 1 or 2 or 3, it is characterised in that：CPU is connect by SPI Mouth 1588 protocol analysis chips of connection, FPGA is connected by localbus buses.

5. the VCXO soft-lock phase devices of base station are used for according to claim 1 or 2 or 3, it is characterised in that：FPGA passes through SPI Interface connects analog-digital converter.

6. the VCXO soft-lock phase devices of base station are used for according to claim 1 or 2 or 3, it is characterised in that：1588 protocol analysis Chip uses ACS9521 chips.

7. the VCXO soft-lock phase devices of base station are used for according to claim 1 or 2 or 3, it is characterised in that：Analog-digital converter is adopted Use DAC8551 chips.