CN206209693U - A kind of multi-channel audio signal parallel acquisition device - Google Patents
A kind of multi-channel audio signal parallel acquisition device Download PDFInfo
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- CN206209693U CN206209693U CN201620973073.3U CN201620973073U CN206209693U CN 206209693 U CN206209693 U CN 206209693U CN 201620973073 U CN201620973073 U CN 201620973073U CN 206209693 U CN206209693 U CN 206209693U
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Abstract
A kind of multi-channel audio signal parallel acquisition device, including FPGA processing units, multiple audio decoder chips and processor, the multiple audio decoder chip are electrically connected to the FPGA processing units；The FPGA processing units are electrically connected with the audio decoder chip and the processor.Harvester of the present utility model greatly reduces the cost and power consumption of whole system compared to traditional integrated A/D chip solutions.
Description
Technical field
The utility model is related to field of speech recognition, further relates to a kind of multi channel signals parallel acquisition device.
Background technology
With speech recognition and the development of conversational system, intelligent sound interaction technique has caused increasing concern.
Interactive voice be unable to do without the collection to audio signal, and multi channel signals parallel acquisition is always signal transacting, is based particularly on battle array
The core technology of the field of signal processing of row.
Array Signal Processing is generally required to multiple sensors while be acquired, so as to using the phase between each road signal
Potential difference information, designs corresponding Array Signal Processing algorithm.In to the design process of this kind of acquisition system, often data channel
Many, data throughout is big, message transmission rate is fast, and requirement of real-time is high.
Typically complete to adopt using integrated multi-channel A/D chips currently for multi-channel audio signal parallel acquisition system
Collection, A/D chip interface sequential is controlled by dsp chip or arm processor.
However, there is following technological deficiency in prior art：
(1) the multi channel signals parallel acquisition system being directed to typically directly completes to adopt using integrated multi-channel A/D chips
Collection, in the market, such duplex high precision (such as 16,24) A/D chip is expensive, and power consumption is larger, is unfavorable for overall system
The cost control of system and low power dissipation design.
(2) conventional audio coding decoding chip (Codec chips) carries out the transmission of voice data, and branch using I2S interfaces
The time division multiplexing (TDM) of each interchannel is held, i.e., the data of multiple passages can be transmitted using single I2S interfaces.However, mesh
Although preceding processor conventional on the market is general also to have I2S interfaces, TDM mode is not supported, it means that for multichannel
, it is necessary to there is processor multichannel 12S interfaces to dock, this undoubtedly increases the type selecting difficulty and cost of processor to Codec；And should
Pattern increased the difficulty of data syn-chronization between each passage.
Utility model content
(1) technical problem to be solved
In view of this, the purpose of this utility model is to provide a kind of multi-channel audio signal parallel acquisition device, to solve
Certainly at least one technical problem in prior art described above.
(2) technical scheme
To achieve the above object, the utility model provides a kind of multi-channel audio signal parallel acquisition device, including
FPGA processing units, multiple audio decoder chips and processor, the multiple audio decoder chip are electrically connected to the FPGA
Processing unit, including register；The FPGA processing units are electrically connected with the audio decoder chip and the processor, FPGA
Processing unit includes I2S interfaces and I2C interfaces, and the I2S interfaces are electrically connected with the audio decoder chip；The I2C interfaces
The register is electrically connected with, the I2S is also electrically connected with the processor.
Preferably, the FPGA processing units include data fusion and re-encoding module.
Preferably, the FPGA processing units include I2S transmission rate adjustment units, and I2S transmission rates adjustment unit is used
I2S interfaces after the data separate after recompiling improves speed, are transferred to the processor.
Preferably, time division multiplexing, single I2S interfaces transmission are used between the I2S interfaces and audio decoder chip
The voice data of decoding chip multiple passage.
Preferably, the FPGA processing units include state monitoring module, the state monitoring module and the audio solution
Code chip is electrically connected with.
Preferably, the acquisition precision of the audio decoder chip is 16,24 or 32.
Preferably, ADC of the audio decoder chip comprising monolithic multi-channel parallel.
Preferably, the processor is ARM, MIPS, X86-based general-purpose chip, or USB/SDI bus marco chips.
(3) beneficial effect
By above-mentioned technical proposal, it can be seen that the beneficial effect of multi-channel audio signal parallel acquisition device of the present utility model
Fruit includes：
(1) compared to multi-channel A/D chips, Codec chip costs are much lower, and power consumption is lower, and with essence higher
Degree (conventional Codec can accomplish the precision of 24 substantially), is particularly suitable for some to cost and sensitive power consumption and to signal accuracy
It is required that multi-channel audio signal treatment product high；
(2) parallel acquisition of multi-channel audio signal is completed using multichannel Codec chips, compared to traditional integrated A/
D chip solutions, greatly reduce the cost and power consumption of whole system；
(3) voice data of multi-disc Codec chips is merged using FPGA, and utilization improves I2S interface rates
Mode, realizes the perfection docking with various types of processors I2S interfaces so that the acquisition scheme is applied to various types of processors, general
Property is strong；
(4) carry multi-disc Codec chips can be continued on FPGA, multichannel, high-precision Parallel ADC is neatly realized
Acquisition scheme, and set expandability is strong；The audio collecting system is especially suitable for that data channel is more, data throughout big, data are passed
Defeated speed is fast, and requirement of real-time audio signal sample demand high.
Brief description of the drawings
Fig. 1 is the circuit structure block diagram of the multi-channel audio signal parallel acquisition device of the utility model embodiment.
Fig. 2 is the operational flow diagram of the FPGA processing units of the utility model embodiment.
Specific embodiment
According to basic conception of the present utility model, there is provided a kind of multi-channel audio signal parallel acquisition device, including FPGA
Processing unit, multiple audio decoder chips and processor, wherein the multiple audio decoder chip is electrically connected to the FPGA
Processing unit, voice data is formed for gathering audio signal；The FPGA processing units are electrically connected with the audio decoder core
Piece and the processor, the FPGA processing units are used to receive the voice data of each audio decoder chip, that is, receive multichannel
Voice data, and the voice data is merged and recompiled, and improve with the transmission rate of the processor, will again
Data transfer after coding is to the processor.
Further, the FPGA processing units include I2S interfaces and I2C interfaces, and the I2S interfaces are electrically connected with described
Audio decoder chip, for the transmission of voice data；The audio decoder chip includes register, and the I2C interfaces electrically connect
The register is connect, for configuring the register；The I2S is also electrically connected with the processor.
Further, the FPGA processing units include data fusion and re-encoding module, for the multichannel
Voice data is merged and recompiled.
Further, the FPGA processing units include I2S transmission rate adjustment units, I2S transmission rate adjustment units
Data separate after for that will recompile improves the I2S interfaces after speed, is transferred to the processor.
Further, time division multiplexing, single I2S interfaces is used to pass between the I2S interfaces and audio decoder chip
The voice data of defeated decoding chip multiple passage.
Further, the FPGA processing units include state monitoring module, the state monitoring module and the audio
Decoding chip is electrically connected with, the working condition for monitoring the audio decoder chip.
Further, the processor can be Multiple Type processor, ARM, MIPS, X86-based general-purpose chip, or
The bus marco chip such as USB/SDI.
To make the purpose of this utility model, technical scheme and advantage become more apparent, below in conjunction with specific embodiment, and
Referring to the drawings, the utility model is described in further detail.Following saying to the utility model implementation method referring to the drawings
It is bright to be intended to explain overall utility model design of the present utility model, and be not construed as to one kind of the present utility model
Limitation.
The utility model is based on the multi-channel audio signal parallel acquisition system of FPGA and Codec, in FPGA (Field
Programmable Gate Array) carry multi-disc multichannel Codec chips on processing unit, using general defeated on FPGA
Enter/delivery outlet (I/O mouthfuls), software simulation I2S interfaces and its TDM mode realize receiving the voice data of each Codec chip；
Then the fusion and re-encoding of data are carried out inside FPGA；Then using the speed of the I2S interfaces for improving software simulation in FPGA
Rate, the voice data that will be recompiled sends processor to I2S transmission rates higher.
Such as, to 12 passages, sample rate for the audio signal of 16KHz is acquired, inside FPGA processing units
It is that (each frame I2S data include two channel numbers of left and right to 96KHz using transmission rate after 12 channel datas are merged and re-encoded
According to) I2S interfaces be transferred to processor.The circuit structure block diagram of system is as shown in Figure 1.
Codec chips in the system use the chip of the model pcm3168a of TI companies, the Codec chips to support single
The channel parallel ADC of piece 6, is 24 per passage precision；At most can be while 4 pcm3168a of carry on same bus.
FPGA processing units use the chip of the Spartan6 series of Xilinx companies, between FPGA and Codec chips
Hardware connection includes I2S interfaces, I2C interfaces and other status monitoring signals.Wherein I2S interfaces are used for the biography of voice data
Defeated, I2C interfaces are used to configure the register inside pcm3168a, and status monitoring signal is used for monitoring the work shape of pcm3168a
State.Connected by I2S interfaces between FPGA and ppu, for the voice data after fusion and re-encoding is transferred into place
Reason device.
3 partial function modules are broadly divided into inside FPGA processing units：
1) control and the reception of voice data to pcm3168a, the main I/O mouthfuls of software simulation I2C using FPGA are realized
Interface protocol and I2S interface protocols, complete the reception to the register configuration and voice data of pcm3168a.
2) data fusion and re-encoding module, the part achieve a butt joint each passage for receiving voice data fusion and
Re-encoding, the interspersed sequence, the addition of frame head postamble including passage etc..
3) I2S transmission rates adjusting module, the part is mainly realized the voice data after fusion, fast using transmission is improved
I2S interfaces after rate, are transferred to processor.
The software flow pattern of FPGA processing units is as shown in Figure 2：
The utility model embodiment is based on the multi-channel audio signal parallel acquisition system of FPGA and Codec, using scene
The powerful programming in logic function of programmable gate array (i.e. FPGA), the voice data to multi-disc Codec is merged, and utilization is carried
The mode of I2S interface rates high, processor is transferred to by the voice data after fusion, is met with the perfect right of various types of processors
Connect.
The sample rate of audio signal refer to collecting device in one second to the sampling number of voice signal, sample rate is higher
The reduction of sound is more true more natural.Conventional sampled audio signal rate is generally divided into 22.05KHz, 44.1KHz, 48KHz tri-
Individual grade, for some special applications, also has using 16KHz, 32KHz, 96KHz etc..Audio coding decoding chip (i.e. Codec)
Just it is specific to the dedicated IC chip of audio signal sample design.
Particular embodiments described above, has carried out entering one to the purpose of this utility model, technical scheme and beneficial effect
Step is described in detail, it should be understood that be the foregoing is only specific embodiment of the utility model, is not limited to this reality
With new, all within spirit of the present utility model and principle, any modification, equivalent substitution and improvements done etc. all should be included
Within protection domain of the present utility model.
Claims (7)
1. a kind of multi-channel audio signal parallel acquisition device, including FPGA processing units, multiple audio decoder chips and treatment
Device, it is characterised in that：
The multiple audio decoder chip is electrically connected to the FPGA processing units, including register；
The FPGA processing units are electrically connected with the audio decoder chip and the processor, and FPGA processing units include I2S
Interface and I2C interfaces, the I2S interfaces are electrically connected with the audio decoder chip；The I2C interfaces are electrically connected with the deposit
Device, the I2S is also electrically connected with the processor；
Wherein, the FPGA processing units include I2S transmission rate adjustment units, and I2S transmission rates adjustment unit is used for will weight
Data separate after newly encoded improves the I2S interfaces after speed, is transferred to the processor.
2. multi-channel audio signal parallel acquisition device according to claim 1, it is characterised in that the FPGA treatment is single
Unit includes data fusion and re-encoding module.
3. multi-channel audio signal parallel acquisition device according to claim 1, it is characterised in that the I2S interfaces and
Time division multiplexing, the voice data of single I2S interfaces transmission decoding chip multiple passage are used between audio decoder chip.
4. multi-channel audio signal parallel acquisition device according to claim 1, it is characterised in that the FPGA treatment is single
Unit includes state monitoring module, and the state monitoring module is electrically connected with the audio decoder chip.
5. multi-channel audio signal parallel acquisition device according to claim 1, it is characterised in that the audio decoder core
The acquisition precision of piece is 16,24 or 32.
6. multi-channel audio signal parallel acquisition device according to claim 1, it is characterised in that the audio decoder core
ADC of the piece comprising monolithic multi-channel parallel.
7. multi-channel audio signal parallel acquisition device according to claim 1, it is characterised in that the processor is
ARM, MIPS, X86-based general-purpose chip, or USB/SDI bus marco chips.
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| CN201620973073.3U CN206209693U (en) | 2016-08-29 | 2016-08-29 | A kind of multi-channel audio signal parallel acquisition device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111596704A (en) * | 2020-05-25 | 2020-08-28 | 中船动力研究院有限公司 | Temperature signal processing circuit and automatic controller |
| CN113961167A (en) * | 2021-10-28 | 2022-01-21 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Multi-channel audio data processing method and device |
-
2016
- 2016-08-29 CN CN201620973073.3U patent/CN206209693U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111596704A (en) * | 2020-05-25 | 2020-08-28 | 中船动力研究院有限公司 | Temperature signal processing circuit and automatic controller |
| CN113961167A (en) * | 2021-10-28 | 2022-01-21 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Multi-channel audio data processing method and device |
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