CN206194741U - Two -way ultralow electric capacity transient voltage inhibitor - Google Patents
Two -way ultralow electric capacity transient voltage inhibitor Download PDFInfo
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- CN206194741U CN206194741U CN201621031771.8U CN201621031771U CN206194741U CN 206194741 U CN206194741 U CN 206194741U CN 201621031771 U CN201621031771 U CN 201621031771U CN 206194741 U CN206194741 U CN 206194741U
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- epitaxial layer
- transient voltage
- doped region
- groove
- voltage suppressor
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Abstract
The utility model relates to a two -way ultralow electric capacity transient voltage inhibitor, include: a conductivity type's semiconductor substrate, the 2nd conductivity type's first epitaxial layer, a conductivity type's third epitaxial layer, the 2nd conductivity type's of formation first buried layer between first epitaxial layer and third epitaxial layer, relative the 2nd conductivity type's who forms with first buried layer first doped region in the third epitaxial layer, compared with the prior art, first slot, wherein first slot is in third epitaxial layer surface extends to semiconductor substrate, the second slot, wherein the second slot passes the third epitaxial layer from the surface extension of third epitaxial layer, the first insulation medium is filled in first slot and second slot, the third slot, the third slot is in first buried layer to first epitaxial layer is passed in the surface extension of third epitaxial layer, the active area, its normal position polycrystalline silicon and annealing by filling in the third slot forms.
Description
Technical field
The utility model is related to semiconductor microelectronic technology field, and specifically, the utility model is related to a kind of two-way super
Low capacitor transient stage voltage suppressor.
Background technology
Transient Voltage Suppressor TVS (Transient Voltage Suppressor) is developed on the basis of voltage-stabiliser tube
High-effect circuit brake.The profile of TVS diode is as good as with common voltage-stabiliser tube, however, due to special structure and technique
Design, the transient response speed and surge absoption ability of TVS diode are far above common voltage-stabiliser tube.For example, the sound of TVS diode
It is only 10 between seasonable-12Second, and up to thousands of watts of surge power can be absorbed.Under the conditions of applied in reverse, when bearing one
During the big pulse of high-energy, the working impedance of TVS diode can quickly be down to extremely low conduction value, so as to allow high current to lead to
Cross, meanwhile, by voltage clamp in predeterminated level.Therefore, TVS diode can effectively protect the precision unit device in electronic circuit
Damage of the part from various surge pulses.
Relative to unidirectional TVS device, two-way TVS device is due to the classical electrical I-V curve base with positive and negative both direction
This symmetrical feature so that in actual applications, can protection circuit simultaneously both direction, so range of application is wider.
The market of consumer electronics is developed rapidly, and the electronic product performance with mobile phone and mobile terminal as representative is constantly carried
Rise, mobile phone or mobile terminal etc. all have higher requirements to reaction speed, transmission speed, and the ultra-low capacitance less than 1pF is that TVS must expire
The rigid index of foot.
Therefore the two-way TVS for combining low capacitor design will be with very big market prospect.
The two-way TVS of prior art, generally longitudinal NPN or positive-negative-positive structure are constituted, as shown in Figure 1, it is possible to achieve larger
Power and preferable voltage symmetry, and with low cost, process is simple.But this structure cannot realize low electric capacity.
Another scheme is using such as entitled " a kind of low capacitor transient stage voltage suppressor device and preparation method "
The technology of Chinese patent application 201410841443.3, the technology is one-way low-capacitance TVS, want to realize it is two-way must be by two groups of separation
, the duplicate one-way low-capacitance TVS device of performance connects according to Fig. 2 modes.Because power supply and ground two ends are full symmetric, can
To realize two-way ultra-low capacitance performance.
But this structure has the following disadvantages：
1st, two groups of chip Series Package is needed, it is relatively costly；
2nd, for less packaging body, two groups of chip cannot be encapsulated simultaneously.
Another scheme is two-way one-way low-capacitance, directly by one-way low-capacitance TVS device for two passages
Tunnel ends are drawn, as shown in figure 3, because two tunnel ends are full symmetric, it is possible to achieve two-way ultra-low capacitance performance.
But this structure has the following disadvantages：
1st, two tunnel ends must draw from front simultaneously, so as to cause chip area larger, be not suitable for less encapsulation
Body；
Two tunnel ends each must make a call to a wires when the 2nd, encapsulating, relatively costly.
Yet another approach is that encapsulation is integrated, and integrated mode reality is encapsulated with many independent PIN diodes and general T VS pipes
Existing bidirectional low-capacitance, as shown in Figure 4.
This structure has the following disadvantages：
1st, 2 chips are placed on each Ji Dao, so as to cause the probability for encapsulating defect to uprise, increased Die
The cost of bonding；
Two passages each must make a call to a wires when the 2nd, encapsulating, relatively costly；
3rd, the bigger space of the integration packaging requirement of multiple chips, increased overall dimensions, be not suitable for less packaging body.
It can be seen that, it is still desirable to a kind of two-way ultra-low capacitance TVS and its manufacture method come overcome in above-mentioned deficiency at least it
One.
Utility model content
The utility model will solve at least one above-mentioned technical problem, and single-chip integration is utilized the utility model discloses one kind
The two-way device of surge protector of ultra-low capacitance that technique makes, the technical solution adopted in the utility model is as follows：
On the one hand the utility model provides a kind of two-way ultra-low capacitance Transient Voltage Suppressor (TVS), including：
The Semiconductor substrate of the first conduction type；
First epitaxial layer of the second conduction type for being formed over the substrate；
3rd epitaxial layer of the first conduction type for being formed on the first epitaxial layer；
First buried regions of the second conduction type formed between the first epitaxial layer and the 3rd epitaxial layer；
The first doped region of the second conduction type of formation relative with the first buried regions in the 3rd epitaxial layer；
Second doped region of the first conduction type formed in the 3rd epitaxial layer, wherein the second doped region and the first buried regions
It is not relative；
First groove, wherein the first groove is extended in Semiconductor substrate from the 3rd epi-layer surface, and it is described
First epitaxial layer, the 3rd epitaxial layer are defined to the first island by first groove jointly；
Second groove, wherein the second groove extends through the 3rd epitaxial layer from the 3rd epi-layer surface, and by
A part for three epitaxial layers is defined to the second island, and the first buried regions is outside the second island；
First dielectric, is filled in first groove and second groove；
3rd groove, the 3rd groove is extended through in the first buried regions to the first epitaxial layer from the 3rd epi-layer surface；
Active area, it is formed by the in-situ polycrystalline silicon filled in the 3rd groove and after annealing；
Wherein the first epitaxial layer and active area respectively as the first TVS pipe anode and negative electrode, the first epitaxial layer and substrate
Respectively as the anode and negative electrode of the second TVS pipe, the anode of the first doped region and the first buried regions respectively as upper commutation diode
And negative electrode, the second doped region as lower commutation diode negative electrode, lower commutation diode and first, second TVS pipe common anode；
And wherein the first conduction type is opposite with the second conduction type.
In one alternate embodiment, TVS also includes
In the fairlead that active area, the first doped region, the corresponding position of the second doped region are formed；
In the interconnection line (14) that the position of fairlead is formed, wherein the negative electrode of the anode of upper rectifying tube and lower rectifying tube passes through
Interconnection line is connected, and forms an exit of two-way TVS；
The metal layer (1) formed to substrate back, as another exit of two-way TVS pipe.
In one alternate embodiment, the resistivity of the first epitaxial layer is not more than 0.02 Ω cm, and thickness is not less than 6 μm.
In one alternate embodiment, the resistivity of the 3rd epitaxial layer is more than 5.5 Ω cm, 5.5 μm of thickness G T.GT.GT.
In one alternate embodiment, the first doped region is that ion implantation dosage is more than E14cm-2The second of the order of magnitude is conductive
The doped region formed after type dopant and annealing.
In one alternate embodiment, the second doped region is that concentration is not less than E19cm-3First conduction type of the order of magnitude is miscellaneous
The doped region that matter is formed.
In one alternate embodiment, the Semiconductor substrate is Si of the resistivity less than 0.02 Ω cm.
In one alternate embodiment, first conduction type is N-type, and the second conduction type is p-type；Or
First conduction type is p-type, and the second conduction type is N-type.
The beneficial effects of the utility model：
By the technical solution of the utility model, the two-way ultra-low capacitance TVS of Single-Chip Integration can be realized.In addition, phase
The various prior arts more listed than in background technology, additional technique effect also includes saving bonding die and spun gold, low packaging cost,
Meet application demand of the market to such product.
3rd trench fill poly-silicon annealing forms the mode of doped region, increased the sectional area of active area, there is provided TVS
The power of pipe, reduces bulk resistor.Trench isolations instead of PN junction isolation, reduce ghost effect, improve the performance of device.
Brief description of the drawings
Fig. 1 shows the structural representation of the two-way TVS of prior art.
Fig. 2 shows the equivalent circuit of the two-way ultra-low capacitance TVS being in series using the one-way low-capacitance TVS of prior art
Figure.
Fig. 3 show the two-way ultra-low capacitance TVS being formed by connecting using the one-way low-capacitance TVS binary channels of prior art etc.
Effect circuit diagram.
Fig. 4 shows to encapsulate the two-way low electricity that integrated mode is realized using many independent PIN diodes and general T VS pipes
The equivalent circuit diagram of appearance.
Fig. 5 shows the equivalent circuit diagram of two-way ultra-low capacitance TVS of the present utility model.
Fig. 6-18 shows the corresponding device profile map of making each steps of TVS of the present utility model.
Reference numerals list
1 metal layer
2 Semiconductor substrates
3 first epitaxial layers
4 second epitaxial layers (sacrifice layer)
5 the 3rd epitaxial layers
6 first groove areas
7 the 3rd trench areas
8 active areas
9 second groove areas
10 first buried districts
11 first doped regions
12 second doped regions
13 dielectrics
14 interconnection lines
Specific embodiment
In order to illustrate more clearly of the utility model, the utility model is done into one with reference to preferred embodiments and drawings
The detailed description of step.Identical part is represented with identical mark in accompanying drawing.It will be appreciated by those skilled in the art that being had below
The content of body description is illustrative and be not restrictive, and should not limit protection domain of the present utility model with this.
As shown in figure 5, two-way ultra-low capacitance TVS of the present utility model includes the first TVS pipe 15, it is the second TVS pipe 16, upper whole
Stream diode 17 and lower commutation diode 18.Wherein, the negative electrode of the first TVS pipe 15 is connected with the negative electrode of upper commutation diode 17
Connect, the TVS pipe 15 of lower commutation diode 18 and first and the pipe common anodes of the 2nd TVS 16, the anode of upper commutation diode 17 is with
The negative electrode of commutation diode 18 is connected, used as an exit of two-way TVS of the present utility model, the negative electrode of the second TVS pipe 16
As another exit of two-way TVS.
Fig. 6-18 shows the Making programme of the two-way device of surge protector of ultra-low capacitance of the present utility model.
As shown in Figure 6, there is provided N-type semiconductor substrate 2.
In one example, the Semiconductor substrate is heavily doped N-type substrate of the resistivity less than 0.02 Ω cm.Should be partly
The material of conductor substrate is, for example, Si.
As shown in fig. 7, forming the first epitaxial layer of p-type 3 in the N-type substrate 2.The formation of the first epitaxial layer 3 can be with profit
Realized with growth technology well known to those skilled in the art, for example MOCVD.
In one example, the resistivity of the first epitaxial layer of the p-type 3 is not more than 0.02 Ω cm, and thickness is not less than 6 μm
Heavily doped P-type epitaxial layer.
As shown in figure 8, forming the second epitaxial layer 4 on first epitaxial layer 3.Second epitaxial layer is used as successive process
In sacrifice layer, the high temperature process that this layer is postponed a meeting or conference outward in then continuous processing procedure gradually expands by the first epitaxial layer is counter.What is be finally completed
In device, the Rotating fields disappear.
In one example, the second epitaxial layer 4 is that resistivity is more than 0.2 Ω cm, the p-type that 2 μm of thickness G T.GT.GT or is hindered in N-type
Epitaxial buffer layer.
As shown in figure 9, forming the first buried regions 10 of the second conduction type, first buried regions 10 is from the table of the second epitaxial layer 4
Face is extended to inside it.
In one example, E15cm is injected to the second epitaxial layer 4 using ion implantation technology-2The antimony of the order of magnitude, 1150 DEG C
It is annealed above, so as to form first buried regions 10.
As shown in Figure 10, the epitaxial layer 5 of N-type the 3rd is formed.
In one example, epitaxial growth resistivity is more than 5.5 Ω cm, the N-type high resistant extension of 5.5 μm of thickness G T.GT.GT.
As shown in figure 11, the first doped region of formation p-type 11 relative with the first buried regions 10 in the 3rd epitaxial layer, as upper
The anode of rectifying tube.
In one example, ion implanting is more than E14cm-2The boron of the order of magnitude, 1000 DEG C annealed above described so as to be formed
First doped region 11.
As shown in figure 12, the second doped region of N-type 12 is formed in the 3rd epitaxial layer, as the negative electrode of lower rectifying tube.Wherein
Second doped region 12 is not relative with the first buried regions 10.It is mentioned here not relative, refer in figure on vertical direction second and mix
The projection in miscellaneous area is not overlap with the first buried regions 10.
In one example, thermal diffusion doping concentration is not less than E19cm-3The phosphorus of the order of magnitude and form the second doped region 12.
As shown in figure 13, first groove 6 is formed, the first groove extends to semiconductor lining from the surface of the 3rd epitaxial layer 5
In bottom 2.First epitaxial layer 3, the second epitaxial layer 4, the 3rd epitaxial layer 5 are defined to the first island by the first groove jointly.
As shown in figure 14, second groove 9 is formed, the second groove is extended through outside the 3rd from the surface of the 3rd epitaxial layer 5
Prolong layer.3rd epitaxial layer 5 is divided into multiple isolated islands by the second groove.Second groove is by a part for the 3rd epitaxial layer 5
The second island is defined to, the first buried regions 10 is outside the second island.
Dielectric is filled in first groove 6 and second groove 9.
As shown in figure 15, the 3rd groove 7 is formed, the 3rd groove extends through the first buried regions from the 3rd epi-layer surface
In 10 to the first epitaxial layers 3.
In-situ polycrystalline silicon is filled in the 3rd groove 7, and carries out annealing and form active area 8, as the negative electrode of a TVS.
3rd trench fill in-situ polycrystalline annealed silicon forms the mode of active area, increased the sectional area of active area, there is provided
The power of TVS pipe, reduces bulk resistor.Trench isolations instead of PN junction isolation, reduce ghost effect, improve device
Performance.
As shown in figure 16, fairlead is formed in active area 8, the first doped region 11, the corresponding position of the second doped region 12.
In one example, by deposit dielectric 13 such as silica or silicon nitride and by etching dielectric and
Form fairlead.
As shown in figure 17, metal line 14 is formed in the position of fairlead, each functional areas is drawn, form interconnection structure.
The negative electrode of the negative electrode of the first TVS pipe and upper rectifying tube is connected by front side interconnection line 14.The anode of upper rectifying tube and
The negative electrode of lower rectifying tube is connected by a part of interconnection line, forms an exit of two-way TVS.
As shown in figure 18, substrate 2 is carried out thinning and forms metal layer 1 at its back side, as the another of two-way TVS pipe
Individual exit.
Note that the conduction type of each layer in above-described embodiment can unify to be changed into opposite type, it is also possible to realize
Two-way ultra-low capacitance TVS of the present utility model.
It should be noted that here, heavy doping and to be lightly doped be relative concept represents that the doping concentration of heavy doping is more than
The doping concentration being lightly doped, and not to the restriction of specific doping concentration scope.
Obviously, above-described embodiment of the present utility model is only intended to clearly illustrate the utility model example, and
It is not the restriction to implementation method of the present utility model, for those of ordinary skill in the field, in described above
On the basis of can also make other changes in different forms, all of implementation method cannot be exhaustive here,
It is every to belong to the obvious change or change still in of the present utility model that the technical solution of the utility model extends out
The row of protection domain.
Claims (8)
1. a kind of two-way ultra-low capacitance Transient Voltage Suppressor, it is characterised in that including：
The Semiconductor substrate (2) of the first conduction type；
First epitaxial layer (3) of the second conduction type for being formed over the substrate；
3rd epitaxial layer (5) of the first conduction type for being formed on the first epitaxial layer；
First buried regions (10) of the second conduction type formed between the first epitaxial layer and the 3rd epitaxial layer；
First doped region (11) of the second conduction type of formation relative with the first buried regions in the 3rd epitaxial layer；
Second doped region (12) of the first conduction type formed in the 3rd epitaxial layer, wherein the second doped region and the first buried regions
It is not relative；
First groove (6), wherein the first groove is extended in Semiconductor substrate from the 3rd epi-layer surface, and described
First epitaxial layer, the 3rd epitaxial layer are defined to the first island by one groove jointly；
Second groove (9), wherein the second groove extends through the 3rd epitaxial layer from the 3rd epi-layer surface, and by the 3rd
A part for epitaxial layer is defined to the second island, and the first buried regions is outside the second island；
First dielectric, is filled in first groove and second groove；
3rd groove (7), the 3rd groove is extended through in the first buried regions to the first epitaxial layer from the 3rd epi-layer surface；
Active area (8), it is formed by the in-situ polycrystalline silicon filled in the 3rd groove and after annealing；
Wherein the first epitaxial layer (3) and active area (8) respectively as the first Transient Voltage Suppressor pipe anode and negative electrode, first
Epitaxial layer (3) and substrate (2) respectively as the second Transient Voltage Suppressor pipe anode and negative electrode, the first doped region (11) and
One buried regions (10) respectively as upper commutation diode anode and negative electrode, the second doped region (12) as lower commutation diode the moon
Pole, lower commutation diode and first, second Transient Voltage Suppressor pipe common anode；
And wherein the first conduction type is opposite with the second conduction type.
2. Transient Voltage Suppressor according to claim 1, it is characterised in that also include
In the fairlead that active area, the first doped region, the corresponding position of the second doped region are formed；
In the interconnection line (14) that the position of fairlead is formed, wherein the negative electrode of the anode of upper rectifying tube and lower rectifying tube is by interconnection
Line is connected, and forms an exit of bidirectional transient voltage suppressor；
The metal layer (1) formed to substrate back, as another exit of bidirectional transient voltage suppressor pipe.
3. Transient Voltage Suppressor according to claim 1, it is characterised in that
The resistivity of the first epitaxial layer is not more than 0.02 Ω cm, and thickness is not less than 6 μm.
4. Transient Voltage Suppressor according to claim 1, it is characterised in that
The resistivity of the 3rd epitaxial layer is more than 5.5 Ω cm, 5.5 μm of thickness G T.GT.GT.
5. Transient Voltage Suppressor according to claim 1, it is characterised in that
First doped region is that ion implantation dosage is more than E14cm-2Formed after second conductive type impurity of the order of magnitude and annealing
Doped region.
6. Transient Voltage Suppressor according to claim 1, it is characterised in that
Second doped region is that concentration is not less than E19cm-3The doped region that first conductive type impurity of the order of magnitude is formed.
7. Transient Voltage Suppressor according to claim 1, it is characterised in that
The Semiconductor substrate is Si of the resistivity less than 0.02 Ω cm.
8. the Transient Voltage Suppressor as any one of claim 1-7, it is characterised in that first conduction type is
N-type, the second conduction type is p-type；Or
First conduction type is p-type, and the second conduction type is N-type.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201621031771.8U CN206194741U (en) | 2016-08-31 | 2016-08-31 | Two -way ultralow electric capacity transient voltage inhibitor |
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| CN201621031771.8U CN206194741U (en) | 2016-08-31 | 2016-08-31 | Two -way ultralow electric capacity transient voltage inhibitor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158851A (en) * | 2016-08-31 | 2016-11-23 | 北京燕东微电子有限公司 | A kind of two-way ultra-low capacitance Transient Voltage Suppressor and preparation method thereof |
-
2016
- 2016-08-31 CN CN201621031771.8U patent/CN206194741U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158851A (en) * | 2016-08-31 | 2016-11-23 | 北京燕东微电子有限公司 | A kind of two-way ultra-low capacitance Transient Voltage Suppressor and preparation method thereof |
| CN106158851B (en) * | 2016-08-31 | 2022-11-11 | 北京燕东微电子有限公司 | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof |
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