CN206178094U - Chip testing preliminary adjustment circuit - Google Patents
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- CN206178094U CN206178094U CN201621112410.6U CN201621112410U CN206178094U CN 206178094 U CN206178094 U CN 206178094U CN 201621112410 U CN201621112410 U CN 201621112410U CN 206178094 U CN206178094 U CN 206178094U
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Abstract
Chip testing preliminary adjustment circuit includes: the state machine circuit for control chip gets into the test mode and reaches adjustment mode in advance, and withdraws from adjustment mode in advance after the preliminary adjustment is accomplished to the chip, the preliminary adjustment signal produces the circuit for produce corresponding preliminary adjustment control signal according to the outside instruction, the preliminary adjustment circuit for through the resistance capacitance value of matcing different preliminary adjustment control signal adjustment chip, with clock and the reference voltage value who changes the chip. The utility model discloses a chip testing preliminary adjustment circuit has fast and stable, reliable, characteristics that the area is little to the test degree of difficulty and test cost can be reduced, quick reliable test on the basis that chip area does not increase has been realized.
Description
Technical field
This utility model belongs to electronic circuit technology field, more particularly, it relates to a kind of chip testing pre-adjusting circuit.
Background technology
With the development of integrated circuit, the demand of chip volume production test is more and more, particularly high-precision to chip to want
Ask so that chip test when need to trim circuit, make the key indexs such as clock, the reference voltage of chip more accurate.Such as
What chip can be carried out quick pre-adjustment and fuse programming can accurately be finished complete to test be in the industry be badly in need of solve
One of problem.
Utility model content
The purpose of this utility model is to provide a kind of circuit that can carry out test pre-adjustment to chip with fast and reliable.
To achieve these goals, this utility model takes following technical solution：
Chip testing pre-adjusting circuit, including：State machine circuit, for control chip test pattern and presetting mould preparation are entered
Formula, and complete the presetting integral pattern of pre-adjustment backed off after random in chip；Pre-adjustment signal generating circuit, for being produced according to external command
Corresponding pre-adjustment control signal；Pre-adjusting circuit, for adjusting chip internal by the different pre-adjustment control signal of matching
Resistance capacitance value, to change the clock and reference voltage value of chip.
More specifically, the state machine circuit includes that the N levels being sequentially connected select electronic circuit, and per grade selects electronic circuit to include
One data signal MUX, a clock signal MUX and a trigger, data signal MUX
And the selection signal end of clock signal MUX is connected with the test mode signal end of external test machine；1st grade selects son
The first input end of the data signal MUX of circuit is connected with the second outfan of the first trigger, the second input with
Outside command signal input connects, outfan is connected with the data input pin of the first trigger, and the 1st grade selects electronic circuit
The first input end of clock signal MUX is connected with the clock signal port of external counter, the second input with it is outside
The clock of the connection of test clock signal port, the clock port of outfan and the first trigger and the 2nd grade of selection electronic circuit believe
The second input connection of number selector, first outfan and the second outfan of trigger respectively with the 2nd grade of selection electronic circuit
In data signal MUX the second input and clock signal MUX first input end connection；N-th grade
The first input end of data signal MUX for selecting electronic circuit is connected with the second outfan of the n-th trigger, second defeated
Enter end be connected with the first outfan of the trigger of upper level selection electronic circuit, the data input pin of outfan and the n-th trigger
Connection, first input end and the upper level of the clock signal MUX of n-th grade of selection electronic circuit select the triggering of electronic circuit
The outfan of the clock signal MUX of the connection of the second outfan, the second input and upper level selection electronic circuit of device connects
Connect, outfan is connected with the clock port of the n-th trigger, first outfan and the second outfan of trigger respectively with next stage
Second input and the first input end of clock signal MUX of the data signal MUX in selection electronic circuit
Connection, wherein, n=2,3 ..., N.
More specifically, the pre-adjustment signal generating circuit includes decoding unit and data storage circuitry, wherein, decoding is single
Unit includes K level decoding circuits, and per one-level decoding circuit by constituting with door, data storage circuitry includes data storage MUX
With data storage flip-flop；Each of 1st grade of decoding circuit and each input of door successively with touch in selection electronic circuits at different levels
The outfan connection of device is sent out, in every grade of decoding circuit one and the one of door in each outfan and next stage decoding circuit with door
Individual input connection, afterbody decoding circuit has one and door, should deposit with data in data storage circuitry with the outfan of door
The selection signal end connection of storage MUX；The first input end of data storage MUX and data storage flip-flop
Second outfan of the connection of the first outfan, the second input and data storage flip-flop connects, outfan and data storage are touched
Send out the data input pin connection of device, the clock port of data storage trigger is connected with outside test clock signal port, defeated
Go out end to be connected with pre-adjusting circuit by MUX selectores.
More specifically, the pre-adjusting circuit includes decoder and 2N NMOS tube, the input and data of decoder
Pre-adjustment signal generating circuit connects, and each outfan of decoder is connected respectively with the grid of a NMOS tube, each NMOS tube
Drain electrode be sequentially connected, the source electrode of each NMOS tube is connected with a VREF resistance in chip reference voltage module.
More specifically, the MUX selects 1 MUX for 2.
More can be specific, the decoder is 4-16 decoders.
More specifically, the state machine circuit includes 8 grades of selection electronic circuits.
More specifically, the decoding unit include 3 grades of decoding circuits, first with door, second with door, the 5th with door, the 6th
With 1 grade of decoding circuit of Men Wei, the 3rd with door, the 7th with 2 grades of decoding circuits of Men Wei, the 4th with door be 3rd level decoding circuit；
Each in 1st grade of decoding circuit selects the outfan of trigger in electronic circuit to be connected with the input of door with one-level, often
Level decoding circuit in be connected with the input of door with next stage decoding circuit with the outfan of door, in 3rd level decoding circuit and
The outfan of door is connected with data storage circuitry.
From above technical scheme, test pre-adjusting circuit of the present utility model can be realized being write by external test machine
Instruction constantly adjusts the value of the corresponding reference voltage of change and master clock, so as to carry out the pre-adjustment of scorification filament test, tool
The characteristics of having fast and stable, reliability, little area, and difficulty of test and testing cost can be reduced, while chip multiplexing port is entered
Test pattern, realizes the test of the fast and reliable on the basis of chip area does not increase.
Description of the drawings
In order to be illustrated more clearly that this utility model embodiment, below will be to wanting needed for embodiment or description of the prior art
The accompanying drawing for using does simple introduction, it should be apparent that, drawings in the following description are only some embodiments of the present utility model,
For those of ordinary skill in the art, on the premise of not paying creative work, can be with according to these accompanying drawings acquisitions
Other accompanying drawings.
Fig. 1 is the block diagram of this utility model embodiment；
Fig. 2 is the schematic diagram of this utility model embodiment state machine circuit；
Fig. 3 is the schematic diagram of this utility model embodiment pre-adjustment signal generating circuit；
Fig. 4 is the schematic diagram of this utility model embodiment pre-adjusting circuit.
Specific embodiment
As shown in figure 1, chip testing pre-adjusting circuit of the present utility model includes that state machine circuit, presetting entire signal are produced
Circuit and pre-adjusting circuit.Wherein, state machine circuit is used for control chip into test pattern and presetting integral pattern, and in chip
Complete the presetting integral pattern of pre-adjustment backed off after random.Pre-adjustment signal generating circuit, it is corresponding presetting for being produced according to external command
Whole control signal.Pre-adjusting circuit adjusts the resistance capacitance value of chip internal by the different pre-adjustment control signal of matching, makes
Obtain chip internal resistance capacitance annexation to change, so as to change the clock and reference voltage value of chip, and by pre-reading judgement
Whether the value of testing and debugging meets design requirement, and determines adjusted value.
State machine circuit is the state control circuit of pre-adjusting circuit, when chip normal work, pre-adjusting circuit
Do not work, pre-adjustment could be carried out to chip when chip is into test pattern.State machine circuit selects electronic circuit structure by N levels
Into N is integer, and the value of N is related to the bit wide of instruction, and 8 bit instructions, the N=8 of the present embodiment are adopted industry more.Per grade of selection
Electronic circuit includes two MUX and a trigger, and the two MUX one are data signal multi-path choice
Device, one is clock signal MUX, and selection electronic circuits at different levels are sequentially connected.The state machine circuit of the present embodiment includes 8
Level selects electronic circuit, MUX to select 1 MUX using 2.In addition to the 1st grade of structure slightly difference for selecting electronic circuit,
The structure all same of remaining per grade selection electronic circuit, be with the structure of the 1st grade of selection electronic circuit and the 2nd grade of selection electronic circuit below
Example is illustrated to state machine circuit.As shown in figure 1, the 1st grade select electronic circuit include the first data signal MUX u1,
First clock signal MUX u2 and the first trigger d1, the 2nd grade selects electronic circuit to select including the second data signal multichannel
Device u3, the 3rd clock signal MUX u4 and the second trigger d2 are selected, the first order selects the data signal multichannel of electronic circuit
Selector and clock signal MUX are one-level MUX, and the second level selects the data signal multi-path choice of electronic circuit
Device and clock signal MUX are two grades of MUX, by that analogy.
The second outfan QN of the first input end I1 of the first data signal MUX u1 and the first trigger d1 connects
Connect, the second input I2 of the first data signal MUX u1 is connected with the command signal input MR of outside, the first number
It is believed that the outfan Z of number MUX u1 is connected with the data input pin D of the first trigger d1, a feedback circuit is formed,
The data signal of selection is input to into the first trigger d1.The first input end I1 of the first clock signal MUX u2 with it is outer
The clock signal port CNTL connections of portion's enumerator, the second input I2 and the outside of the first clock signal MUX u2
Test clock signal port WDI connects, the clock of the outfan Z of the first clock signal MUX u2 and the first trigger d1
Port CP connects, and clock signal MUX is used to select the clock signal of input.Select the clock signal in electronic circuit many
The outfan of road selector also selects the second input of the clock selector of electronic circuit be connected with next stage simultaneously, and such as the
The outfan Z of one clock signal MUX u2 connects with the second input I2 of second clock signal MUX u4 simultaneously
Connect.The first outfan and the second outfan for selecting the trigger of electronic circuit selects the data in electronic circuit to believe with next stage respectively
Second input of number MUX and the first input end connection of clock signal MUX, trigger receives instruction
After signal and clock signal, data are latched and many of next stage are arrived in the signal data output latched in the next clock cycle
Road selector.Such as the first outfan Q and the second input I2 of the second data signal MUX u3 of the first trigger d1
Connection, the second outfan QN of the first trigger d1 is connected with the first input end I1 of second clock signal MUX u4.
The first input end I1 and the second trigger d2 of the second data signal MUX u3 of the 2nd grade of selection electronic circuit
The second outfan QN connection, the data input of the outfan Z of the second data signal MUX u3 and the second trigger d2
End D connections.The outfan Z of second clock signal MUX u4 is connected with the clock port CP of the second trigger d2, and second
The outfan Z of clock signal MUX u4 is simultaneously also defeated with the second of the clock selector of next stage selection electronic circuit
Enter end connection, the first outfan Q and the second outfan QN of the second trigger d2 select the number in electronic circuit with next stage respectively
It is believed that the first input end connection of the second input of number MUX and clock signal MUX.
First data signal MUX u1, the first clock signal MUX u2, the choosing of the second data signal multichannel
Select device u3, the selection signal end s of second clock signal MUX u4 to be connected with the test mode signal end of external test machine,
Test selection signal src_sel generated after test machine input test instruction outside receiving.
Pre-adjustment signal generating circuit is by decoding unit with data storage circuit group into decoding unit includes K levels decoding electricity
Road, K is integer, as shown in Fig. 2 the decoding unit of the present embodiment include 3 grades of decoding circuits, first with door a1, second and door a2,
5th is the 1st grade of decoding circuit with door a5, the 6th and door a6, with the quantity and selection electronic circuit of door in the 1st grade of decoding circuit
Quantity correspondence, is select electronic circuit quantity 1/2nd, is decoded for its upper level with the quantity of door in every one-level decoding circuit
With 1/2nd of door quantity in circuit.3rd is the 2nd grade of decoding circuit with door a3, the 7th and door a7, and the 4th is the 3rd with door a4
Level decoding circuit.Each in 1st grade of decoding circuit selects trigger in electronic circuit with each input of door with one-level
Outfan (Q and QN ends) connection, receive the signal from trigger any one outfan output, chosen rear trigger is every
Secondary only one of which outfan output signal.
For example, first connects with the outfan of the first trigger d1 in the first input end and the 1st grade of selection electronic circuit of door a1
Connect, receive the signal exported from first trigger d1 the first outfan Q or the second outfan QN, first is defeated with the second of door a1
Enter end selects the outfan of the second trigger d2 in electronic circuit to be connected with the 2nd grade, and reception is exported from the second trigger d2 first
The signal of end Q or the second outfan QN outputs, by that analogy, second selects electronic circuit with the first input end of door a2 with 3rd level
In trigger outfan connection, the second input is connected with the outfan of trigger in the 4th grade of selection electronic circuit；5th
The outfan of the trigger in electronic circuit is selected be connected with the first input end of door a5 with the 5th grade, the second input and the 6th grade are selected
Select the outfan connection of the trigger in electronic circuit；6th is tactile with what the first input end of door a6 and the 7th grade were selected in electronic circuit
The outfan connection of device is sent out, the second input selects the outfan of trigger in electronic circuit to be connected with the 8th grade.
In every grade of decoding circuit in each outfan with door and next stage decoding circuit one with an input of door
Connection, afterbody decoding circuit only one of which and door, should be connected with the outfan of door with data storage circuitry.Such as the 1st grade is translated
One is connected with one in the 2nd grade of decoding circuit with the outfan of door with an input of door in code circuit, the 2nd grade of decoding electricity
Lu Zhongyi is connected with the outfan of door with one in 3rd level decoding circuit with an input of door, i.e., first with door a1's
Outfan and second is connected respectively with the outfan of door a2 with the 3rd with two inputs of door a3, the 5th and door a5 outfan
It is connected with the 7th with two inputs of door a7 respectively with the outfan of door a6 with the 6th.3rd and door a3 outfan and the 7th
It is connected with two inputs of door a4 respectively at the 4th with the outfan of door a7, the 4th is electric with the outfan of door a4 and data storage
Road is connected.
Data storage circuitry includes data storage MUX uw and data storage flip-flop dw, last in decoding unit
It is connected with the outfan of door with the selection signal end of data storage MUX uw in one-level decoding circuit, data storage multichannel
The first input end I1 of selector uw and the first outfan Q connections of data storage flip-flop dw, data storage MUX
The second outfan QN connections of the second input I2 of uw and data storage flip-flop dw, data storage MUX uw it is defeated
Go out to hold the data input pin D of Z and data storage flip-flop dw to connect, clock port CP and the outside of data storage trigger dw
Test clock signal port WDI connects, and the outfan of data storage trigger dw is electric with pre-adjustment by the MUX selectores of two
Road connects.
Pre-adjusting circuit includes decoder Q1 and 2N NMOS tube, and the decoder of the present embodiment is 4-16 decoders.Translate
The input of code device Q1 is used to receive presetting entire signal, and input is by MUX selectores and data pre-adjustment signal generating circuit
Connection, the outfan of decoder Q1 exports 16 decoded signals, and each outfan is connected with the grid of a NMOS tube, respectively
The drain electrode of NMOS tube is sequentially connected, and the source electrode of each NMOS tube connects with a VREF resistance in chip reference voltage module
Connect, VREF resistance is sequentially connected, and first VREF resistance eutral grounding, last VREF resistance is connected with isolation resistance rx.
As shown in figure 3, the first outfan SW01 of decoder Q1 is connected with the grid of the first NMOS tube N1, the first NMOS tube
The source electrode of N1 is connected with a VREF resistance r1, the other end ground connection of a VREF resistance r1；Second outfan of decoder Q1
SW02 is connected with the grid of the second NMOS tube N2, and the source electrode of the second NMOS tube N2 is connected with the 2nd VREF resistance r2, the 2nd VREF
The other end of resistance r2 is connected with a VREF resistance r1, by that analogy, the 15th outfan SW15 of decoder Q1 and the tenth
The grid connection of five NMOS tubes N15, the source electrode of the 15th NMOS tube N15 is connected with the 15th VREF resistance r15, the 15th resistance
The two ends of r15 are connected respectively with the 14th VREF resistance and the 16th VREF resistance r16；16th outfan of decoder Q1
SW16 is connected with the grid of the 16th NMOS tube N16, and the source electrode of the 16th NMOS tube N16 is connected with the 16th VREF resistance r16,
The two ends of the 16th VREF resistance r16 are connected respectively with the 15th VREF resistance r15 and isolation resistance rx.In pre-adjusting circuit,
Two groups of four pre-adjustments are signally attached to control the grid whether NMOS tube turns on, and when these signals are low level, NMOS tube is led
It is logical, by the resistance conducting of adjustment, so as to change the value of reference voltage and master clock.Alternative selector that the present embodiment is used,
Trigger and door, decoder, NMOS tube are the standard cell devices on Wuxi in magnificent technology library.
It is right below by taking the reset chip of model SW1721S of Zhuhai Zhong Hui microelectronics limited company production as an example
The course of work of this utility model chip testing pre-adjusting circuit is illustrated.
Write test instruction during electricity on chip, state machine circuit passes through the number of command signal input MR connecting test machines
According to port, test pattern is entered after the test instruction that chip detection to MR is input into, and instruction input will be tested to state machine circuit,
State machine circuit enters into test mode, and now state machine circuit waits pre-adjustment instruction and the survey of test clock and reference voltage
Examination instruction；
One-level choosing after receiving the test instruction of pre-adjustment instruction and test clock and reference voltage, in state machine circuit
Selecting data signal MUX and clock signal MUX in electronic circuit selects respectively testing and control to instruct and test
Clock, and the data for being sampled by the first trigger and being preserved write in the first trigger are input to after signal behavior is sampled, altogether
There are eight triggers to preserve instruction, state machine circuit exports the test of corresponding signal control chip when write instruction is matched,
Chip is set to enter into presetting integral pattern and output reference voltage and master clock, state machine circuit inputs a signal into presetting entire signal
In producing the decoding circuit of circuit；
Pre-adjustment signal generating circuit produces two groups of totally eight pre-adjustment control signals, including four according to corresponding instruction
The presetting entire signal of individual clock signal：clk_trim[0]、clk_trim[1]、clk_trim[2]、clk_trim[3]；And four
Reference voltage adjusts signal：vref_trim[0]、vref_trim[1]、vref_trim[2]、vref_trim[3]；Chip passes through
Pre-adjustment signal generating circuit is signally attached to pre-adjusting circuit, the different resistance of control connection and electric capacity by aforementioned eight, adjusts
The value of whole controlled master clock and reference voltage；Presetting entire signal is electric by producing from presetting entire signal after the selection of MUX selectores
Road is input into pre-adjusting circuit；
Chip is that acquiescence selects connection fuse module when pre-adjustment is not entered into, and the fuse adjustment for passing through is different
Capacitance resistance value change the value of clock and voltage, after chip selects presetting integral pattern, selection signal control MUX selects presetting
Entire signal, makes pre-adjusting circuit effectively and works；
Pre-adjusting circuit is received after the adjustment control signal generated by state machine circuit, when starting corresponding to chip main
Clock and reference voltage carry out pre-adjustment, and decoder is received after pre-adjustment control signal, and by decoding corresponding adjusted value is obtained,
Four pre-adjustment control signals correspond to 16 resistance and adjust decoded signal altogether, and each adjustment control signal is input to as control
On the grid of the NMOS tube of system switch, whether control NMOS tube turns on, only when pre-adjustment decoded signal is high level, NMOS
Pipe conducting is connected in the resistance in NMOS tube drain electrode and the VREF resistance in chip reference voltage module, changes the partial pressure of reference voltage
Resistance value, so as to adjust the reference voltage value for changing chip；Structure and reference voltage pre-adjustment for the circuit of clock adjustment
Circuit structure is consistent, and what adjustment connected is the resistance value in chip clock module；
Pre-adjusting circuit set-up procedure is specific as follows：
Chip output reference voltage, and preset value is calculated, preset value is determined from low to high four vref_trim [0:
3] binary system trims numerical value, test data of chip end MR ends output vref_trim [0] value, the chip STB ends input after value writes
The low pulse width signal of one clock cycle；Test data of chip end MR ends export vref_trim [1] value, the chip after value writes
STB ends are input into the low pulse width signal of a clock cycle；Test data of chip end MR ends export vref_trim [2] value, write in value
Complete rear chip STB ends are input into the low pulse width signal of a clock cycle；Test data of chip end MR ends output vref_trim [4]
Value, chip STB ends are input into the low pulse width signal of a clock cycle after value writes, and now complete a reference voltage presetting
It is whole；
After completing a reference voltage pre-adjustment, the reference voltage of pio chip, the value for judging to read is calculated again is
It is no to meet test request, if meeting test request, qualified adjusted value is recorded and starts the master clock of pre-adjustment chip, such as
It is really undesirable, 4 vref_trim [0 are write according to the magnitude of voltage for reading again:3] binary system trims numerical value, is written to described
Pre-adjusting circuit in, read reference voltage value, until meeting test request；
Chip exports master clock, and calculates preset value, and preset value is determined from low to high four clk_trim [0:3] two
System trims numerical value, test data of chip end MR ends output clk_trim [0] value, the chip STB ends input one after value writes
The low pulse width signal of clock cycle；Test data of chip end MR ends export clk_trim [1] value, the chip STB ends after value writes
The low pulse width signal of one clock cycle of input；Test data of chip end MR ends export clk_trim [2] value, the core after value writes
Piece STB ends are input into the low pulse width signal of a clock cycle；Test data of chip end MR ends export clk_trim [4] value, in value
The low pulse width signal that rear chip STB ends are input into a clock cycle is write, a master clock pre-adjustment is now completed；
After completing a master clock pre-adjustment, chip output master clock calculates again whether the value for judging to read meets
Test request, if meeting test request, completes to test presetting integral pattern, if undesirable, according to read it is main when
Clock value writes 4 clk_trim [0 again:3] binary system trims numerical value, in being written to the pre-adjusting circuit of chip, reads master clock
Value, until meeting test request.
After the complete master clock of chip pre-adjustment, qualified adjusted value is recorded, chip simultaneously exits presetting integral pattern, and by benchmark
Magnitude of voltage is exported to test machine by PFO, and master clock is exported to test machine by RST mouths.Chip completes presetting integral pattern
Afterwards, corresponding value can be recorded and preserves the value, be adjusted in fuse with being applied to chip testing, realize the tune of chip
Whole test.
Test pre-adjusting circuit of the present utility model combines requirement of the chip to circuit area, employs low cost multiplexing electricity
Line structure, only enters under corresponding test pattern in chip, pre-adjusting circuit just can normal work, with reliability it is high,
Area is little, the characteristics of easily realize, can while chip area is not increased the port of multiplexing chip and partial status it is electromechanical
Road, by the master clock and reference voltage value that change chip with corresponding instruction, with convenience and ease for operation, it is possible to anti-
Test target is adjusted to again.
Above example only to illustrate the technical solution of the utility model rather than a limitation, although with reference to above-mentioned enforcement
Example has been described in detail to this utility model, it should be understood by a person of ordinary skill in the art that still can be to this reality
Modified with new specific embodiment or equivalent, and repaiied without departing from any of this utility model spirit and scope
Change or equivalent, it all should cover among right of the present utility model.
Claims (9)
1. chip testing pre-adjusting circuit, it is characterised in that include：
State machine circuit, for control chip test pattern and presetting integral pattern are entered, and complete pre-adjustment backed off after random in chip
Presetting integral pattern；
Pre-adjustment signal generating circuit, for producing corresponding pre-adjustment control signal according to external command；
Pre-adjusting circuit, for adjusting the resistance capacitance value of chip internal by the different pre-adjustment control signal of matching, to change
Become the clock and reference voltage value of chip.
2. chip testing pre-adjusting circuit according to claim 1, it is characterised in that：The state machine circuit is included successively
The N levels of connection select electronic circuit, and per grade selects electronic circuit to include data signal MUX, a clock signal multichannel
The selection signal end of selector and a trigger, data signal MUX and clock signal MUX and outside survey
The test mode signal end connection of test-run a machine；
The first input end of the data signal MUX of the 1st grade of selection electronic circuit and the second outfan of the first trigger connect
Connect, the second input is connected with the command signal input of outside, outfan is connected with the data input pin of the first trigger, the
1 grade selection electronic circuit the first input end of clock signal MUX be connected with the clock signal port of external counter,
Second input be connected with the test clock signal port of outside, the clock port of outfan and the first trigger and the 2nd grade are selected
Select the second input connection of the clock selector of electronic circuit, first outfan and the second outfan of trigger respectively with
2nd grade of the second input for selecting the data signal MUX in electronic circuit and clock signal MUX it is first defeated
Enter end connection；
The first input end of the data signal MUX of n-th grade of selection electronic circuit and the second outfan of the n-th trigger connect
Connect, the second input and upper level select the first outfan of the trigger of electronic circuit to be connected, the number of outfan and the n-th trigger
Connect according to input, first input end and the upper level of the clock signal MUX of n-th grade of selection electronic circuit select son electricity
The clock signal MUX of the connection of the second outfan, the second input and upper level selection electronic circuit of the trigger on road
Outfan connection, outfan are connected with the clock port of the n-th trigger, and the first outfan of trigger and the second outfan are distinguished
The second input of the data signal MUX in electronic circuit and the of clock signal MUX is selected with next stage
One input connects, wherein, n=2,3 ..., N.
3. chip testing pre-adjusting circuit according to claim 1, it is characterised in that：The pre-adjustment signal generating circuit
Including decoding unit and data storage circuitry, wherein, decoding unit include K level decoding circuits, per one-level decoding circuit by with door
Constitute, data storage circuitry includes data storage MUX and data storage flip-flop；
Each of 1st grade of decoding circuit connects successively with each input of door with the outfan of trigger in selection electronic circuits at different levels
Connect, each is connected with the outfan of door with one in next stage decoding circuit with an input of door in every grade of decoding circuit,
Afterbody decoding circuit has one and door, should be with the outfan of door and data storage MUX in data storage circuitry
Selection signal end connects；
The first input end of data storage MUX and the connection of the first outfan, second input of data storage flip-flop
With the data input pin connection of the connection of the second outfan, outfan and data storage flip-flop of data storage flip-flop, data
The clock port of storage flip-flop is connected with the test clock signal port of outside, outfan is by MUX selectores and pre-adjustment
Circuit connects.
4. chip testing pre-adjusting circuit according to claim 1, it is characterised in that：The pre-adjusting circuit includes decoding
Device and NMOS tube, the input of decoder is connected with data pre-adjustment signal generating circuit, each outfan point of decoder
It is not connected with the grid of a NMOS tube, the drain electrode of each NMOS tube is sequentially connected, the source electrode of each NMOS tube is and chip reference
VREF resistance connection in voltage module.
5. chip testing pre-adjusting circuit according to claim 2, it is characterised in that：The MUX is selected more than 1 for 2
Road selector.
6. chip testing pre-adjusting circuit according to claim 4, it is characterised in that：The decoder is 4-16 decodings
Device.
7. chip testing pre-adjusting circuit according to claim 2, it is characterised in that：The state machine circuit includes 8 grades
Select electronic circuit.
8. chip testing pre-adjusting circuit according to claim 3, it is characterised in that：The decoding unit is translated including 3 grades
Code circuit, first with door, second with door, the 5th with door, the 6th with 1 grade of decoding circuit of Men Wei, the 3rd is with door with door, the 7th
2nd grade of decoding circuit, the 4th is 3rd level decoding circuit with door；The input of each in the 1st grade of decoding circuit and door with
One-level selects the outfan connection of trigger in electronic circuit, with the outfan and next stage decoding circuit of door in every grade of decoding circuit
In be connected with the input of door, be connected with data storage circuitry with the outfan of door in 3rd level decoding circuit.
9. chip testing pre-adjusting circuit according to claim 3, it is characterised in that：Translate for the 1st grade in the decoding unit
It is corresponding with the quantity for selecting electronic circuit with the quantity of door in code circuit, it is select electronic circuit quantity 1/2nd, translate per one-level
Code circuit in the quantity of door be in its upper level decoding circuit with door quantity 1/2nd.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621112410.6U CN206178094U (en) | 2016-10-10 | 2016-10-10 | Chip testing preliminary adjustment circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108196181A (en) * | 2017-12-18 | 2018-06-22 | 上海艾为电子技术股份有限公司 | A kind of chip test mode access method, into system and chip |
| CN114428204A (en) * | 2020-10-29 | 2022-05-03 | 长鑫存储技术有限公司 | Method and device for adjusting chip output characteristics |
| US12002751B2 (en) | 2020-10-29 | 2024-06-04 | Changxin Memory Technologies, Inc. | Adjustment method and device for chip output characteristics |
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2016
- 2016-10-10 CN CN201621112410.6U patent/CN206178094U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108196181A (en) * | 2017-12-18 | 2018-06-22 | 上海艾为电子技术股份有限公司 | A kind of chip test mode access method, into system and chip |
| CN114428204A (en) * | 2020-10-29 | 2022-05-03 | 长鑫存储技术有限公司 | Method and device for adjusting chip output characteristics |
| CN114428204B (en) * | 2020-10-29 | 2023-09-01 | 长鑫存储技术有限公司 | Chip output characteristic adjusting method and device |
| US12002751B2 (en) | 2020-10-29 | 2024-06-04 | Changxin Memory Technologies, Inc. | Adjustment method and device for chip output characteristics |
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