JP2004045090A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of testing individually a functional block out of a plurality which are provided, reducing the number of terminals for setting an operation mode to a minimum when a test is performed. <P>SOLUTION: An operation mode setting circuit 20 receives a test signal TEST, a reset signal RESET, and an external clock CLK from terminals 12, 14, and 16 respectively, sets an operation mode for the semiconductor integrated circuit 10, and outputs an operation mode setting signal SET<0:n-1> of a bit length n to a decoder 22. The decoder 22 decodes the setting signal SET<0:n-1>, asserts either a test mode selecting signal TM1-TM2<SP>n</SP>-1 or normal operation mode selecting signal NM, and outputs it to a selector 24. The selector 24 connects a specified functional block to input/output terminals 18 according to these selecting signals, and a test of the functional block according to the set operation mode is performed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a plurality of function blocks and a plurality of operation modes corresponding to a test that can be performed for each function block.
[0002]
[Prior art]
2. Description of the Related Art In recent years, semiconductor integrated circuits have become more sophisticated and multifunctional, and one semiconductor integrated circuit is generally composed of a plurality of functional blocks. In a semiconductor integrated circuit having a plurality of functional blocks, since each functional block affects each other, it is not easy to detect which functional block has a defect even when testing the semiconductor integrated circuit as a whole. Therefore, in a semiconductor integrated circuit having such a plurality of functional blocks, each functional block is independently connected to an external connection terminal, and an operation mode in which a functional test can be executed for each functional block corresponds to each functional block. The provision of the test has facilitated the test.
[0003]
A dedicated operation mode setting terminal for externally setting an operation mode corresponding to the test of each functional block is provided, and a function block to be tested is selected by a signal applied to the operation mode setting terminal. .
[0004]
FIG. 18 is a schematic block diagram showing the overall configuration of a conventional semiconductor integrated circuit including a plurality of functional blocks and capable of testing each functional block.
[0005]
18, semiconductor integrated circuit 100 includes operation mode setting terminal 112, input / output terminal 18, decoder 22, selector 24, functional blocks FB1 to FBm, and bus 26. Note that FIG. 18 representatively shows main parts related to setting of the operation mode of the semiconductor integrated circuit 100.
[0006]
The operation mode setting terminal 112 is a test-only terminal that receives an operation mode setting signal TEST <0: n−1> (n is a natural number) for setting the operation mode of the semiconductor integrated circuit 100 from the outside when the semiconductor integrated circuit 100 is tested. is there. The operation mode setting terminal 112 is composed of n terminals, and operates in response to an operation mode setting signal TEST <0: n−1> input to the operation mode setting terminal 112. ⁿ Different operation modes can be set.
[0007]
The decoder 22 decodes the operation mode setting signals TEST <0: n−1> input from the operation mode setting terminal 112, and outputs test mode selection signals TM1 to TM2. ⁿ -1 and the normal operation mode selection signal NM are asserted and output to the selector 24.
[0008]
The input / output terminal 18 is a terminal for exchanging data and commands input / output to / from the semiconductor integrated circuit 100 with the outside. The input / output terminal 18 is not provided specifically for the test, but is a terminal used during a normal operation. The input / output terminal 18 receives data and the like input to the semiconductor integrated circuit 100 from the outside during normal operation, and outputs data and the like output from the semiconductor integrated circuit 100 to the outside. On the other hand, at the time of testing, the input / output terminal 18 receives test data input to a function block corresponding to the set operation mode from the outside, and outputs data corresponding to the test result output from the function block. Output to outside.
[0009]
Selector 24 receives test mode selection signals TM1 to TM2 received from decoder 22. ⁿ The corresponding functional block is connected to the input / output terminal 18 according to -1 and the normal operation mode selection signal NM. That is, the selector 24 connects the function block FB1 to the input / output terminal 18 when the test mode selection signal TM1 corresponding to the test of the function block FB1 is asserted. Similarly, the selector 24 connects the functional block FBm to the input / output terminal 18 when the test mode selection signal TMm corresponding to the test of the functional block FBm (m is a natural number of 2 or more) is asserted.
[0010]
When the normal operation mode selection signal NM is asserted, the selector 24 connects each functional block to the input / output terminal 18 in a predetermined connection relationship so that the semiconductor integrated circuit 100 performs a normal operation as a whole. I do.
[0011]
The functional blocks FB1 to FBm are functional blocks having individual functions in the semiconductor integrated circuit 100. Each of the function blocks FB1 to FBm receives a test mode selection signal corresponding to its own function block from the decoder 22, and when the test mode selection signal is asserted, it is connected to only the selector 24 and selects the test mode selection. If the signal is not asserted, it is connected to selector 24 and bus 26.
[0012]
The bus 26 is an internal bus for exchanging various signals such as data and instructions between the functional blocks FB1 to FBm.
[0013]
FIG. 19 is a diagram showing the correspondence between the set values of the operation mode input from the operation mode setting terminal 112 and the contents of the operation mode.
[0014]
Referring to FIG. 19, in semiconductor integrated circuit 100, when operation mode setting signal TEST <0: n−1> corresponding to value “0” is set from operation mode setting terminal 112, the normal operation mode is selected. Is done. When the operation mode setting signal TEST <0: n−1> corresponding to the value “1” is set from the operation mode setting terminal 112, the function block FB1 test mode for performing the function test of the function block FB1 is selected. Similarly, when an operation mode setting signal TEST <0: n−1> corresponding to the value “m” is set from operation mode setting terminal 112, a function block FBm test mode for performing a function test of function block FBm is selected. Is done.
[0015]
Note that the set values “m + 1” to “2” ⁿ Although the operation mode is not particularly assigned to -1 ″, in the semiconductor integrated circuit 100, a maximum of 2 ⁿ (The operation mode setting value is "2 ⁿ Operation mode can be set.
[0016]
Referring to FIG. 18 again, in semiconductor integrated circuit 100, for example, when operation mode setting signal TEST <0: n−1> corresponding to value “1” is set from operation mode setting terminal 112, decoder 22 Decodes the operation mode setting signals TEST <0: n-1> and asserts the test mode selection signal TM1.
[0017]
When the test mode selection signal TM1 is asserted, the functional block FB1 exchanges data with only the selector 24. On the other hand, the selector 24 connects only the functional block FB1 to the input / output terminal 18. Therefore, by inputting test data corresponding to the function block FB1 from the input / output terminal 18, the function block FB1 can be tested independently of other function blocks.
[0018]
When an operation mode setting value corresponding to a test of another functional block is input to the operation mode setting terminal 112, an independent test is similarly performed for each corresponding functional block.
[0019]
On the other hand, when the operation mode setting signal TEST <0: n−1> corresponding to the value “0” is set from the operation mode setting terminal 112, the decoder 22 outputs the operation mode setting signal TEST <0: n−1>. Decode and assert the normal operation mode selection signal NM. When the normal operation mode selection signal NM is asserted, the selector 24 connects each functional block to the input / output terminal 18 in a predetermined connection relationship so that the semiconductor integrated circuit 100 performs a normal operation as a whole. Then, when data is input from the input / output terminal 18, in the semiconductor integrated circuit 100, the functional blocks FB1 to FBm operate in association with each other, and realize a normal function.
[0020]
FIG. 20 is a functional block diagram functionally describing the selector 24 shown in FIG.
[0021]
Referring to FIG. 20, selector 24 includes a plurality of circuits 241 corresponding to each of input / output terminals 18. Each of the circuits 241 includes internal selectors 243 and 245, an output buffer 247, an input buffer 249, and AND gates G1 to Gm.
[0022]
Hereinafter, the circuit 241 connected to the terminal 181 which is one terminal of the input / output terminal 18 will be described. The internal selector 243 outputs test mode selection signals TM1 to TM2 ⁿ -1 and the normal operation mode selection signal NM are received from the decoder 22. Further, the internal selector 243 receives signals output from each of the functional blocks FB1 to FBm. Then, the internal selector 243 outputs an output signal from the functional block corresponding to the asserted test mode selection signal to the output buffer 247.
[0023]
The output buffer 247 outputs the signal output from the internal selector 243 to the terminal 181.
[0024]
Internal selector 245 receives test mode selection signals TM1 to TMm and normal operation mode selection signal NM from decoder 22. When any of the test mode selection signals TM1 to TMm is asserted, the internal selector 245 outputs the asserted test mode selection signal to the corresponding one of the AND gates G1 to Gm as it is. When the normal operation mode selection signal NM is asserted, the internal selector 245 asserts a predetermined signal so that the semiconductor integrated circuit 100 performs a normal operation as a whole, and outputs the AND gate G1. To Gm.
[0025]
The input buffer 249 inputs the signal received by the terminal 181 and outputs the signal to the AND gates G1 to Gm. AND gate G1 calculates the logical product of the signals received from internal selector 245 and input buffer 249, and outputs the calculation result to functional block FB1. The other AND gates G2 to Gm also function similarly, and therefore, description thereof will not be repeated.
[0026]
Hereinafter, the operation of the selector 24 will be described by taking as an example the case where the test mode selection signal TM1 is asserted. When the test mode selection signal TM1 is asserted, the internal selector 245 asserts the signal output to the AND gate G1 and negates the signals output to the other AND gates G2 to Gm. Therefore, in each circuit 241, only the AND gate G1 outputs the signal output from the input buffer 249, and no signals are output from the other AND gates G2 to Gm to the corresponding functional blocks. That is, the signal input from the input / output terminal 18 is output from each circuit 241 only to the functional block FB1.
[0027]
On the other hand, when the test mode selection signal TM1 is asserted, the internal selector 243 outputs the signal output from the functional block FB1 to the output buffer 247. Therefore, the signal output from functional block FB 1 is output to input / output terminal 18.
[0028]
As described above, the operation mode of the semiconductor integrated circuit 100 is set based on the operation mode setting value input from the operation mode setting terminal 112, and a test is performed for each functional block of the semiconductor integrated circuit 100.
[0029]
[Problems to be solved by the invention]
In the above-described conventional semiconductor integrated circuit 100, the operation mode setting terminal 112 to which the operation mode setting signal TEST <0: n-1> for executing the test for each functional block is configured by n terminals Is done. Therefore, when the number of functional blocks constituting the semiconductor integrated circuit increases, the number of operation modes also increases, and accordingly, the number of terminals constituting the operation mode setting terminal 112 also increases.
[0030]
2. Description of the Related Art In recent years, semiconductor integrated circuits have become more sophisticated and multifunctional, and the number of functional blocks included in the semiconductor integrated circuit tends to further increase. Accordingly, while the number of normal terminals for inputting and outputting data and commands increases, as described above, as the number of functional blocks increases, the number of terminals constituting the operation mode setting terminal, which is a test-only terminal, increases. When the number also increases, the total number of terminals that the semiconductor integrated circuit can have is limited, so that the number of terminals is generally limited, and further enhancement of functions and multifunctionality are limited.
[0031]
In addition, the increase in the number of terminals constituting the operation mode setting terminal, which is a dedicated test terminal, imposes restrictions on miniaturization of the semiconductor integrated circuit, and it is not possible to cope with recent demands for miniaturization of the semiconductor integrated circuit.
[0032]
Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to minimize the number of terminals for setting an operation mode at the time of a test and to provide a plurality of functional blocks. An object of the present invention is to provide a semiconductor integrated circuit that can be individually tested.
[0033]
[Means for Solving the Problems]
According to the present invention, the semiconductor integrated circuit is a semiconductor integrated circuit having a plurality of operation modes, wherein the operation mode setting circuit sets any one of the plurality of operation modes based on a control signal input from a predetermined terminal And an internal circuit that operates in the operation mode set by the operation mode setting circuit.
[0034]
Preferably, the predetermined terminal is constituted by one terminal.
Preferably, each of the plurality of operation modes is one of each of at least one test mode and a normal operation mode, and the operation mode setting circuit, when the control signal is at a first logic level at a predetermined timing, , One of at least one test mode is set based on the control signal input to the control unit, and when the control signal is at the second logic level at a predetermined timing, the normal operation mode is set.
[0035]
Preferably, the operation mode setting circuit receives the external clock, and when the control signal is at a first logic level at a predetermined timing, the external mode during the period when the control signal subsequently input is at the first logic level The number of cycles is counted, and one of at least one test mode is set based on the count value.
[0036]
Preferably, the control signal includes serial data consisting of a code indicating an operation mode, and the operation mode setting circuit fetches serial data input thereafter when the control signal is at the first logic level at a predetermined timing; One of at least one test mode is set based on the acquired serial data.
[0037]
Preferably, when the control signal is at the first logic level at a predetermined timing, the operation mode setting circuit may determine at least one of the at least one operation signal based on data input from at least one terminal used during normal operation of the semiconductor integrated circuit. Set one of the test modes.
[0038]
Preferably, when the control signal is at the first logic level at a predetermined timing, the operation mode setting circuit may include at least one terminal used during normal operation of the semiconductor integrated circuit in synchronization with a subsequent change in the control signal. And setting one of at least one test mode based on the taken data.
[0039]
Preferably, when the control signal is at the first logical level at a predetermined timing, the operation mode setting circuit synchronizes with a subsequent change of the control signal and at least one of the operation modes set at the time of the change. The setting of the operation mode is shifted to one of the test modes in a predetermined order.
[0040]
Preferably, the predetermined timing is a timing at which the reset operation is canceled in the operation mode setting circuit.
[0041]
Preferably, the operation mode setting circuit sets a predetermined operation mode in a reset operation.
[0042]
Preferably, the predetermined operation mode is a DC test mode, and the operation mode setting circuit receives the external clock, and holds the setting of the DC test mode when the external clock is not input after the reset operation is released.
[0043]
Preferably, the operation mode setting circuit sets the operation mode based on the control signal, and then outputs the set operation mode to the outside.
[0044]
As described above, in the semiconductor integrated circuit according to the present invention, the operation mode setting circuit sets any one of the plurality of operation modes based on the control signal input from the predetermined terminal.
[0045]
Therefore, according to the present invention, the semiconductor integrated circuit does not need to include many operation mode setting terminals dedicated to the test, and can reduce the number of dedicated terminals required for setting the operation mode.
[0046]
Then, by reducing the number of dedicated terminals required for setting the operation mode, terminals having a limited number can be used as terminals for achieving the original function of the semiconductor integrated circuit, Even higher functionality can be realized.
[0047]
Furthermore, if the number of terminals is reduced, the size of the semiconductor integrated circuit can be reduced.
[0048]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.
[0049]
[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor integrated circuit according to Embodiment 1 of the present invention.
[0050]
Referring to FIG. 1, a semiconductor integrated circuit 10 includes terminals 12, 14, 16, an input / output terminal 18, an operation mode setting circuit 20, a decoder 22, a selector 24, functional blocks FB1 to FBm, a bus 26. Note that FIG. 1 representatively shows a main part of the semiconductor integrated circuit 10 relating to the setting of the operation mode of the semiconductor integrated circuit 10.
[0051]
The semiconductor integrated circuit 10 includes a terminal 12 formed of one terminal in place of the operation mode setting terminal 112 formed of n terminals in the configuration of the semiconductor integrated circuit 100 described in the related art. The configuration of the semiconductor integrated circuit 100 according to the related art differs from the configuration of the conventional semiconductor integrated circuit 100 in further including a mode setting circuit 20.
[0052]
The terminal 12 receives a control signal CNTL used for setting an operation mode of the semiconductor integrated circuit 10 in an operation mode setting circuit 20, which will be described later, at the time of testing the semiconductor integrated circuit 10. The terminal 12 is composed of one terminal as described above, and is controlled by the operation mode setting circuit 20 using the control signal CNTL input from the terminal 12. ⁿ Different operation modes can be set.
[0053]
Terminal 14 receives reset signal RESET, and terminal 16 receives external clock CLK. Although these terminals are not shown in the description of the conventional semiconductor integrated circuit 100, they are also provided in the conventional semiconductor integrated circuit 100, and are newly provided in the semiconductor integrated circuit 10 according to the first embodiment. It is not provided.
[0054]
The operation mode setting circuit 20 receives the control signal CNTL, the reset signal RESET, and the external clock CLK from the terminals 12, 14, and 16, respectively, sets the operation mode of the semiconductor integrated circuit 10, and sets the n-bit-length operation mode setting signal SET < 0: n-1> to the decoder 22. Then, the decoder 22 decodes the operation mode setting signals SET <0: n−1> output from the operation mode setting circuit 20, and outputs the test mode selection signals TM1 to TM2. ⁿ -1 and the normal operation mode selection signal NM are asserted and output to the selector 24.
[0055]
Other configurations and operations of semiconductor integrated circuit 10 are the same as those of conventional semiconductor integrated circuit 100, and therefore, description thereof will not be repeated.
[0056]
FIG. 2 is a functional block diagram for functionally explaining operation mode setting circuit 20 in semiconductor integrated circuit 10 according to the first embodiment.
[0057]
Referring to FIG. 2, operation mode setting circuit 20 includes a counter 201. The counter 201 resets the internal counter value to 0 when the reset signal RESET is asserted. When the control signal CNTL is asserted when the reset signal RESET is negated and the reset is released, the counter 201 counts the number of cycles of the external clock CLK during a period in which the control signal CNTL is subsequently asserted. The value is output to the decoder 22 as the operation mode setting signal SET <0: n-1>.
[0058]
On the other hand, when the control signal CNTL is not asserted when the reset signal RESET is negated, the counter 201 does not count the external clock CLK and outputs the reset counter value 0 to the decoder 22. That is, the operation mode of the semiconductor integrated circuit 10 is set to the normal operation mode.
[0059]
FIG. 3 is an operation waveform diagram of each signal when the normal operation mode is set in semiconductor integrated circuit 10 according to the first embodiment.
[0060]
Referring to FIG. 3, at time T1, reset signal RESET is asserted, and the counter value of counter 201 is reset to 0. The control signal CNTL is negated at time T2 before the reset signal RESET is negated. Note that, in the figure, a hatched portion in the control signal CNTL indicates that the signal state is not specified.
[0061]
Then, at time T2, the reset signal RESET is negated, but since the control signal CNTL is negated, the counter 201 does not count the external clock CLK, and the counter 201 performs the operation mode setting signal SET <0: n. -1> is output as 0.
[0062]
Therefore, the decoder 22 asserts the normal operation mode selection signal NM and outputs it to the selector 24 based on the fact that the operation mode setting signals SET <0: n−1> are set to 0. Therefore, semiconductor integrated circuit 10 operates in the normal operation mode.
[0063]
FIG. 4 is an operation waveform diagram of each signal when the test mode is set in the semiconductor integrated circuit 10.
[0064]
Referring to FIG. 4, at time T1, reset signal RESET is asserted, and the counter value of counter 201 is reset to 0. The control signal CNTL is asserted at time T2 before the reset signal RESET is negated.
[0065]
At time T2, when the reset signal RESET is negated, the counter 201 starts counting the number of cycles of the external clock CLK from time T3 when the external clock CLK rises next. Then, counter 201 counts the number of rising edges of external clock CLK from time T3 to time T4 until control signal CNTL is negated at time T5, and outputs the counter value to decoder 22 as an operation mode setting value.
[0066]
Then, based on the operation mode setting signals SET <0: n−1> received from the counter 201, the decoder 22 outputs the test mode selection signals TM1 to TM2. ⁿ The corresponding test mode selection signal of −1 is asserted and output to the selector 24. In the selector 24, the functional block corresponding to the asserted test mode selection signal is connected to the input / output terminal 18. As a result, in the semiconductor integrated circuit 10, a test of a functional block corresponding to the set operation mode is executed.
[0067]
As described above, according to semiconductor integrated circuit 10 of the first embodiment, since operation mode setting circuit 20 for setting an operation mode is provided in semiconductor integrated circuit 10, a terminal for inputting a signal for setting an operation mode is provided. Can be greatly reduced. As a result, the terminals whose number is limited can be used as signal input / output terminals for achieving the original function of the semiconductor integrated circuit 10, and further enhancement of the function of the semiconductor integrated circuit 10 can be realized. Further, since the number of terminals can be reduced, the size of the semiconductor integrated circuit 10 can be reduced.
[0068]
[Embodiment 2]
Semiconductor integrated circuit 10A according to the second embodiment has an operation mode setting circuit 20A instead of operation mode setting circuit 20 in the configuration of semiconductor integrated circuit 10 according to the first embodiment.
[0069]
Similarly to operation mode setting circuit 20 in the first embodiment, operation mode setting circuit 20A receives control signal CNTL, reset signal RESET, and external clock CLK from terminals 12, 14, and 16, respectively, and operates operation mode of semiconductor integrated circuit 10A. And outputs an n-bit operation mode setting signal SET <0: n−1> to the decoder 22.
[0070]
Other configurations and operations of semiconductor integrated circuit 10A are the same as those of semiconductor integrated circuit 10 according to the first embodiment, and therefore description thereof will not be repeated.
[0071]
In semiconductor integrated circuit 10A according to the second embodiment, an operation mode set value is input as serial data from terminal 12 as control signal CNTL. The operation mode setting circuit 20A receives the control signal CNTL, the reset signal RESET, and the external clock CLK, detects whether or not the operation mode is the test mode based on the state of these signals. CNTL is converted into an operation mode setting signal SET <0: n−1> of n-bit parallel data and output to the decoder 22.
[0072]
FIG. 5 is a functional block diagram for functionally explaining operation mode setting circuit 20A in semiconductor integrated circuit 10A according to the second embodiment.
[0073]
Referring to FIG. 5, operation mode setting circuit 20A includes a shift register 202 and a test mode detection circuit 204.
[0074]
The shift register 202 resets the internal state when the reset signal RESET is asserted. When the reset signal RESET is negated and the enable signal ENABLE received from the test mode detection circuit 204 is asserted when the reset signal RESET is negated, the shift register 202 takes in the control signal CNTL which is serial data in synchronization with the external clock CLK. The fetched serial data is output to the decoder 22 as an operation mode setting signal SET <0: n−1> which is n-bit parallel data.
[0075]
The test mode detection circuit 204 receives the control signal CNTL, the reset signal RESET, and the external clock CLK, and when the reset signal RESET is negated, recognizes that the control signal CNTL is asserted to indicate that the test mode is set, and thereafter the shift register The enable signal ENABLE is asserted for a time necessary for the control signal CNTL to be read into 202. The external clock CLK is used to count a predetermined time required for the control signal CNTL to be read into the shift register 202. During the counting, the signal ENABLE is asserted.
[0076]
On the other hand, when the reset signal is negated, the test mode detection circuit 204 does not assert the enable signal ENABLE unless the control signal CNTL is asserted. Therefore, the shift register 202 does not take in the control signal CNTL, and outputs the reset value 0 to the decoder 22. That is, the operation mode of semiconductor integrated circuit 10A is set to the normal operation mode.
[0077]
FIG. 6 is an operation waveform diagram of each signal when the test mode is set in semiconductor integrated circuit 10A according to the second embodiment.
[0078]
Referring to FIG. 6, at time T1, reset signal RESET is asserted, and the state of shift register 202 is reset. The control signal CNTL is asserted at time T2 before the reset signal RESET is negated.
[0079]
At time T2, when the reset signal RESET is negated and the control signal CNTL is asserted, the test mode detection circuit 204 recognizes that the current mode is the test mode, and asserts the enable signal ENABLE. When the enable signal ENABLE is asserted, the shift register 202 starts taking in the control signal CNTL which is serial data of the operation mode setting value. Thereafter, the control signal CNTL is input to the shift register 202, and the input is completed by time T3. Test mode detection circuit 204 negates enable signal ENABLE at time T3.
[0080]
Then, the shift register 202 outputs the operation mode setting value captured as the serial data to the decoder 22 as the operation mode setting signal SET <0: n−1> of the parallel data. Subsequent operations are the same as those of semiconductor integrated circuit 10 according to the first embodiment, and therefore description thereof will not be repeated.
[0081]
As described above, also with the semiconductor integrated circuit 10A according to the second embodiment, the number of terminals for inputting signals for setting an operation mode is significantly reduced, and the same effect as that of the first embodiment can be obtained.
[0082]
[Embodiment 3]
FIG. 7 is a schematic block diagram showing the entire configuration of the semiconductor integrated circuit according to the third embodiment.
[0083]
Referring to FIG. 7, a semiconductor integrated circuit 10B according to the third embodiment has an operation mode setting circuit 20B in place of operation mode setting circuit 20 in the configuration of semiconductor integrated circuit 10 according to the first embodiment, and The circuit 20B is connected to the input / output terminal 18.
[0084]
The operation mode setting circuit 20B receives the control signal CNTL, the reset signal RESET, and the external clock CLK from the terminals 12, 14, and 16, respectively, and further receives the operation mode setting value from the input / output terminal 18 during the operation mode setting period. Then, the operation mode setting circuit 20 </ b> B outputs an operation mode setting signal SET <0: n−1> to the decoder 22 based on the received operation mode setting value.
[0085]
Other configurations and operations of semiconductor integrated circuit 10B are the same as those of semiconductor integrated circuit 10 according to the first embodiment, and therefore description thereof will not be repeated.
[0086]
In semiconductor integrated circuit 10B according to the third embodiment, an operation mode setting value is input from input / output terminal 18 during the operation mode setting period. When the input of the operation mode setting value is completed and the operation mode is set, test data corresponding to the set operation mode is input / output from the input / output terminal 18, and the function block corresponding to the operation mode is input. Test is performed.
[0087]
FIG. 8 is a functional block diagram for functionally explaining operation mode setting circuit 20B in semiconductor integrated circuit 10B according to the third embodiment.
[0088]
Referring to FIG. 8, operation mode setting circuit 20B includes a flip-flop 206. The flip-flop 206 resets the internal state when the reset signal RESET is asserted. When the reset signal RESET is negated and the reset state is released and the control signal CNTL is asserted, the flip-flop 206 fetches the operation mode set value from the input / output terminal 18 and outputs it to the decoder 22.
[0089]
When the control signal CNTL is negated, the flip-flop 206 does not take in data from the input / output terminal 18 and holds and outputs data before the control signal CNTL is negated. Therefore, even if the data from the input / output terminal 18 subsequently changes, the flip-flop 206 continues to hold the operation mode set during the period in which the control signal CNTL was asserted, and outputs the operation mode to the decoder 22. . Note that the external clock CLK is used in the flip-flop 206 to give a timing of capturing a signal from the input terminal D.
[0090]
On the other hand, when the reset signal RESET is negated and the control signal CNTL is not asserted, the reset value 0 is output to the decoder 22. That is, the operation mode of semiconductor integrated circuit 10B is set to the normal operation mode.
[0091]
FIG. 9 is an operation waveform diagram of each signal when the test mode is set in semiconductor integrated circuit 10B according to the third embodiment.
[0092]
Referring to FIG. 9, at time T1, reset signal RESET is asserted, and the internal state of flip-flop 206 is reset. Before the reset signal RESET is negated at the time T2, the control signal CNTL is asserted, and the operation mode set value is input to the input / output terminal 18.
[0093]
At time T2, when the reset signal RESET is negated and the reset state is released in the flip-flop 206, since the control signal CNTL is asserted, the flip-flop 206 takes in the operation mode setting value from the input / output terminal 18, Output to the decoder 22. Then, at time T3, when the control signal CNTL is negated, the flip-flop 206 latches the operation mode setting value, and thereafter, the latched operation mode setting value regardless of a change in data input from the input / output terminal 18. To the decoder 22.
[0094]
After the lapse of time T3, test data is input / output from the input / output terminal 18, and the test data is input / output to / from a functional block corresponding to the set operation mode, and a test is executed.
[0095]
When the operation mode setting circuit is formed by a flip-flop, a control signal CNTL can be used instead of the external clock CLK for giving the timing of taking in each input signal.
[0096]
FIG. 10 is a functional block diagram for functionally explaining another operation mode setting circuit 20C in the semiconductor integrated circuit 10B according to the third embodiment.
[0097]
Referring to FIG. 10, operation mode setting circuit 20C includes flip-flop 208. In the flip-flop 208, a control signal CNTL is used instead of the external clock CLK for giving a timing of receiving a signal from the input terminal D. Flip-flop 208 fetches data from input / output terminal 18 at the rising timing of control signal CNTL, latches the fetched data, and outputs it to decoder 22. When the control signal CNTL does not change, data is not fetched from the input / output terminal 18, so that even if test data is subsequently input from the input / output terminal 18, the operation mode is not changed.
[0098]
FIG. 11 is an operation waveform diagram of each signal when the operation mode setting circuit 20C is used in the semiconductor integrated circuit 10B.
[0099]
Referring to FIG. 11, at time T1, reset signal RESET is asserted, and the internal state of flip-flop 208 is reset. Before the reset signal RESET is negated at the time T2, the control signal CNTL is asserted.
[0100]
After the reset signal RESET is negated at time T2, the control signal CNTL falls once at time T3 and rises again at time T4, and the flip-flop 208 switches the operation mode set value D1 from the input / output terminal 18 at the rising timing. The operation mode setting value D1 is output to the decoder 22. Between time T4 and time T5, control signal CNTL does not change, and even if data input from input / output terminal 18 changes, the operation mode setting value output from flip-flop 208 to decoder 22 changes from D1. The test can be performed by inputting / outputting test data from the input / output terminal 18 during this time.
[0101]
Next, when the control signal CNTL falls once at time T5 and rises again at time T6, the flip-flop 208 takes in the operation mode set value D2 from the input / output terminal 18 at the rising timing and latches it. The mode setting value D2 is output to the decoder 22. After time T6, the control signal CNTL does not change, and even if the data input from the input / output terminal 18 changes, the operation mode setting value output from the flip-flop 208 to the decoder 22 does not change from D2, A test can be performed by inputting and outputting test data from the output terminal 18.
[0102]
As described above, according to the semiconductor integrated circuit 10B of the third embodiment, since the operation mode setting value is input from the normal input / output terminal 18 not dedicated to the test, the signal for setting the operation mode at the time of the test is used. The number of terminals dedicated to the test for inputting is greatly reduced, and the same effect as in the first embodiment can be obtained.
[0103]
[Embodiment 4]
The semiconductor integrated circuit 10D according to the fourth embodiment has an operation mode setting circuit 20D instead of the operation mode setting circuit 20 in the configuration of the semiconductor integrated circuit 10 according to the first embodiment.
[0104]
Similarly to operation mode setting circuit 20 in the first embodiment, operation mode setting circuit 20D receives control signal CNTL and reset signal RESET from terminals 12 and 14, sets the operation mode of semiconductor integrated circuit 10D, and sets the n-bit length. The operation mode setting signals SET <0: n−1> are output to the decoder 22.
[0105]
Then, each time the control signal CNTL input from the terminal 12 changes, the operation mode setting circuit 20D sets the operation mode in accordance with a predetermined order and outputs the set operation mode to the decoder 22.
[0106]
Other configurations of semiconductor integrated circuit 10D are the same as those of semiconductor integrated circuit 10 according to the first embodiment, and therefore description thereof will not be repeated.
[0107]
FIG. 12 is a transition diagram showing an example of a transition state of the operation mode in the semiconductor integrated circuit 10D according to the fourth embodiment.
[0108]
Referring to FIG. 12, when the reset state is released in operation mode setting circuit 20D, semiconductor integrated circuit 10D shifts to the normal operation mode if control signal CNTL is negated. On the other hand, at the time of reset release, if the control signal CNTL is asserted, the operation mode 1 is set. Next, the operation mode set value is incremented by one in synchronization with the rising edge of the control signal CNTL, and the operation mode 2 is set. Thereafter, each time the control signal CNTL rises, the operation mode set value is incremented by one. When the control signal CNTL changes after the operation mode m is set, the operation mode 1 is set again, and thereafter, the operation mode transits cyclically.
[0109]
In the example described above, the operation mode is incremented by one. However, the operation mode may be changed in another predetermined order.
[0110]
FIG. 13 is a functional block diagram for functionally explaining operation mode setting circuit 20D in semiconductor integrated circuit 10D according to the fourth embodiment.
[0111]
Referring to FIG. 13, operation mode setting circuit 20D includes a next operation mode setting circuit 232 and a flip-flop 234. Next operation mode setting circuit 232 receives control signal CNTL, reset signal RESET, and operation mode setting signal SET <0: n−1> output from flip-flop 234 to decoder 22, and receives a rising edge of control signal CNTL. The operation mode is changed according to a predetermined order in synchronization with the operation mode, and the operation mode set value after the change is output to the flip-flop 234. When the reset signal RESET is asserted, the next operation mode setting circuit 232 sets the operation mode to a predetermined initial operation mode.
[0112]
The flip-flop 234 resets the internal state when the reset signal RESET is asserted. After the reset signal RESET is negated, the flip-flop 234 fetches and latches the operation mode setting value output from the next operation mode setting circuit 232 in response to the rise of the control signal CNTL, and outputs it to the decoder 22. Then, unless the rising edge of the control signal CNTL is detected, the acquired operation mode setting value is held.
[0113]
On the other hand, when the reset signal RESET is negated and the control signal CNTL is not asserted, the flip-flop 234 outputs the reset value 0 to the decoder 22. That is, the operation mode of the semiconductor integrated circuit 10D is set to the normal operation mode.
[0114]
FIG. 14 is an operation waveform diagram of each signal when the test mode is set in the semiconductor integrated circuit 10D according to the fourth embodiment. In this operation waveform diagram, a case where the operation mode transits in the order shown in FIG. 12 will be described.
[0115]
Referring to FIG. 14, when reset signal RESET is asserted at time T1, next operation mode setting circuit 232 sets the operation mode setting value to "1" as an initial state of the operation mode. Further, the flip-flop 234 resets the internal state. Further, before the reset signal RESET is negated at the time T2, the control signal CNTL is asserted.
[0116]
After the reset signal RESET is negated at time T2, the control signal CNTL falls once at time T3 and then rises at time T4, the next operation mode setting circuit 232 changes the operation mode setting value to " Transition from "1" to "2". At that timing, the flip-flop 234 captures and latches the post-transition operation mode output from the next operation mode setting circuit 232, and outputs the captured operation mode setting value to the decoder 22.
[0117]
Next, at time T5, control signal CNTL once again falls, and at time T6, when control signal CNTL rises, next operation mode setting circuit 232 changes the operation mode from "2" to "3" at that timing, and , The flip-flop 234 takes in the operation mode setting value “3” after the transition from the next operation mode setting circuit 232, latches it, and outputs it to the decoder 22.
[0118]
In this way, the operation mode sequentially transitions in a predetermined order according to the change of the control signal CNTL.
[0119]
As described above, according to the semiconductor integrated circuit 10D of the fourth embodiment, the operation mode is changed according to the change of the control signal CNTL, so that the same effect as that of the first embodiment can be obtained, and The operation mode can be sequentially set only by changing the control signal CNTL set from the above into a pulse shape.
[0120]
[Embodiment 5]
In the first and second embodiments, the external clock CLK changes, the control signal CNTL is taken in at that timing, and the operation mode is set. In the third embodiment, the operation mode setting value is fetched from the input / output terminal 18 at the timing when the external clock CLK or the control signal CNTL changes, and the operation mode is set. Further, in the fourth embodiment, the operation mode transits at the timing when the control signal CNTL changes, and the operation mode is set.
[0121]
The semiconductor integrated circuit according to the fifth embodiment operates in the DC test mode when the operation mode setting circuit does not change the external clock CLK or the control signal CNTL for giving a signal fetch timing after the reset state is released. Here, the DC test mode is a test mode for measuring a DC characteristic of a pad of each terminal of the semiconductor integrated circuit, and measures a voltage output characteristic, a leak current, and the like of the pad.
[0122]
The semiconductor integrated circuit 10E according to the fifth embodiment has an operation mode setting circuit 20E instead of the operation mode setting circuit 20 in the configuration of the semiconductor integrated circuit 10 according to the first embodiment. Other configurations of semiconductor integrated circuit 10E are the same as those of semiconductor integrated circuit 10 according to the first embodiment, and therefore description thereof will not be repeated.
[0123]
FIG. 15 is a functional block diagram for functionally explaining operation mode setting circuit 20E in semiconductor integrated circuit 10E according to the fifth embodiment.
[0124]
Referring to FIG. 15, operation mode setting circuit 20E includes an operation mode setting unit 212 and a selector 214. The operation mode setting unit 212 has an operation mode setting function of the operation mode setting circuit 20 in the semiconductor integrated circuit 10 according to the first embodiment. Further, when a reset operation is performed by a reset signal RESET, the operation mode setting value “m + 1” is set. Is set internally as the default. The operation mode setting value “m + 1” corresponds to the DC test mode.
[0125]
The selector 214 receives the control signal CNTL, and outputs the operation mode setting value set by the operation mode setting unit 212 to the decoder 22 when the control signal CNTL is asserted. On the other hand, when the control signal CNTL is negated, the selector 214 outputs a normal operation mode setting value previously provided as an internal constant to the decoder 22.
[0126]
In the operation mode setting circuit 20E, when the reset signal RESET is asserted, the operation mode setting unit 212 resets the internal state and internally sets the operation mode setting value “m + 1” as a default. When the reset signal RESET is negated and the reset state is released in the operation mode setting unit 212, if the control signal CNTL is asserted, the selector 214 switches the DC test mode set by the operation mode setting unit 212. The operation mode setting value “m + 1” shown is output to the decoder 22.
[0127]
On the other hand, when the reset signal RESET is negated and the reset state is released in the operation mode setting unit 212, and the control signal CNTL is not asserted, the selector 214 outputs the normal operation mode setting value which is previously set as an internal constant to the decoder 22. Output to
[0128]
In any case, after the reset signal RESET is negated, the external clock CLK does not change, and a DC test is performed in the test mode.
[0129]
Note that the operation mode setting unit 212 may have the operation mode setting circuits 20A and 20D provided with the above-described default setting function, corresponding to the second and fourth embodiments.
[0130]
Similarly, in the semiconductor integrated circuit 10B according to the third embodiment, the operation mode setting circuits 20B and 20C can also have the above-described default setting function.
[0131]
As described above, according to the semiconductor integrated circuit 10E of the fifth embodiment, when the operation mode setting circuit 20E is reset, the operation mode setting value corresponding to the DC test mode is set as a default, so that after reset is released. It is possible to operate in the DC test mode without changing the external clock CLK for taking in the signal for setting the operation mode or the control signal CNTL.
[0132]
Embodiment 6
In the semiconductor integrated circuit according to the sixth embodiment, after the operation mode is set, the set operation mode set value is output to the outside. Thus, the set operation mode can be confirmed.
[0133]
Semiconductor integrated circuit 10F according to the sixth embodiment has an operation mode setting circuit 20F instead of operation mode setting circuit 20 in the configuration of semiconductor integrated circuit 10 according to the first embodiment. Other configurations of semiconductor integrated circuit 10F are the same as those of semiconductor integrated circuit 10 according to the first embodiment, and therefore description thereof will not be repeated.
[0134]
FIG. 16 is a functional block diagram for functionally explaining operation mode setting circuit 20F in semiconductor integrated circuit 10F according to the sixth embodiment.
[0135]
Referring to FIG. 16, operation mode setting circuit 20F includes an operation mode setting unit 222, a control circuit 224, an operation mode output circuit 226, and a buffer 228.
[0136]
The operation mode setting unit 222 is an operation mode setting circuit 20 in the semiconductor integrated circuit 10 according to the first embodiment, and sets an operation mode in n cycles after the reset signal RESET is negated, and sets the set operation mode. Output to the decoder 22.
[0137]
The operation mode output circuit 226 receives the operation mode setting value set by the operation mode setting unit 222, and responds to a command received from the control circuit 224 in n cycles after the operation mode is set by the operation mode setting unit 222. , And outputs the operation mode setting value to the buffer 228 as serial data.
[0138]
The control circuit 224 receives the reset signal RESET and the external clock CLK, and sets the operation mode from the operation mode output circuit 226 to the terminal 12 via the buffer 228 in n cycles after the operation mode is set by the operation mode setting unit 222. The operation mode output circuit 226 and the buffer 228 are controlled so that a value is output.
[0139]
The buffer 228 outputs the operation mode output from the operation mode output circuit 226 to the terminal 12 in response to a command from the control circuit 224.
[0140]
In FIG. 16, the control signal CNTL is not input to the control circuit 224, and after the reset signal RESET is negated, the control circuit 224 sets the operation mode after setting the operation mode regardless of the state of the control signal CNTL. An output operation is performed. A control signal CNTL is input to the control circuit 224, and only when the control signal CNTL is asserted when the reset signal RESET is negated, the output operation in the operation mode is performed thereafter. Is also good. That is, in the normal operation mode, the operation mode setting value may not be checked, and the operation mode setting value may be checked only in the test mode.
[0141]
FIG. 17 is an operation waveform diagram of each signal when the test mode is set in semiconductor integrated circuit 10F according to the sixth embodiment.
[0142]
Referring to FIG. 17, at time T1, reset signal RESET is asserted, and the internal state of operation mode setting section 222 is reset. Before the reset signal RESET is negated at the time T2, the control signal CNTL is asserted. When the reset signal RESET is negated at time T2, since the control signal CNTL is asserted, the operation mode setting unit 222 recognizes that the operation mode is the test mode, and is input from the terminal 12 in n cycles until time T3. The operation mode is set based on the control signal CNTL.
[0143]
On the other hand, control circuit 224 receives reset signal RESET and external clock CLK, and activates operation mode output circuit 226 and buffer 228 at time T3, which is n cycles after reset signal RESET is negated. In response to a command from the control circuit 224, the operation mode output circuit 226 converts the operation mode setting value, which is the parallel data output from the operation mode setting unit 222, into serial data in n cycles from time T3 to T4. The buffer 228 outputs the operation mode setting value to the terminal 12.
[0144]
The operation mode setting unit 222 may be an operation mode setting circuit 20A to 20E corresponding to the second to fifth embodiments, and in the case of the third embodiment, the operation mode setting unit 222 according to the sixth embodiment. Has a configuration corresponding to the semiconductor integrated circuit 10B shown in FIG.
[0145]
As described above, according to the semiconductor integrated circuit 10F according to the sixth embodiment, the set operation mode can be confirmed. Therefore, as in the first to fifth embodiments, the operation mode for the test is set. The number of dedicated test terminals for inputting signals is greatly reduced, and it is possible to confirm outside the semiconductor integrated circuit whether the set operation mode is a desired operation mode.
[0146]
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor integrated circuit according to a first embodiment.
FIG. 2 is a functional block diagram for functionally explaining an operation mode setting circuit in the semiconductor integrated circuit according to the first embodiment;
FIG. 3 is an operation waveform diagram of each signal when a normal operation mode is set in the semiconductor integrated circuit according to the first embodiment;
FIG. 4 is an operation waveform diagram of each signal when a test mode is set in the semiconductor integrated circuit according to the first embodiment;
FIG. 5 is a functional block diagram for functionally explaining an operation mode setting circuit in a semiconductor integrated circuit according to a second embodiment;
FIG. 6 is an operation waveform diagram of each signal when a test mode is set in the semiconductor integrated circuit according to the second embodiment;
FIG. 7 is a schematic block diagram showing an overall configuration of a semiconductor integrated circuit according to a third embodiment.
FIG. 8 is a functional block diagram for functionally explaining an operation mode setting circuit in a semiconductor integrated circuit according to a third embodiment;
FIG. 9 is an operation waveform diagram of each signal when a test mode is set in the semiconductor integrated circuit according to the third embodiment;
FIG. 10 is a functional block diagram for functionally explaining another operation mode setting circuit in the semiconductor integrated circuit according to the third embodiment;
FIG. 11 is an operation waveform diagram of each signal when the operation mode setting circuit shown in FIG. 10 is used in the semiconductor integrated circuit according to the third embodiment;
FIG. 12 is a transition diagram showing an example of a transition state of an operation mode in the semiconductor integrated circuit according to the fourth embodiment;
FIG. 13 is a functional block diagram for functionally explaining an operation mode setting circuit in a semiconductor integrated circuit according to a fourth embodiment.
FIG. 14 is an operation waveform diagram of each signal when a test mode is set in the semiconductor integrated circuit according to the fourth embodiment.
FIG. 15 is a functional block diagram for functionally explaining an operation mode setting circuit in a semiconductor integrated circuit according to a fifth embodiment.
FIG. 16 is a functional block diagram for functionally explaining an operation mode setting circuit in a semiconductor integrated circuit according to a sixth embodiment.
FIG. 17 is an operation waveform diagram of each signal when a test mode is set in the semiconductor integrated circuit according to the sixth embodiment.
FIG. 18 is a schematic block diagram showing an overall configuration of a conventional semiconductor integrated circuit including a plurality of functional blocks and capable of performing a test for each functional block.
19 is a diagram showing a correspondence relationship between set values of operation modes and contents of the operation modes in the semiconductor integrated circuit shown in FIG. 18;
FIG. 20 is a functional block diagram for functionally explaining the selector shown in FIG. 18;
[Explanation of symbols]
10, 10A, 10B, 10D to 10F semiconductor integrated circuit, 12, 14, 16 terminals, 18, 181, 182 input / output terminals, 20, 20A to 20F operation mode setting circuit, 22 decoder, 24, 214 selector, 26 bus, 112 operation mode setting terminal, 201 counter, 202 shift register, 204 test mode detection circuit, 206, 208, 234 flip-flop, 212, 222 operation mode setting section, 224 control circuit, 226 operation mode output circuit, 228 buffer, 232 order Operation mode setting circuit, 241 circuit, 243, 245 internal selector, 247 output buffer, 249 input buffer, 251 to 255 signal line, G1 to Gm AND gate, FB1 to FBm functional block.

Claims (12)

A semiconductor integrated circuit having a plurality of operation modes,
An operation mode setting circuit that sets any one of the plurality of operation modes based on a control signal input from a predetermined terminal;
An internal circuit that operates in the operation mode set by the operation mode setting circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said predetermined terminal is constituted by one terminal. Each of the plurality of operation modes is each of at least one test mode and any of a normal operation mode;
The operation mode setting circuit,
When the control signal is at the first logic level at a predetermined timing, one of the at least one test mode is set based on the control signal input thereafter,
3. The semiconductor integrated circuit according to claim 1, wherein said normal operation mode is set when said control signal is at a second logic level at said predetermined timing. The operation mode setting circuit receives an external clock, and when the control signal is at the first logic level at the predetermined timing, the control signal input thereafter is during the period in which the control signal is at the first logic level. 4. The semiconductor integrated circuit according to claim 3, wherein the number of cycles of the external clock is counted, and one of the at least one test mode is set based on the count value. The control signal includes serial data including a code representing the operation mode,
When the control signal is at the first logic level at the predetermined timing, the operation mode setting circuit fetches the serial data input thereafter, and performs the at least one test based on the fetched serial data. 4. The semiconductor integrated circuit according to claim 3, wherein one of the modes is set. The operation mode setting circuit, when the control signal is at the first logic level at the predetermined timing, based on data input from at least one terminal used during normal operation of the semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3, wherein any one of one test mode is set. When the control signal is at the first logic level at the predetermined timing, the operation mode setting circuit is configured to synchronize at least one of the at least one signal used during normal operation of the semiconductor integrated circuit in synchronization with a subsequent change in the control signal. 4. The semiconductor integrated circuit according to claim 3, wherein data is taken from one of the terminals, and one of the at least one test mode is set based on the taken data. The operation mode setting circuit, when the control signal is at the first logic level at the predetermined timing, in synchronization with a subsequent change of the control signal, from the operation mode set at the time of the change, 4. The semiconductor integrated circuit according to claim 3, wherein the setting of the operation mode is shifted to any one of at least one test mode in a predetermined order. 9. The semiconductor integrated circuit according to claim 3, wherein the predetermined timing is a timing at which a reset operation is canceled in the operation mode setting circuit. The semiconductor integrated circuit according to claim 9, wherein the operation mode setting circuit sets a predetermined operation mode at the time of the reset operation. The predetermined operation mode is a DC test mode,
11. The semiconductor integrated circuit according to claim 10, wherein the operation mode setting circuit receives an external clock and holds the setting of the DC test mode when the external clock is not input after the reset operation is released. The semiconductor integrated circuit according to claim 3, wherein the operation mode setting circuit sets the operation mode based on the control signal and then outputs the set operation mode to the outside. circuit.

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