CN206162231U - Double - circuit voltage buffer circuit - Google Patents
Double - circuit voltage buffer circuit Download PDFInfo
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- CN206162231U CN206162231U CN201621123055.2U CN201621123055U CN206162231U CN 206162231 U CN206162231 U CN 206162231U CN 201621123055 U CN201621123055 U CN 201621123055U CN 206162231 U CN206162231 U CN 206162231U
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Abstract
The utility model discloses a double - circuit voltage buffer circuit, it includes high voltage signal input terminal, high voltage output end, low voltage signal input terminal, low voltage output end, an operational amplifier, the 2nd operational amplifier, a MOS pipe, the 2nd MOS pipe, first electric current source, current reuse branch road, the utility model discloses an operational amplifier high -gain, the negative feedback loop that MOS pipe constitutes has guaranteed the voltage unanimity of voltage after the buffering and input. The change of any output all can be amplified by negative feedback loop, and consequently the change of output is very little, and the impedance of output is very little, has the circuit design of simplification, cost -effective advantage. The utility model discloses a MOS pipe constitutes the current reuse branch road, realizes the multiplexing of output stage electric current to the consumption has been reduced. The utility model relates to a double - circuit voltage buffer circuit extensively is applicable to integrated circuit technical field.
Description
Technical field
The utility model is related to technical field of integrated circuits, more particularly to a kind of two-way voltage buffer circuit.
Background technology
It is frequently necessary to buffer two paths of signals in electronic circuit such as analog to digital conversion circuit, improves the driving force of output, it is existing
In technology, need to use special buffer chip, when user's request is relatively simple, easily cause the wasting of resources.
The content of the invention
In order to solve above-mentioned technical problem, the purpose of this utility model is to provide a kind of two-way voltage buffer circuit.
The technical scheme that the utility model is adopted is：A kind of two-way voltage buffer circuit, it includes that high voltage signal is defeated
Enter end, high-voltage output terminal, low voltage signal input, low-voltage output end, the first operational amplifier, the second operation amplifier
Device, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first current source, current multiplexing branch road, the positive input terminal of first operational amplifier with
High voltage signal input connection, its output end is connected with the grid of first metal-oxide-semiconductor, its negative input end and described the
The source electrode connection of one metal-oxide-semiconductor, the source electrode of first metal-oxide-semiconductor is connected with the high-voltage output terminal；Second operation amplifier
The positive input terminal of device is connected with the low voltage signal input, and its output end is connected with the grid of second metal-oxide-semiconductor, and it is born
Input is connected with the source electrode of second metal-oxide-semiconductor, and the drain electrode of second metal-oxide-semiconductor is connected with the drain electrode of first metal-oxide-semiconductor,
The source electrode of second metal-oxide-semiconductor is connected with the negative pole of first current source, and the positive pole of first current source is connected to ground, institute
The source electrode for stating the second metal-oxide-semiconductor is connected with the low-voltage output end；The current multiplexing branch road respectively with first metal-oxide-semiconductor
The drain electrode connection of source electrode and second metal-oxide-semiconductor, the multiplex circuit provides power supply for the first metal-oxide-semiconductor.
Further, the current multiplexing branch road includes the 3rd metal-oxide-semiconductor and the first power supply, the grid point of the 3rd metal-oxide-semiconductor
It is not connected with the drain electrode of first metal-oxide-semiconductor and the source electrode of the second metal-oxide-semiconductor, its drain electrode connects with the source electrode of first metal-oxide-semiconductor
Connect, its source electrode is connected with first power supply.
Further, first metal-oxide-semiconductor is PMOS, and second metal-oxide-semiconductor is NMOS tube.
Further, the 3rd metal-oxide-semiconductor is PMOS.
Further, the current multiplexing branch road includes second source, the 3rd power supply and the second current source, and described second is electric
Source is connected with the negative pole of the second current source, and the positive pole of second current source is connected with the source electrode of first metal-oxide-semiconductor, and described
Three current sources are connected with the drain electrode of second metal-oxide-semiconductor.
Further, the second source and the 3rd power supply are same power supply.
The beneficial effects of the utility model are：The utility model is by operational amplifier high-gain, and it is negative anti-that metal-oxide-semiconductor is constituted
It is fed back to road and ensure that the voltage after buffering is consistent with the voltage of input.The change of any output all can be amplified by negative feedback loop,
Therefore what is exported varies less, and the impedance of output is very little, with simplified circuit design, cost-effective advantage.
The utility model constitutes current multiplexing branch road by metal-oxide-semiconductor, the multiplexing of output stage electric current is realized, so as to reduce work(
Consumption.
Description of the drawings
Specific embodiment of the present utility model is described further below in conjunction with the accompanying drawings：
Fig. 1 is the circuit theory diagrams of the specific embodiment of the utility model one；
Fig. 2 is the circuit theory diagrams of the utility model another specific embodiment.
Specific embodiment
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase
Mutually combination.
Embodiment 1
As shown in figure 1, a kind of two-way voltage buffer circuit, it includes high voltage signal input VREFP, high voltage output
End VOUTP, low voltage signal input VREFN, low-voltage output end VOUTN, the first operational amplifier OP1, the second computing are put
Big device OP2, the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the first current source I1, current multiplexing branch road, first operational amplifier
The positive input terminal of OP1 is connected with the high voltage signal input VREFP, the grid of its output end and the first metal-oxide-semiconductor M1
Connection, its negative input end is connected with the source electrode of the first metal-oxide-semiconductor M1, source electrode and the high voltage of the first metal-oxide-semiconductor M1
Output end VOUTP connects, and the positive input terminal of the second operational amplifier OP2 connects with the low voltage signal input VREFN
Connect, its output end is connected with the grid of the second metal-oxide-semiconductor M2, its negative input end is connected with the source electrode of the second metal-oxide-semiconductor M2,
The drain electrode of the second metal-oxide-semiconductor M2 is connected with the drain electrode of the first metal-oxide-semiconductor M1, the source electrode of the second metal-oxide-semiconductor M2 with it is described
The negative pole connection of the first current source I1, the positive pole of the first current source I1 is connected to ground, the source electrode of the second metal-oxide-semiconductor M2 with
The low-voltage output end VOUTN connections；The current multiplexing branch road respectively with the source electrode of the first metal-oxide-semiconductor M1 and described
The drain electrode connection of the second metal-oxide-semiconductor M2, the multiplex circuit provides power supply for the first metal-oxide-semiconductor.
Preferably, the current multiplexing branch road includes the 3rd metal-oxide-semiconductor M3 and the first power supply VAA1, the 3rd metal-oxide-semiconductor M3
Grid be connected with the drain electrode of the first metal-oxide-semiconductor M1 and the source electrode of the second metal-oxide-semiconductor M2 respectively, its drain electrode and described first
The source electrode connection of metal-oxide-semiconductor M1, its source electrode is connected with the first power supply VAA1, drain electrode and the 2nd MOS of the first metal-oxide-semiconductor M1
The drain electrode connection of pipe M2.
In the present embodiment first metal-oxide-semiconductor be PMOS, second metal-oxide-semiconductor be NMOS tube, the 3rd metal-oxide-semiconductor
For PMOS.The multiplexing of the circuit realiration output stage electric current, so as to reduce power consumption.The grid of wherein the 3rd metal-oxide-semiconductor M3 connects
To high-voltage output terminal VOUTP, the source class of the 3rd metal-oxide-semiconductor M3 is connected to the first power supply VAA1, and drain is connected to the firstth metal-oxide-semiconductor M1's
Source class simultaneously feeds back to the first operational amplifier OP1.Other backfeed loop detects the value of high-voltage output terminal VOUTP, feeds back to
The negative terminal of the first operational amplifier OP1, forms negative feedback loop.Due to the high-gain of amplifier, between two inputs of amplifier
Operation principle, therefore the voltage high-voltage output terminal VOUTP for feeding back to and the reference voltage of input can be explained with " empty short "
High voltage signal input VREFP must be closely.Therefore the negative feedback loop ensure that the voltage after buffering and input
Voltage is consistent.The guarantee of work low-voltage output end OUTN of the second same operational amplifier OP2 and the reference voltage electricity of input
High voltage signal input VREFP is consistent for pressure.Because the grid of the 3rd metal-oxide-semiconductor M3 is connected to high-voltage output terminal VOUTP, the 3rd
The electric current automatic biasing of metal-oxide-semiconductor M3 to and the second metal-oxide-semiconductor M2, the first metal-oxide-semiconductor M1, the first current source I1 are consistent.
Embodiment 2
The current multiplexing branch road includes second source VAA2, the 3rd power supply VAA3 and the second current source I2, described the
Two power supply VAA2 are connected with the negative pole of the second current source VAA3, the positive pole of the second current source VAA2 and first metal-oxide-semiconductor
The source electrode connection of M1, the 3rd current source VAA3 is connected with the drain electrode of second metal-oxide-semiconductor.
In the present embodiment the first metal-oxide-semiconductor M1 is PMOS, and the second metal-oxide-semiconductor M2 is NMOS tube, and high voltage is believed
Number input VREFP drives the grid of the first metal-oxide-semiconductor M1, the M1 of the first metal-oxide-semiconductor by the first operational amplifier OP1 anodes
The high-voltage output terminal VOUTP after buffering is output as, the value of backfeed loop detection high-voltage output terminal VOUTP in addition, instead
Feed the negative terminal of the first operational amplifier OP1, form negative feedback loop.Due to the high-gain of amplifier, two inputs of amplifier
Between operation principle, therefore the voltage of the high-voltage output terminal VOUTP for feeding back to and the ginseng of input can be explained with " empty short "
Examining voltage high voltage signal input VREFP must be closely.Therefore the negative feedback loop ensure that the voltage after buffering and
The voltage of input is consistent.The change of any output all can be amplified by negative feedback loop, thus export vary less, even if output
Curent change is very big, and the impedance for exporting in other words is very little.The specific derivation of equation can show that the impedance of output is feedback
The inverse of the mutual conductance of the first metal-oxide-semiconductor M1 of output is multiplied by the gain of loop.Typically below ten ohm.
It is more than that preferable enforcement of the present utility model is illustrated, but the utility model is created and is not limited to institute
State embodiment, those of ordinary skill in the art can also make a variety of etc. on the premise of without prejudice to the utility model spirit
With deformation or replacement, the deformation or replacement of these equivalents are all contained in the application claim limited range.
Claims (6)
1. a kind of two-way voltage buffer circuit, it is characterised in that：It includes high voltage signal input, high-voltage output terminal, low
Voltage signal inputs, low-voltage output end, the first operational amplifier, the second operational amplifier, the first metal-oxide-semiconductor, the 2nd MOS
Pipe, the first current source, current multiplexing branch road；
The positive input terminal of first operational amplifier is connected with the high voltage signal input, its output end and described first
The grid connection of metal-oxide-semiconductor, its negative input end is connected with the source electrode of first metal-oxide-semiconductor, the source electrode of first metal-oxide-semiconductor with it is described
High-voltage output terminal connects；
The positive input terminal of second operational amplifier is connected with the low voltage signal input, its output end and described second
The grid connection of metal-oxide-semiconductor, its negative input end is connected with the source electrode of second metal-oxide-semiconductor, the drain electrode of second metal-oxide-semiconductor with it is described
The drain electrode connection of the first metal-oxide-semiconductor, the source electrode of second metal-oxide-semiconductor is connected with the negative pole of first current source, and described first is electric
The positive pole in stream source is connected to ground, and the source electrode of second metal-oxide-semiconductor is connected with the low-voltage output end；
The current multiplexing branch road is connected respectively with the source electrode of first metal-oxide-semiconductor and the drain electrode of second metal-oxide-semiconductor, described
Multiplex circuit provides power supply for the first metal-oxide-semiconductor.
2. two-way voltage buffer circuit according to claim 1, it is characterised in that：The current multiplexing branch road includes the 3rd
Metal-oxide-semiconductor and the first power supply, the drain electrode respectively with first metal-oxide-semiconductor of the grid of the 3rd metal-oxide-semiconductor and the source of the second metal-oxide-semiconductor
Pole connects, and its drain electrode is connected with the source electrode of first metal-oxide-semiconductor, and its source electrode is connected with first power supply.
3. two-way voltage buffer circuit according to claim 1, it is characterised in that：First metal-oxide-semiconductor be PMOS, institute
The second metal-oxide-semiconductor is stated for NMOS tube.
4. the two-way voltage buffer circuit according to any one of Claims 2 or 3, it is characterised in that：3rd metal-oxide-semiconductor is
PMOS.
5. two-way voltage buffer circuit according to claim 1, it is characterised in that：The current multiplexing branch road includes second
Power supply, the 3rd power supply and the second current source, the second source is connected with the negative pole of the second current source, second current source
Positive pole be connected with the source electrode of first metal-oxide-semiconductor, the 3rd current source is connected with the drain electrode of second metal-oxide-semiconductor.
6. two-way voltage buffer circuit according to claim 5, it is characterised in that：The second source is electric with the described 3rd
Source is same power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621123055.2U CN206162231U (en) | 2016-10-14 | 2016-10-14 | Double - circuit voltage buffer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621123055.2U CN206162231U (en) | 2016-10-14 | 2016-10-14 | Double - circuit voltage buffer circuit |
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| Publication Number | Publication Date |
|---|---|
| CN206162231U true CN206162231U (en) | 2017-05-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621123055.2U Active CN206162231U (en) | 2016-10-14 | 2016-10-14 | Double - circuit voltage buffer circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106325351A (en) * | 2016-10-14 | 2017-01-11 | 广州昌钰行信息科技有限公司 | Two-channel voltage buffer circuit |
| CN110262589A (en) * | 2019-05-23 | 2019-09-20 | 南京牧镭激光科技有限公司 | A kind of TEC temperature control driving circuit and its control strategy |
-
2016
- 2016-10-14 CN CN201621123055.2U patent/CN206162231U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106325351A (en) * | 2016-10-14 | 2017-01-11 | 广州昌钰行信息科技有限公司 | Two-channel voltage buffer circuit |
| CN110262589A (en) * | 2019-05-23 | 2019-09-20 | 南京牧镭激光科技有限公司 | A kind of TEC temperature control driving circuit and its control strategy |
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