CN103944569B - A kind of analog-digital converter - Google Patents
A kind of analog-digital converter Download PDFInfo
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- CN103944569B CN103944569B CN201310019308.6A CN201310019308A CN103944569B CN 103944569 B CN103944569 B CN 103944569B CN 201310019308 A CN201310019308 A CN 201310019308A CN 103944569 B CN103944569 B CN 103944569B
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Abstract
The present invention provides a kind of analog-digital converter, including：Input channel, for receiving analog input signal；The first order circuit being connected with the input channel, for receiving the analog input signal；The second level circuit being connected with the first order circuit, the analog error signal for receiving the first order circuit output, and the analog error signal is converted into data signal output；The first order circuit is additionally operable to receive the output signal selected in the output signal of the second level circuit, and the output signal selected is converted into digital output signal.The solution of the present invention can realize that the precision of analog-digital converter can configure.
Description
Technical field
The present invention relates to circuit field, a kind of modulus is particularly related to（A/D）Converter.
Background technology
Continuing to develop for integrated circuit technique, needs low in many portable sets, Industry Control and wireless communication applications
The chip of power consumption, small area.Low-power consumption reduces the capacity requirement to battery, so that equipment cumulative volume is reduced, small chip face
Product can reduce overhead, further improve portable devices.Analog-digital converter is as chip interface circuit, except meeting work(
Outside the requirement of consumption and area, in some electronic equipments, to realize different functions, generally requiring analog-digital converter has different
Precision.If according to the different analog-digital converter of the integrated multiple precision of system requirements, can not only dramatically increase chip area, together
When low-power consumption application difficult to realize.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of analog-digital converter, it is possible to achieve the precision of analog-digital converter
It is configurable.
In order to solve the above technical problems, embodiments of the invention provide a kind of analog-digital converter, including：
Input channel, for receiving analog input signal；
The first order circuit being connected with the input channel, for receiving the analog input signal；
The second level circuit being connected with the first order circuit, the simulation error for receiving the first order circuit output
Signal, and the analog error signal is converted into data signal output；
The first order circuit is additionally operable to receive the output signal selected in the output signal of the second level circuit,
And the output signal selected is converted into digital output signal.
Wherein, above-mentioned analog-digital converter also includes：
The first switch between the input channel and the first order circuit is connected to, for the simulation input to be believed
Number or the output signal of the second level circuit input the first order circuit.
Wherein, analog-digital converter also includes：
The accuracy selection circuit of the first switch is controlled, for controlling the first order circuit and the second level circuit
The number of times of circulation.
Wherein, the first order circuit includes：
The first sub-adc converter being connected with the first switch, it is used in being circulated in first time, the simulation is defeated
Enter signal slightly to quantify, and provide the output signal of the first sub-adc converter；
The second switch between the first switch and first sub-adc converter is connected to, for gating described
One sub-adc converter；
The second sub-adc converter being connected with the first switch, for the analog input signal and described second
The output signal selected in the output signal of level circuit is slightly quantified, and provides second sub-adc converter
Output signal；
The 3rd switch between the first switch and second sub-adc converter is connected to, for gating described
Two sub-adc converters；
The first subnumber mould that output with first sub-adc converter and second sub-adc converter is connected turns
Parallel operation, for the data signal of first sub-adc converter, second sub-adc converter output to be converted into simulation
Signal；
First be connected with the sampling hold circuit of the input channel and the first subnumber weighted-voltage D/A converter output is accurate
Multiply 2 circuits, for the output of the analog input signal and the first subnumber weighted-voltage D/A converter that export the sampling hold circuit
Signal makes the difference, and amplifies 2 times.
Wherein, the second level circuit includes：
The 3rd sub-adc converter being connected with the output of the first order circuit, for by the defeated of the first order circuit
Go out signal slightly to quantify, and provide the output signal of the 3rd sub-adc converter；
The 4th switch between the first order circuit and the 3rd sub-adc converter is connected to, it is described for gating
3rd sub-adc converter；
The 4th sub-adc converter being connected with the output of the first order circuit, for by the defeated of the first order circuit
Go out signal slightly to quantify；
The 5th switch between the output of the first order circuit and the 4th sub-adc converter is connected to, for selecting
Lead to the 4th sub-adc converter；
The second subnumber weighted-voltage D/A converter that output with the 3rd sub-adc converter is connected, for by the 3rd submodule
The data signal of number converter output is converted to analog signal；
Second be connected with the sampling hold circuit of the input channel and the second subnumber weighted-voltage D/A converter output is accurate
Multiply 2 circuits, for the error signal of the first order circuit output and the output signal of the second subnumber weighted-voltage D/A converter to be done
Difference, and amplify 2 times.
Wherein, the 4th sub-adc converter is 1 analog-digital converter.
Wherein, described first accurate multiply 2 circuits and second and accurately multiplies 2 circuits by Full differential operational amplifier and capacitance group
Into.
Wherein, above-mentioned analog-digital converter also includes：
The bias current generating circuit being connected with the first order circuit and the second level circuit, for described first
Level circuit and the second level circuit are powered.
Wherein, the bias current generating circuit includes：
Amplifier and the first metal-oxide-semiconductor, the feedback control loop of load resistance formation；Wherein, the output connection institute of the amplifier
The grid of the first metal-oxide-semiconductor, one end of the drain electrode connection load resistance of first metal-oxide-semiconductor are stated, and connects the amplifier
Inverting input, the load resistance the other end ground connection；
The current mirroring circuit that first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor are constituted；Wherein, institute
The grid for stating the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is connected with each other, and the grid with first metal-oxide-semiconductor
Connection, three branch roads are mirrored to by the constant current of the first metal-oxide-semiconductor branch road in proportion；
The 5th metal-oxide-semiconductor being connected with second metal-oxide-semiconductor；
The 6th metal-oxide-semiconductor being connected with the 3rd metal-oxide-semiconductor；
The 7th metal-oxide-semiconductor being connected with the 4th metal-oxide-semiconductor；
The 8th metal-oxide-semiconductor being connected with the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor and the 7th metal-oxide-semiconductor；
The 9th metal-oxide-semiconductor being connected with the 8th metal-oxide-semiconductor；
Wherein, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor and the 7th metal-oxide-semiconductor as three articles of branch currents of switch controlled whether
Flow into the 8th metal-oxide-semiconductor connected by diode, then the electric current being made up of the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor
There is provided to the Full differential operational amplifier by electric current extraction for mirror.
Wherein, above-mentioned analog-digital converter also includes：
The mode selection circuit being connected with the bias current generating circuit, for according to whether in mode of operation, choosing
Select whether the bias current generating circuit works；
Wherein, non-operating mode has three kinds, respectively standby, sleep and shutdown mode；
When in mode of operation, the mode selection circuit sets the bias current according to the difference of clock frequency
The size of the bias current of generation circuit.
Wherein, above-mentioned analog-digital converter also includes：
The clock driver circuit being connected with the first order circuit and the second level circuit, for producing the first order
Required non-overlapping clock during the bottomplanksampling of circuit and the second level circuit.
Wherein, above-mentioned analog-digital converter also includes：
The redundancy calibration circuit being connected with the first order circuit and the second level circuit, for first order electricity
The data signal of road and the second level circuit output is calibrated, the signal after being calibrated.
The above-mentioned technical proposal of the present invention has the beneficial effect that：
In such scheme, obtained after signal slightly can be quantified by the two stage cycle level of first order circuit and second level circuit
High accuracy output, and the configurable of precision can be realized.
Brief description of the drawings
Fig. 1 is modulus of the invention（A/D）The schematic block diagram of converter；
Fig. 2 is the schematic block diagram for realizing that precision is configurable of the invention；
Fig. 3 is the structural representation of Fig. 2 first order circuits；
Fig. 4 is the structural representation of Fig. 2 second level circuit；
Fig. 5 is that programmable offset electric current realizes circuit diagram.
Embodiment
To make the technical problem to be solved in the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing and tool
Body embodiment is described in detail.
As shown in figure 1, The embodiment provides a kind of modulus（A/D）Converter, including：Input channel 101, is used
In reception analog input signal；Wherein, analog input signal one kind is single ended signal, then has 9 optional passages；It is another
Kind be difference form, wherein one as inverting input, other are normal phase input end, then have 8 groups of passages；Arrow table in Fig. 1
Show signal stream, be not only applicable to single ended signal；
The first order circuit 107 being connected with the input channel 101, for receiving the analog input signal；
The second level circuit 108 being connected with the first order circuit 107, is exported for receiving the first order circuit 107
Analog error signal, and by the analog error signal be converted to data signal output；
It is defeated that the first order circuit 107 is additionally operable to receive one selected in the output signal of the second level circuit 108
Go out signal, and the output signal selected is converted into digital output signal.
Wherein, above-mentioned analog-digital converter also includes：Be connected to the input channel 101 and the first order circuit 107 it
Between first switch 106, for the output signal of the analog input signal or the second level circuit 108 to be inputted into institute
State first order circuit 107.
Further, above-mentioned analog-digital converter also includes：The accuracy selection circuit 102 of the first switch 106 is controlled, is used
In the number of times for controlling the first order circuit 107 and the second level circuit 108 circulation.
In the embodiment of the above-mentioned analog-digital converter of the present invention, it can also include：With the first order circuit 107 and institute
The redundancy calibration circuit 110 of the connection of second level circuit 108 is stated, for the first order circuit 107 and the second level circuit
The data signal of 108 outputs is calibrated, the signal after being calibrated.
That is, the control selections of accuracy selection circuit 102 switch 106, determine A/D converter the first order 107 it is defeated
Enter end signal of the reception from passage 101 and still receive the signal after the processing of the second level 108；Accuracy selection 102 can root
The cycle-index of first order circuit 107 and second level circuit 108 is controlled according to required precision, so as to configure precision；Configure precision
Process may be referred to Fig. 2：First order circuit 107 and second level circuit 108 are re-used, and per circulation primary, are re-used once,
And by 2 digit numeric codes of quantization（That is binary system）Export and calibrate circuit 110 to redundancy；Redundancy calibration circuit 110 uses every grade 1.5
The collimation technique of position, obtains the output of 2n；Wherein n is the number of times of circulation；The essence of 6 ~ 12 is for example realized in the present embodiment
Degree is configurable, i.e. corresponding control cycle-index 3 ~ 6 times, during last time circulation, only uses first order circuit 107, and the second level
Circuit 108 is by 1 ADC（Analog-digital converter）202 replace, and 1 ADC202 is in embodiment by a dynamic comparer reality
It is existing.
First order circuit 107 and second level circuit 108 will realize the function of thick quantizer input signal and surplus gain, the
The structure of stage circuit 107 is as shown in Figure 3：
The first order circuit 107 includes：The first sub-adc converter being connected with the first switch 106（ADC）
304, used in being circulated in first time, the analog input signal is slightly quantified, and provide the first sub-adc converter（ADC）
304 output signal；
It is connected to the first switch 106 and first sub-adc converter（ADC）Second switch 302 between 304,
For gating first sub-adc converter（ADC）304；
The second sub-adc converter being connected with the first switch 106（ADC）305, for the simulation input to be believed
Number and the output signal of the second level circuit 108 in an output signal selecting slightly quantified, and provide described
Second sub-adc converter（ADC）305 output signal；
It is connected to the first switch 106 and second sub-adc converter（ADC）The 3rd switch 303 between 305,
For gating second sub-adc converter（ADC）305；
With first sub-adc converter（ADC）304 and second sub-adc converter（ADC）305 output connects
The the first subnumber weighted-voltage D/A converter connect（DAC）306, for by first sub-adc converter（ADC）304th, second submodule
Number converter（ADC）The data signal of 305 outputs is converted to analog signal；
With the sampling hold circuit 301 and the first subnumber weighted-voltage D/A converter of the input channel（DAC）306 output connections
First accurately multiply 2 circuits 307, for the analog input signal and first son for exporting the sampling hold circuit 301
Digital analog converter（DAC）306 output signal makes the difference, and amplifies 2 times.
That is, there is two branch roads after analog signal input channel 101, one passes through SH301（Sampling hold circuit）,
The sub- ADC of another entrance quantifies.Because the input signal of first order circuit 107 has two kinds of forms, single-ended or difference, therefore here
There are two sub- ADC, the first sub-adc converter（ADC）304 and second sub-adc converter（ADC）305；First sub- analog-to-digital conversion
Device（ADC）304 single-ended signals work when inputting, and are controlled by second switch 302；Second sub-adc converter（ADC）305 difference are believed
Number input when work, by the 3rd switch 303 control；The control signal of the switch of second switch 302 and the 3rd 303 is complementary, therefore together
One moment only had a sub- ADC job.2 position digital signal one after sub- ADC quantizations is exported to the redundancy calibration in Fig. 1
110, another is used as the first digital analog converter（DAC）306 control signal；First subnumber weighted-voltage D/A converter（DAC）306 by 2
Digital code changes into analog signal, then is made the difference with the above SH301 input signals kept, eventually passes first and accurately multiplies 2（I.e. ×
2）Circuit 307 amplifies error, then exports to next stage.
As shown in figure 4, in the analog-digital converter embodiment of the present invention, the second level circuit 108 includes：With described
3rd sub-adc converter of the output connection of stage circuit 107（ADC）403, for by the output of the first order circuit 107
Signal slightly quantifies, and provides the 3rd sub-adc converter（ADC）403 output signal；
It is connected to the first order circuit 107 and the 3rd sub-adc converter（ADC）The 4th switch between 403
402, for gating the 3rd sub-adc converter（ADC）403；
The 4th sub-adc converter being connected with the output of the first order circuit 107（ADC）404, for by described
The output signal of stage circuit 107 slightly quantifies；
It is connected to the output of the first order circuit 107 and the 4th sub-adc converter（ADC）The 5th between 404
Switch 401, for gating the 4th sub-adc converter（ADC）404；
With the 3rd sub-adc converter（ADC）Second subnumber weighted-voltage D/A converter of 403 output connection（DAC）405, use
In by the 3rd sub-adc converter（ADC）The data signal of 403 outputs is converted to analog signal；
With the sampling hold circuit 407 and the second subnumber weighted-voltage D/A converter of the input channel（DAC）405 output connections
Second accurately multiply 2 circuits 406, error signal and the second subnumber mould for the first order circuit 107 to be exported turn
Parallel operation（DAC）405 output signal makes the difference, and amplifies 2 times.
Wherein, the 4th sub-adc converter（ADC）For 1 ADC；Described first accurately multiplies 2 circuits 307 and the second essence
Really multiply 2 circuits 406 to constitute by Full differential operational amplifier and electric capacity.
That is, the function of second level circuit 108 is similar to first order circuit 107, with reference to Fig. 4；First order circuit 107
Sole difference between second level circuit 108 is exactly second level circuit without handling single ended signal, therefore is not necessarily to
Use two sub- ADC；Then the only one of which difference subspace ADC403 of second level circuit 108（I.e. above-mentioned 3rd sub- ADC）.3rd submodule
Number converter（ADC）403 are switched 402 control by the 4th be connected with it.In addition when last time is circulated, second level circuit
108 need to export 1 digit numeric code, therefore than adding 1 ADC in first order circuit 107（I.e. above-mentioned 4th sub- ADC404）.1
Controls of the position ADC404 by the 5th switch 401 being connected with it.
In above-described embodiment, sampling hold circuit in first order circuit 107 and second level circuit 108（SH）301st, 407 and
It is accurate multiply 2 circuits 307,406 and be combined together employ bottomplanksampling technology, it is therefore desirable to the clock of non-overlapping.
Therefore, as shown in figure 1, the embodiment of the analog-digital converter of the present invention also includes：With the first order circuit 107 and
The clock driver circuit 109 that the second level circuit 108 is connected, for producing the first order circuit 107 and the second level
Required non-overlapping clock during the bottomplanksampling of circuit 108.
Further, in the embodiment of analog-digital converter of the invention, it can also include：With the first order circuit 107
The bias current generating circuit 104 connected with the second level circuit 108, for the first order circuit 107 and described the
Secondary circuit 108 is powered；Specifically, as shown in figure 5, the bias current generating circuit 104 includes：Amplifier 501 and first
Metal-oxide-semiconductor 502, the feedback control loop of the formation of load resistance 504；Wherein, the output of the amplifier 501 connects first metal-oxide-semiconductor
502 grid, one end of the drain electrode connection load resistance 504 of first metal-oxide-semiconductor 502, and connect the amplifier 501
Inverting input, the load resistance 504 the other end ground connection；First metal-oxide-semiconductor 502, the second metal-oxide-semiconductor the 505, the 3rd
The current mirroring circuit of the metal-oxide-semiconductor 509 of metal-oxide-semiconductor 507 and the 4th composition；Wherein, second metal-oxide-semiconductor 505, the 3rd metal-oxide-semiconductor 507 and institute
The grid for stating the 4th metal-oxide-semiconductor 509 is connected with each other, and the grid with first metal-oxide-semiconductor 502 is connected, by first metal-oxide-semiconductor
The constant current of 502 branch roads is mirrored to three branch roads in proportion；The 5th metal-oxide-semiconductor 506 being connected with second metal-oxide-semiconductor 505；With
6th metal-oxide-semiconductor 508 of the 3rd metal-oxide-semiconductor 507 connection；The 7th metal-oxide-semiconductor 510 being connected with the 4th metal-oxide-semiconductor 509；With institute
State the 8th metal-oxide-semiconductor 511 of the 5th metal-oxide-semiconductor 506, the 6th metal-oxide-semiconductor 508 and the 7th metal-oxide-semiconductor 510 connection；With described
9th metal-oxide-semiconductor 512 of eight metal-oxide-semiconductors 511 connection；Wherein, the 5th metal-oxide-semiconductor 506, the 6th metal-oxide-semiconductor 508 and the 7th metal-oxide-semiconductor 510
The 8th metal-oxide-semiconductor 511 connected by diode whether is flowed into as three articles of branch currents of switch controlled, then passes through described
There is provided to the fully differential operation amplifier by electric current extraction for the current mirror of eight metal-oxide-semiconductors 511 and the 9th metal-oxide-semiconductor 512 composition
Device.
Specifically, in view of during A/D converter normal work, the spy that clock frequency can change and change with external condition
Point, present invention employs the further mode for saving power consumption.In an embodiment of the present invention, the significant contributor of power consumption is accurate
Multiply 2 circuits 307,406.Accurately multiply 2 circuits 307,406 to be made up of Differential OPAMP and electric capacity.When sampling rate changes, to essence
The performance requirement for really multiplying Differential OPAMP in 2 circuits 307,406 is also varied from, and speed is slower, and performance requirement is lower.Therefore exist
To different sampling rates, there is provided the bias current different to amplifier in the present invention.With reference to Fig. 5, Fig. 5, which is depicted, is supplied to amplifier
Reference bias current generation circuit.
Wherein, above-mentioned metal-oxide-semiconductor can be PMOS, and the metal-oxide-semiconductor 502 of amplifier 501 and first, load resistance 504 are formed
Feedback control loop, the current potential of bias nodes 503 is clamped down on as Vbias；Vbias is the reference voltage provided by benchmark so that resistance
Voltage constant on 504, so as to obtain electric current constant all the way.
First metal-oxide-semiconductor 502 and the second metal-oxide-semiconductor 505, the 3rd metal-oxide-semiconductor 507, the 4th metal-oxide-semiconductor 509 constitute current mirroring circuit,
The constant current of the branch road of first metal-oxide-semiconductor 502 is mirrored to three branch roads in proportion.Ratio in embodiment is 1:2:4.
By controlling the size of the second metal-oxide-semiconductor 505, the 3rd metal-oxide-semiconductor 507, the 4th metal-oxide-semiconductor 509, it can obtain proportional
Constant current.
5th metal-oxide-semiconductor 506, the 6th metal-oxide-semiconductor 508, the 7th metal-oxide-semiconductor 510 as three articles of branch currents of switch controlled whether
Flow into the 8th metal-oxide-semiconductor 511 connected below by diode.Due to the current in proportion of three branch roads, controlling switch pipe
Break-make can obtain the electric current of 7 kinds of sizes.The current mirror being made up of again the 8th metal-oxide-semiconductor 511 and the 9th metal-oxide-semiconductor 512 is by electric current
Draw there is provided to the amplifier in A/D converter, realize that power consumption changes with the change of clock rate.The corresponding relation such as institute of table 1
Show.Wherein C0 ~ C2 is control signal.
The programmable offset electric current of table 1 and clock corresponding table
Further, in above-mentioned analog-digital converter of the invention, it can also include：
The mode selection circuit 103 being connected with the bias current generating circuit, for according to whether in mode of operation,
Select whether the bias current generating circuit 104 works；Wherein, non-operating mode has three kinds, respectively standby, sleep and closes
Machine pattern；When in mode of operation, the mode selection circuit sets the biased electrical miscarriage according to the difference of clock frequency
The size of the bias current of raw circuit.
In addition, in the above-mentioned analog-digital converter of the present invention, can also be integrated with：With the bias current generating circuit 104
The reference voltage generating circuit 105 of connection, facilitates system application.In order to save power consumption, when outside can provide reference voltage,
Reference voltage generating circuit 105 can be closed.
In summary, implementation of the invention you provide two stage cycle structure A/D converter, chip occupying area is small, work(
Consumption is low, precision can configure.By controlling the cycle-index of circulation level, the configurable precision of 6 ~ 12 is realized, due to there is two-stage
Level is circulated, therefore the precision realized is generally 2N, wherein N is the number of times of circulation.Circular form structure inherently possesses that area is small, work(
The characteristics of consuming low, inventor adds the battery saving mode of three kinds of off working states on this basis, to save power consumption.Respectively treat
Machine, sleep and shutdown mode.Three kinds of non-operating modes can return to mode of operation at any time, but recovery time difference, because
The power consumption of this consumption is also different.
For the A/D converter phenomenon that clock frequency may change in the application, the present invention passes through to power consumption in circulation level
Significant contributor --- operational amplifier provides programmable offset electric current, realizes A/D converter total power consumption and becomes with clock frequency
The characteristics of change.For example for clock 100kHz ~ 6MHz excursion, programmable bias circuit provide 7 kinds it is of different sizes
Electric current, according to circumstances reduces unnecessary power wastage.
Described above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of principle of the present invention is not departed from, some improvements and modifications can also be made, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (9)
1. a kind of analog-digital converter, it is characterised in that including：
Input channel, for receiving analog input signal；
The first order circuit being connected with the input channel, for receiving the analog input signal；
The second level circuit being connected with the first order circuit, the simulation error for receiving the first order circuit output is believed
Number, and the analog error signal is converted into data signal output；
The first order circuit is additionally operable to receive the output signal selected in the output signal of the second level circuit, and will
The output signal selected is converted to digital output signal；
The redundancy calibration circuit being connected with the first order circuit and the second level circuit, for the first order circuit and
The data signal of the second level circuit output is calibrated, the signal after being calibrated；
Be connected to the first switch between the input channel and the first order circuit, for by the analog input signal or
The output signal of the second level circuit inputs the first order circuit；
The accuracy selection circuit of the first switch is controlled, for controlling the first order circuit and the second level circuit cycles
Number of times, so as to configure precision, the process of configuration precision includes：First order circuit and second level circuit are re-used, and often circulate
Once, be re-used once, and by 2 digit numeric codes of quantization export give redundancy calibrate circuit；Redundancy calibration circuit uses every grade 1.5
The collimation technique of position, obtains the output of 2n；Wherein n is the number of times of circulation.
2. analog-digital converter according to claim 1, it is characterised in that the first order circuit includes：
The first sub-adc converter being connected with the first switch, used in being circulated in first time, believes the simulation input
It is number thick to quantify, and provide the output signal of the first sub-adc converter；
The second switch between the first switch and first sub-adc converter is connected to, for gating first son
Analog-digital converter；
The second sub-adc converter being connected with the first switch, for the analog input signal and second level electricity
The output signal selected in the output signal on road is slightly quantified, and provides the defeated of second sub-adc converter
Go out signal；
The 3rd switch between the first switch and second sub-adc converter is connected to, for gating second son
Analog-digital converter；
The first subnumber weighted-voltage D/A converter that output with first sub-adc converter and second sub-adc converter is connected,
For the data signal of first sub-adc converter, second sub-adc converter output to be converted into analog signal；
First be connected with the sampling hold circuit of the input channel and the first subnumber weighted-voltage D/A converter output accurately multiplies 2 electricity
Road, analog input signal and the output signal of the first subnumber weighted-voltage D/A converter for the sampling hold circuit to be exported are done
Difference, and amplify 2 times.
3. analog-digital converter according to claim 2, it is characterised in that the second level circuit includes：
The 3rd sub-adc converter being connected with the output of the first order circuit, for the output of the first order circuit to be believed
It is number thick to quantify, and provide the output signal of the 3rd sub-adc converter；
The 4th switch between the first order circuit and the 3rd sub-adc converter is connected to, for gating the described 3rd
Sub-adc converter；
The 4th sub-adc converter being connected with the output of the first order circuit, for the output of the first order circuit to be believed
It is number thick to quantify；
The 5th switch between the output of the first order circuit and the 4th sub-adc converter is connected to, for gating
State the 4th sub-adc converter；
The second subnumber weighted-voltage D/A converter that output with the 3rd sub-adc converter is connected, for the 3rd submodule number to be turned
The data signal of parallel operation output is converted to analog signal；
Second be connected with the sampling hold circuit of the input channel and the second subnumber weighted-voltage D/A converter output accurately multiplies 2 electricity
Road, for the error signal of the first order circuit output and the output signal of the second subnumber weighted-voltage D/A converter to be made the difference, and
2 times of amplification.
4. analog-digital converter according to claim 3, it is characterised in that the 4th sub-adc converter is 1 modulus
Converter.
5. analog-digital converter according to claim 3, it is characterised in that described first accurate multiplies 2 circuits and second accurate
Multiply 2 circuits to constitute by Full differential operational amplifier and electric capacity.
6. analog-digital converter according to claim 5, it is characterised in that also include：
The bias current generating circuit being connected with the first order circuit and the second level circuit, for giving first order electricity
Road and the second level circuit are powered.
7. analog-digital converter according to claim 6, it is characterised in that the bias current generating circuit includes：
Amplifier and the first metal-oxide-semiconductor, the feedback control loop of load resistance formation；Wherein, the output connection described the of the amplifier
The grid of one metal-oxide-semiconductor, one end of the drain electrode connection load resistance of first metal-oxide-semiconductor, and connect the anti-of the amplifier
Phase input, the other end ground connection of the load resistance；
The current mirroring circuit that first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor are constituted；Wherein, described
The grid of two metal-oxide-semiconductors, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is connected with each other, and the grid with first metal-oxide-semiconductor is connected,
The constant current of the first metal-oxide-semiconductor branch road is mirrored to three branch roads in proportion；
The 5th metal-oxide-semiconductor being connected with second metal-oxide-semiconductor；
The 6th metal-oxide-semiconductor being connected with the 3rd metal-oxide-semiconductor；
The 7th metal-oxide-semiconductor being connected with the 4th metal-oxide-semiconductor；
The 8th metal-oxide-semiconductor being connected with the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor and the 7th metal-oxide-semiconductor；
The 9th metal-oxide-semiconductor being connected with the 8th metal-oxide-semiconductor；
Wherein, whether the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor and the 7th metal-oxide-semiconductor flow into as three articles of branch currents of switch controlled
The 8th metal-oxide-semiconductor connected by diode, then the current mirror being made up of the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor will
There is provided to the Full differential operational amplifier for electric current extraction.
8. analog-digital converter according to claim 6, it is characterised in that also include：
The mode selection circuit being connected with the bias current generating circuit, for according to whether in mode of operation, selecting institute
State whether bias current generating circuit works；
Wherein, non-operating mode has three kinds, respectively standby, sleep and shutdown mode；
When in mode of operation, the mode selection circuit sets the bias current to produce according to the difference of clock frequency
The size of the bias current of circuit.
9. analog-digital converter according to claim 1, it is characterised in that also include：
The clock driver circuit being connected with the first order circuit and the second level circuit, for producing the first order circuit
Required non-overlapping clock during with the bottomplanksampling of the second level circuit.
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| CN104753532A (en) * | 2015-04-09 | 2015-07-01 | 西安电子科技大学 | Digital-analog converter with high signal noise distortion ratio |
| US9350377B1 (en) * | 2015-07-07 | 2016-05-24 | Rohde & Schwarz Gmbh & Co. Kg | Digital-to-analog converter with local interleaving and resampling |
| CN105680860B (en) * | 2015-12-28 | 2018-11-09 | 深圳市思达仪表有限公司 | Improve the circuit and method of microcontroller A/D conversion accuracy |
| US10256834B1 (en) * | 2017-09-29 | 2019-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Analog to digital converter |
| CN113746443B (en) * | 2021-09-13 | 2023-12-05 | 江苏润石科技有限公司 | Multi-stage amplifier structure and method for adaptively adjusting slew rate |
| WO2024087236A1 (en) * | 2022-10-29 | 2024-05-02 | 华为技术有限公司 | Analog-to-digital converter and signal processing device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355266A (en) * | 2011-07-28 | 2012-02-15 | 上海宏力半导体制造有限公司 | Successive approximation register analog-digital converter |
| CN102801425A (en) * | 2012-09-07 | 2012-11-28 | 电子科技大学 | Dual-voltage-controlled oscillator loop-based Sigma-Delta analog to digital converter |
-
2013
- 2013-01-18 CN CN201310019308.6A patent/CN103944569B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355266A (en) * | 2011-07-28 | 2012-02-15 | 上海宏力半导体制造有限公司 | Successive approximation register analog-digital converter |
| CN102801425A (en) * | 2012-09-07 | 2012-11-28 | 电子科技大学 | Dual-voltage-controlled oscillator loop-based Sigma-Delta analog to digital converter |
Non-Patent Citations (1)
| Title |
|---|
| Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Technique for CMOS Image Sensor Application;Jin-Fu Lin 等;《IEEE Sensors Council》;20091231;第9卷(第12期);第2045页 * |
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