CN102801425A - Dual-voltage-controlled oscillator loop-based Sigma-Delta analog to digital converter - Google Patents

Abstract

The invention discloses a dual-voltage-controlled oscillator (VCO) loop-based Sigma-Delta analog to digital converter which belongs to the technical field of analog integrated circuits, in particular relates to a Sigma-Delta analog to digital converter comprising two VCO loops and a three-order filter. The Sigma-Delta analog to digital converter comprises a three-order low-flux filter with two feedforward branches and a feedback branch, two VCO quantizers, an NRZ DAC (Non Return To Zero Digital to Analog Converter) and an RZ DAC, and an adder-subtractor device. According to the VCO loop-based Sigma-Delta analog to digital converter, through the dual VCO loops, the even harmonics of the VCO are eliminated, the nonlinear distortion is reduced, and the adopted three-order low-flux filter comprising the two feedforward branches and the feedback branch, on the premise of ensuring system stability, the nonlinear distortion and the quantizing noise of the VCO quantizers can be further reduced. The Sigma-Delta analog to digital converter can be suitable for being applied at high speed, higher precision and low power consumption when working at a low power supply voltage.

Description

A kind of Sigma-Delta analog to digital converter based on the double pressure-controlled oscillator loop

Technical field

The invention belongs to the analog integrated circuit technical field.Be specifically related to a kind of three rank over-sampling (Sigma-Delta) analog to digital converters, be applicable to high speed analog-to-digital conversion based on double pressure-controlled oscillator (VCO) loop.

Background technology

At present, along with developing rapidly of electronic industry and communications electronics industry, Digital Signal Processing is advanced by leaps and bounds.Analog to digital converter is as the bridge of real analog signal to digital signal, needs towards more at a high speed, and high accuracy more, more the direction of low-power consumption develops.Analog to digital converter comprises two types of Nyquist analog to digital converter and over-sampling (Sigma-Delta) analog to digital converters.The clock frequency of Nyquist analog to digital converter is the twice of signal frequency; Specifically can comprise SAR again; FLASH, Pipeline etc., the clock frequency of oversampling analog-to-digital converter is far above the incoming frequency of signal; The frequency ratio of clock frequency and 2 times of input signals is called over-sampling rate (OSR), over-sampling (Sigma-Delta) analog to digital converter be divided into again discrete time (DT) analog to digital converter and continuous time (CT) analog to digital converter.Dissimilar analog to digital converters is applicable to no operation environment, and the Sigma-Delta analog to digital converter of continuous time is applicable to upper frequency, the application occasion of medium accuracy.

Along with semiconductor fabrication gets into the deep-submicron epoch (130nm, 90nm, 65nm etc.); The traditional modulus transducer, like SAR, Pipeline; FLASH etc. are converted into digital signal with voltage amplitude, are difficult in to satisfy under low supply voltage (the being lower than 1.8V) condition at a high speed; High-precision requirement becomes the bottleneck that analog to digital converter develops.

In existing technology; The Sigma-Delta analog to digital converter that has had a kind of common single voltage controlled oscillator (VCO) loop; Shown in accompanying drawing 1; The circuit module that it comprises has filter, non-return-to-zero current steer D/A converting circuit (NRZ DAC), the current steer that makes zero D/A converting circuit (RZ DAC) and VCO quantizer.Behind the signal subtraction of analog input signal and NRZ DAC feedback, get into filter, get into the VCO quantizer behind the signal subtraction of output signal after the amplification and RZ DAC feedback and accomplish analog-to-digital conversion.Simultaneously, the output digital signal of VCO quantizer gets into NRZ DAC and RZ DAC, produces the output that two feedback signals flow into analog input end and filter respectively, constitutes single VCO loop.

The advantage of the Sigma-Delta analog to digital converter of common single VCO loop is and can under the low supply voltage condition, works that low in energy consumption, speed is fast.Shortcoming is that aanalogvoltage converts in the process of VCO frequency signal and has nonlinear distortion; Thereby make the high order harmonic component (seeing accompanying drawing 3) that comprises analog input signal in the output digital signal frequency spectrum of VCO quantizer, reduced the distorted signals noise ratio (SNDR) of system to a great extent.

Summary of the invention

The objective of the invention is the high and low shortcoming of distorted signals noise ratio (SNDR) of Sigma-Delta analog to digital converter VCO nonlinear distortion in order to overcome common single VCO loop, the spy provides a kind of Sigma-Delta analog to digital converter based on double pressure-controlled oscillator (VCO) loop

The Sigma-Delta analog to digital converter of double pressure-controlled oscillator (VCO) loop that the present invention proposes; This analog to digital converter block diagram; Shown in accompanying drawing 2, this analog-digital converter structure comprises a third-order low-pass filter, two non-return-to-zero current steer analog-to-digital conversion circuit (NRZ DAC), two current steer analog-to-digital conversion circuit (RZDAC) that make zero, two VCO quantizers and adder-subtractor.Its concrete structure is following: constitute VCO loop 1 by A road VCO quantizer, RZ DAC, NRZ DAC and adder, constitute VCO loop 2 (seeing two loops that the thickness dotted line forms respectively among Fig. 2), three rank filter and adder-subtractor by B road VCO quantizer, RZ DAC, NRZ DAC and form.The input of three rank filters connects the output of analog input signal and loop 1, loop 2NRZ DAC through adder-subtractor; The output of three rank filters is through adder-subtractor linkloop 1; The input of loop 2VCO quantizer and loop 1; The output of loop 2RZ DAC, the output of the VCO quantizer of loop 1 connects the RZ DAC of this ring and the input of NRZ DAC, and the output of the VCO quantizer of loop 2 connects the RZ DAC of this ring and the input of NRZ DAC; Analog input signal and loop 1, the error signal that obtains behind the signal subtraction of loop 2NRZ DAC feedback gets into three rank filters, output signal and loop 1 after three rank filters amplify; Be divided into positive and negative two-way behind the signal subtraction of the RZ DAC feedback of loop 2; A road and B road (A, the B voltage is opposite) get into the VCO quantizer of loop 1, loop 2 respectively, and two VCO quantizers are accomplished analog-to-digital conversion; Digital signal is respectively from loop 1VCO quantizer output numeral output 1; 2, two outputs of VCO quantizer output numeral output of loop 2, the difference of numeral output 1 and numeral output 2 outputs is as the digital signal of final analog to digital converter output.

Over-sampling (Sigma-Delta) analog to digital converter of double pressure-controlled oscillator (VCO) loop that the present invention proposes; The voltage amplitude of analog signal is not to be converted into digital signal; But be converted into the oscillation frequency signal of VCO earlier; Quantizer is converted into digital signal corresponding to the oscillation frequency signal of VCO more then, is used in the quantizer based on VCO in rank Sigma-Delta loop continuous times three at last, can better suppress the nonlinear distortion of quantizing noise and VCO.Adopt two VCO quantizers to constitute two VCO loop structures simultaneously; Export the output signal subtraction of two VCO quantizers as final; Thereby eliminated the idol time (seeing equality (5)) in aanalogvoltage amplitude and the VCO frequency of oscillation relation; The realization even-order harmonic offsets, and has reduced the nonlinear distortion of VCO, improve transducer distorted signals noise ratio (SNDR).Simultaneously, three rank filters of employing let quantizing noise reduce as far as possible under the prerequisite that guarantees loop stability, have also further suppressed the nonlinear distortion of VCO simultaneously.

Below the work of two VCO cyclic system block diagrams that the present invention is proposed and each module as an introduction:

The present invention sees accompanying drawing 2, has adopted the non-return-to-zero current steer analog-to-digital conversion circuit (NRZDAC) of prior art.NRZ DAC is used to produce the input formation negative feedback that a corresponding current value of digital signal size with input arrives whole system, and different clocks periodic current size is linear with corresponding cycle supplied with digital signal size.Electric current is kept corresponding steady state value in a clock cycle, therefore be called non-return-to-zero DAC.

Figure 2 preclude the use of the prior art analog to digital conversion of zero current steering circuit (RZ? DAC).RZ DAC is used to produce one and forms negative feedback with the big or small corresponding current value of supplied with digital signal to the output of system's three rank filter modules, and different clocks periodic current size is linear with corresponding cycle supplied with digital signal size.Different with NRZ DAC is, RZ DAC exports corresponding current value in the positive half period of clock, and output current is zero in the negative half-cycle of clock, therefore is called the DAC that makes zero.

The three rank filters that adopt among the present invention; Realize the amplification of low frequency aberration signal; Quantizing noise and VCO nonlinear distortion in the ability rejects trap bandwidth, more the filter of high-order can play better inhibition effect to quantizing noise usually, but makes system unstable more easily.

The VCO quantizer that adopts among the present invention realizes controlling voltage to the conversion of digital signal, and input voltage is the control voltage of voltage controlled oscillator (VCO), can change the frequency of VCO.The VCO quantizer at first is converted into the voltage of control end the frequency signal of VCO, and then the frequency signal of VCO is converted into digital signal corresponding output.

Below in conjunction with the description of preceding text to system configuration and each functions of modules, the principle that weight analysis double pressure-controlled oscillator of the present invention (VCO) loop realizes that even-order harmonic is offset, and theoretical foundation of the present invention.

The VCO quantizer is realized the conversion of aanalogvoltage to digital signal among the present invention, comprises two processes: 1, and the control voltage transitions of VCO quantizer is the frequency signal of VCO quantizer; 2, the frequency signal of VCO quantizer converts digital signal into.

The VCO quantizer controls voltage to the conversion of frequency.V _CtrlBe the input signal of VCO quantizer, its size can be controlled the frequency of oscillation f of VCO quantizer _VcoThereby, the input analog voltage amplitude is converted into frequency signal, the two satisfies following relation:

$f_{\mathrm{vco}}={\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="HDA00002113667500021.png,HDA00002113667500022.png"\; state="\{\{state\}\}">f</figure-callout>}}_0+K_{\mathrm{vco}}*V_{\mathrm{ctrl}}+a_2*V_{\mathrm{ctrl}}^2+a_3*V_{\mathrm{ctrl}}^3+......---\left(1\right)$

F wherein ₀Frequency of oscillation when being zero for control voltage, K _VcoArrive the gain of frequency for the voltage of VCO quantizer; Higher order term is represented the non-linear partial of electric voltage frequency conversion; Can produce the high order harmonic component of input signal; Higher order term has produced the nonlinear distortion of VCO quantizer just, has limited the distorted signals noise ratio (SNDR) of common single voltage controlled oscillator (VCO) loop Sigma-Delta analog to digital converter, thereby reduces the number of significant digit (ENOB) of analog to digital converter.SNDR and ENOB satisfy following relation:

SNDR=6.02*ENOB+1.76 （2）

The VCO quantizer is realized the conversion of frequency signal to digital signal.The VCO quantizer is N level ring oscillator (Ring VCO) among the present invention, f _VcoBe the frequency of oscillation of VCO quantizer, f _ClkBe clock frequency, Out is the size of VCO quantizer output digital signal.

f _Vco, f _ClkSatisfy following relation with Out three:

$\mathrm{Max}\left(f_{\mathrm{vco}}\right)<\frac{f_{\mathrm{clk}}}{2}---\left(3\right)$

$\mathrm{Out}=\mathrm{Ceil}\left(\frac{2N*f_{\mathrm{vco}}}{f_{\mathrm{clk}}}\right)---\left(4\right)$

Wherein maximum is got in Max () expression, Ceil () expression round numbers part.

Double pressure-controlled oscillator (VCO) loop is realized the even-order harmonic counteracting.In the accompanying drawing 2, the control end A of two VCO quantizers is opposite with B voltage, and the corresponding frequency of oscillation of result after two VCO quantizer outputs are subtracted each other can be obtained by (1):

$f=f_{\mathrm{vco}}\left(V_{\mathrm{vctrl}}\right)-f_{\mathrm{vco}}(-V_{\mathrm{vctrl}})=2K_{\mathrm{vco}}*V_{\mathrm{vctrl}}+2a_3{V}_{\mathrm{vctrl}}^3+.....---\left(5\right)$

Can see from (5); An idol time cancellation of back control voltage is subtracted each other in output; That is to say even-order harmonic cancellation in the output; Thereby reduce the nonlinear distortion of VCO quantizer, double pressure-controlled oscillator (VCO) the loop Sigma-Delta analog to digital converter that the present invention proposes utilizes this relation to improve the distorted signals noise ratio (SNDR) of system just.

The advantage of double pressure-controlled oscillator (VCO) the loop Sigma-Delta analog to digital converter that proposes for embodiment the present invention of image more; According to accompanying drawing 1 and accompanying drawing 2; Set up the behavioral level simulation model of the two VCO loop Sigma-Delta analog to digital converters of common single VCO loop Sigma-Delta analog to digital converter and the present invention respectively; Input signal is the sinusoidal signal of 1MHz; Bandwidth is 10MHz, and accompanying drawing 3 is common single VCO loop Sigma-Delta analog to digital converter output spectrum figure, two VCO loop Sigma-Delta analog to digital converter output spectrum figure that accompanying drawing 4 proposes for the present invention.

Can see from accompanying drawing 3; Comprise higher second harmonic and triple-frequency harmonics in the output spectrum of common single voltage controlled oscillator (VCO) loop Sigma-Delta; The second harmonic amplitude is about-90dB, and the triple-frequency harmonics amplitude is about-120dB, and the second harmonic amplitude is much larger than the triple-frequency harmonics amplitude.The signal noise ratio that calculates (SNR) is 83.7dB, and distorted signals noise ratio (SNDR) is 75.9dB, and the difference of signal noise ratio (SNR) and distorted signals noise ratio (SNDR) is very big, shows that high order harmonic component has limited the SNDR of system.

Can see that from accompanying drawing 4 second harmonic is cancelled in the output spectrum of double pressure-controlled oscillator (VCO) the loop Sigma-Delta that the present invention proposes, only has triple-frequency harmonics, its amplitude is about-100dB.The signal noise ratio that calculates (SNR) is 86.5dB, and distorted signals noise ratio (SNDR) is 85.8dB.The very for a short time high order harmonic component that shows of the difference of SNR and SNDR is very little to the SNDR influence of system.Simultaneously, contrast can see that because the analog-digital converter structure that the present invention proposes has been offset even-order harmonic, the more single VCO loop structure of distorted signals noise ratio (SNDR) has improved about 10dB, and number of significant digit (ENOB) improves 1.5.

In sum, two VCO loop analog-digital converter structures that the present invention proposes have effectively reduced the nonlinear distortion of VCO quantizer, have improved the distorted signals noise ratio (SNDR) of system, and the performance of system obtains bigger improvement.

Description of drawings

Fig. 1 is common single VCO loop Sigma-Delta analog-to-digital converter block diagram.

Fig. 2 is the two VCO loop Sigma-Delta analog-to-digital converter block diagrams of the present invention.

Fig. 3 is common single VCO loop Sigma-Delta analog to digital converter behavioral level simulation output spectrum.

Fig. 4 is the two VCO loop Sigma-Delta analog to digital converter behavioral level simulation output spectrums of the present invention.

Fig. 5 is the circuit structure diagram of the VCO quantizer of an instance employing of the present invention.

Fig. 6 is the circuit structure diagram of the non-return-to-zero digital to analog converter (NRZ DAC) of an instance employing of the present invention.

Fig. 7 is the circuit structure diagram of the digital to analog converter that makes zero (RZ DAC) of an instance employing of the present invention.

Fig. 8 is the three rank filter circuit configuration figure that instance of the present invention adopts.

Fig. 9 is the transistor-level simulation output signal spectrum figure of an instance of the present invention.

Embodiment

A kind of Sigma-Delta analog to digital converter based on double pressure-controlled oscillator (VCO) loop to the present invention proposes in conjunction with accompanying drawing, is described further through an instance and simulation result, but is not construed as limiting the invention.

At first will confirm the system index of analog to digital converter, the target of this instance is: bandwidth is 10MHz, and distorted signals noise ratio (SNDR) is greater than 72dB, and clock frequency is 400MHz.

The design of VCO quantizer; The VCO quantizer structure that adopts is shown in accompanying drawing 5; In order to realize multidigit output digital signal; The inner voltage controlled oscillator (VCO) of VCO quantizer has adopted ring oscillator (Ring VCO), and process that is used in combination and system are to the requirement of distorted signals noise ratio (SNDR), and this example has adopted 15 grades of ring oscillators (Ring VCO).Output digital signal out span in the accompanying drawing 5 is 1 to 15 like this, can confirm according to relation (4) formula: when VCO quantizer output Out=1, and f _Vco=13.3MHz, when VCO quantizer output Out=15, f _Vco=200MHz, the surge frequency range of ring oscillator (RingVCO) is 13.3MHz ~ 200MHz.In the accompanying drawing 2, require the control voltage of A road and B road VCO quantizer opposite,, only need just can realize opposite connection of the control voltage of two VCO quantizers for the difference control end.Each grade of 15 grades of ring oscillators (Ring VCO) in this example adopts the inverter structure of standard; Simultaneously connect a nmos pass transistor and PMOS transistor respectively as two difference control valves at inverter nmos pass transistor and the transistorized source of PMOS end; The grid of two control valves connects the frequency that different voltages can change ring oscillator (Ring VCO), therefore can be as the difference control end that needs.

D type flip flop in the accompanying drawing 5 (DFF) and XOR gate (XOR) have adopted the numeric structure of prior standard, for can be under the clock frequency of 400MHz operate as normal, have enough big driving force simultaneously, DFF in this example and XOR will consume bigger dynamic current.

The design of non-return-to-zero current steer analog-to-digital conversion circuit (NRZ DAC), NRZ DAC module is made up of the Control current unit of a plurality of parallel connections.The Control current unit module structure that this example adopts is shown in accompanying drawing 6; D type flip flop (DFF) is data and clock synchronization; High crosspoint buffer uprises the crosspoint of two input voltage rising edges and trailing edge, to reduce clock feed-through effect, according to C; The voltage relationship that D is 2, transistor NMOS current source flow out the electric current of a constant size from one of two output port Iout+ and Iout-.Consider that this example has adopted 15 grades of ring oscillators (Ring VCO); Therefore non-return-to-zero current steer analog-to-digital conversion circuit (NRZDAC) need be made up of the Control current unit of 15 parallel connections, and 15 outputs of VCO quantizer are received the data input pin of each Control current unit of NRZ DAC respectively.Simultaneously, system is carried out behavioral level simulation, in order to satisfy the design objective of system, the output current of confirming each Control current unit is 210uA.

The output current of two non-return-to-zero current steer analog-to-digital conversion circuit (NRZ DAC) subtracts each other and can regard an output current and another reverse current addition as in the accompanying drawing 2.This example replaces to the PMOS current source to the NMOS current source of one of them non-return-to-zero current steer analog-to-digital conversion circuit (NRZ DAC); High crosspoint buffer changes low crosspoint buffer into; The output of right latter two non-return-to-zero current steer analog-to-digital conversion circuit (NRZ DAC) directly connects together; Realize the phase reducing of two NRZ DAC output currents, do not need an other subtracter.In addition, each module among the figure all adopts existing technology to realize.

The design of the current steer that makes zero analog-to-digital conversion circuit (RZ DAC), RZ DAC module is made up of the Control current unit of a plurality of parallel connections equally.The Control current unit module structure that adopts in this example is shown in accompanying drawing 7; D type flip flop (DFF) is data and clock synchronization; The current source control logic is according to importing the correct voltage logic of data and clock generating with the Control current source; Make two the output Iout+ and the Iout-of current source export constant size and electric current in the opposite direction, make zero at the negative half-cycle output current of clock at the positive half period of clock.Consider that this instance has adopted 15 grades of ring oscillators (Ring VCO); Therefore the current steer analog-to-digital conversion circuit (RZ DAC) that makes zero need be made up of the Control current unit of 15 parallel connections, and 15 outputs of VCO quantizer are received the data input pin of each Control current unit of RZ DAC respectively.Simultaneously, system is carried out behavioral level simulation, in order to satisfy the design objective of system, the output current of confirming each Control current unit is 20uA.

The output current of two current steer analog-to-digital conversion circuit (RZ DAC) that make zero subtracts each other and can regard an output current and another reverse current addition as in the accompanying drawing 2, and therefore the suitable connection of output of two RZ DAC just can realize current subtraction.In addition, each module among the figure all adopts existing technology to realize.

The design of third-order low-pass filter, the modular structure of third-order low-pass filter shown in accompanying drawing 8,

Be the integrator of three cascades, k ₁, k ₂, k ₃Be respectively the gain of three integrators, there is a feedforward path in the input of three integrators of the output to the of first integrator, and gaining is k _F1, there is the second feedforward path in the output of three integrators of the output to the of first integrator, gains to be k _F2, there is a feedback network in the input of output to the second integrator of the 3rd integrator, and gaining is kz.Article two, feedforward path is used for producing two zero points, increases the stability of system, and feedback network is used for producing a pair of plural limit, optimizes its position in bandwidth and can let system that the inhibition of quantizing noise is reached best effect.

The clock frequency of instance is 400MHz, and bandwidth is 10MHz, confirms that therefore over-sampling rate (OSR) is 20.Utilize over-sampling (Sigma-Delta) tool box of matrix experiment chamber (MATLAB) comprehensively to go out to satisfy three rank filter coefficients of system design index, calculate the coefficient k shown in the accompanying drawing 8 then ₁, k ₂, k ₃, k _F1, k _F2, kz.The active integrator that basic integrator unit in the accompanying drawing 8 has adopted amplifier and feedback resistance electric capacity to form is realized.

The analog input signal of instance is the sinusoidal signal of 1MHz; Behind three rank filters and two voltage controlled oscillators (VCO) loop, change out two ways of digital signals, it is as shown in Figure 9 to make its frequency spectrum of fast Fourier transform (FFT) after the two ways of digital signals of changing out is subtracted each other.Can calculate the interior corresponding distorted signals noise ratio (SNDR) of 10MHz signal bandwidth and be 75.1dB, signal noise ratio (SNR) is 75.4dB, and number of significant digit (ENOB) is 12bit.Can see also that from accompanying drawing 9 second harmonic is lower than triple-frequency harmonics simultaneously, of the present invention pair of VCO loop structure effectively reduced even-order harmonic, improved distorted signals noise ratio (SNDR).

In sum; The Sigma-Delta analog to digital converter based on double pressure-controlled oscillator (VCO) loop that the present invention proposes has reduced the nonlinear distortion of VCO, improves the distorted signals noise ratio (SNDR) of system; Can realize that the analog signal of degree of precision is to the conversion of digital signal at a high speed.

Claims (3)

1. Sigma-Delta analog to digital converter based on the double pressure-controlled oscillator loop; The frequency signal that includes the third-order low-pass filter of the nonlinear distortion that is used to suppress the VCO quantizer in the bandwidth range and quantizing noise, is converted into oscillator to input voltage is converted into VCO quantizer, non-return-to-zero current steer analog-to-digital conversion circuit (NRZ DAC), the current steer that makes zero analog-to-digital conversion circuit (RZ DAC) and the adder-subtractor of digital signal again; It is characterized in that: this analog-to-digital conversion device constitutes VCO loop (1) by A road VCO quantizer, NRZ DAC.RZ DAC and adder-subtractor; Constitute VCO loop (2) by B road VCO quantizer, NRZ DAC, RZ DAC; One three rank filter and adder-subtractor are formed; The input of three rank filters connects the output of analog input signal and loop (1) NRZ DAC, loop (2) NRZ DAC through adder-subtractor; Input and the loop (1) of the output of three rank filters through the VCO quantizer of adder-subtractor linkloop (1), loop (2), the RZ DAC output of loop (2); The output of the VCO quantizer of loop (1) connects the RZ DAC of this ring and the input of NRZDAC, and the output of the VCO quantizer of loop (2) connects the RZ DAC of this ring and the input of NRZ DAC; The error signal that obtains behind the signal subtraction of analog input signal and two NRZ DAC feedbacks gets into three rank filters; Be divided into positive and negative two-way A road behind the signal subtraction of the output signal after three rank filters amplify and two RZ DAC feedbacks, the B road gets into two VCO quantizers respectively and accomplishes analog-to-digital conversion; From the VCO quantizer output output numeral output (1) and the numeral output (2) of loop (1), loop (2), the difference of two numeral outputs is as the digital signal of final conversion respectively for digital signal.

2. a kind of Sigma-Delta analog to digital converter according to claim 1 based on the double pressure-controlled oscillator loop; It is characterized in that: the VCO device that analog to digital converter of the present invention adopts is ring oscillator (Ring VCO); (the Control current unit number of RZ DAC parallel connection is identical, and the output of VCO quantizer is received the data input pin of the Control current unit of NRZDAC, RZ DAC respectively for its annular progression and non-return-to-zero current steer analog-to-digital conversion circuit (NRZ DAC) and the current steer analog-to-digital conversion circuit that makes zero.

3. a kind of Sigma-Delta analog to digital converter according to claim 2 based on the double pressure-controlled oscillator loop; It is characterized in that: the VCO quantizer that the analog to digital converter in the present embodiment adopts is 15 grades of ring oscillators (Ring VCO); Non-return-to-zero current steer analog-to-digital conversion circuit (NRZ DAC) is made up of the Control current unit of 15 parallel connections; 15 outputs of VCO quantizer are received the data input pin of each Control current unit of NRZ DAC respectively; The current steer that makes zero analog-to-digital conversion circuit (RZ DAC) is made up of the Control current unit of 15 parallel connections; 15 outputs of VCO quantizer are received the data input pin of each Control current unit of RZ DAC respectively, and third-order low-pass filter is the integrator of three cascades.

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