CN206076225U - Semiconductor FET transistor structure - Google Patents
Semiconductor FET transistor structure Download PDFInfo
- Publication number
- CN206076225U CN206076225U CN201621094899.9U CN201621094899U CN206076225U CN 206076225 U CN206076225 U CN 206076225U CN 201621094899 U CN201621094899 U CN 201621094899U CN 206076225 U CN206076225 U CN 206076225U
- Authority
- CN
- China
- Prior art keywords
- chip
- lead
- transistor structure
- fet transistor
- semiconductor fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
This utility model is related to a kind of semiconductor FET transistor structure, including load central layer, chip, gate lead, source lead and conducting strip, the load central layer is provided with drain lead, the chip is provided with drain electrode, grid and source electrode, the chip is fixedly arranged on the load central layer, and the drain electrode of the chip is electrically connected with the drain lead by the load central layer, the grid of the chip is electrically connected with the gate lead, the two ends of the conducting strip are adhesively fixed with the source electrode and the source lead of the chip respectively, the source electrode and the source lead for making the chip is turned on.The semiconductor FET transistor structure can improve the production efficiency of transistor, lift the heat-sinking capability of transistor.
Description
Technical field
This utility model is related to transistor arts, more particularly to a kind of semiconductor FET transistor structure.
Background technology
Metal current oxide semiconductor field effect transistor (MOS), mainly uses aluminum steel or copper cash to pass through key in encapsulation
Chip is bridged by conjunction with framework.Existing semiconductor field effect transistor chip is bridged by copper cash or aluminum steel, brilliant
Body tube capacity easily generates heat, and low production efficiency.
The content of the invention
Based on this, it is necessary to provide a kind of semiconductor FET transistor structure, the production efficiency of transistor can be improved, is carried
Rise the heat-sinking capability of transistor.
Its technical scheme is as follows：
A kind of semiconductor FET transistor structure, including central layer, chip, gate lead, source lead and conducting strip are carried,
The load central layer is provided with drain lead, and the chip is provided with drain electrode, grid and source electrode, the chip be fixedly arranged on it is described carry central layer,
And the drain electrode of the chip is electrically connected with the drain lead by the load central layer, the grid of the chip is drawn with the grid
Foot is electrically connected, and the two ends of the conducting strip are adhesively fixed with the source electrode and the source lead of the chip respectively.
Further below technical scheme is illustrated：
Wherein in one embodiment, the source electrode of one end of the conducting strip by conductive adhesive with the chip is electrically connected
Connect, the other end is electrically connected with the source lead by conductive adhesive.
Wherein in one embodiment, the conductive adhesive is tin cream or silver paste.
Wherein in one embodiment, the of first connector and lamellar that are respectively arranged at two ends with lamellar of the conducting strip
Two connectors, first connector are electrically connected with the source electrode of the chip by the conductive adhesive, second connection
Body is electrically connected with the source lead by the conductive adhesive.
Wherein in one embodiment, the conducting strip is additionally provided with the transition body of the first connector and the second connector, institute
State the first connector longitudinally to stagger setting by the transition body and second connector.
Wherein in one embodiment, the conducting strip be copper sheet conductor, aluminium flake conductor, stannum piece conductor, silver strip conductor or
Gold plaque conductor.
Wherein in one embodiment, the grid of the chip is electrically connected with the gate lead by wire.
Wherein in one embodiment, one end of the wire bridges the fixed, other end and institute with the grid of the chip
State gate lead to fix.
Wherein in one embodiment, the gate lead is arranged at intervals at the drain lead with the source lead
Both sides and respectively with the drain lead insulate.
Wherein in one embodiment, the gate lead free end, the free end of the source lead and the drain electrode
The free end interval setting in the same direction of pin insulation.
" first " described in above-mentioned this utility model, " second " do not represent specific quantity and order, are only used for name
The differentiation of title.
Above-mentioned the beneficial effects of the utility model：
Above-mentioned semiconductor FET transistor structure, using the conducting strip of large area lamellar bridge the source electrode of the chip with
The source lead, realizes between chip and source lead high current bridge joint, while being conducive to transistor radiating, is bridging
Chip will not be damaged in journey, packaging efficiency is also improved.The semiconductor FET transistor structure, can improve the production of transistor
Efficiency, lifts the heat-sinking capability of transistor.
Description of the drawings
Fig. 1 is the schematic diagram of semiconductor FET transistor structure described in the utility model.
Description of reference numerals：
100th, carry central layer, 110, drain lead, 200, chip, 210, drain electrode, 220, grid, 230, source electrode, 300, conductive
Piece, the 310, first connector, the 320, second connector, 330, transition body, 400, gate lead, 500, source lead, 600, lead
Electric binding agent, 10, wire.
Specific embodiment
It is to make the purpose of this utility model, technical scheme and advantage become more apparent, below in conjunction with accompanying drawing and specifically real
Mode is applied, this utility model is described in further detail.It should be appreciated that specific embodiment described herein
Only to explain this utility model, protection domain of the present utility model is not limited.
As shown in figure 1, a kind of semiconductor FET transistor structure described in the utility model, including carry central layer 100, core
Piece 200, gate lead 400, source lead 500 and conducting strip 300, carry central layer 100 and are provided with drain lead 110, and chip 200 is provided with
Drain electrode 210, grid 220 and source electrode 230, chip 200 be fixedly arranged on carry central layer 100, and chip 200 drain electrode 210 by carrying central layer
100 are electrically connected with drain lead 110, and the grid 220 of chip 200 is electrically connected with gate lead 400, the two ends point of conducting strip 300
It is not adhesively fixed with the source electrode 230 and source lead 500 of chip 200, the source electrode 230 and source lead 500 for making chip 200 is led
It is logical.
The semiconductor FET transistor structure, using the source electrode of 300 bridging chip 200 of conducting strip of large area lamellar
230 with source lead 500, realize between chip 200 and source lead 500 high current bridge joint, while being conducive to transistor to dissipate
Heat, will not damage chip 200 during bridge joint, also improve packaging efficiency.The semiconductor FET transistor structure, can carry
The production efficiency of high transistor, lifts the heat-sinking capability of transistor.
In the present embodiment, one end of conducting strip 300 is electrically connected with the source electrode 230 of chip 200 by conductive adhesive, separately
One end is electrically connected with source lead 500 by conductive adhesive 600, thus chip 200 will not be damaged during bridge joint, and
And can ensure that the source electrode 230 of chip 200 and source lead 500 are turned on；Preferably, conductive adhesive 600 is tin cream or silver paste.Enter
One step, the second connector 320 of first connector 310 and lamellar that are respectively arranged at two ends with lamellar of conducting strip 300, first connects
Junctor 310 is electrically connected with the source electrode 230 of chip 200 by conductive adhesive 600, and the second connector 320 passes through conductive adhesive
600 are electrically connected with source lead 500, can increase bonding using the second connector 320 of first connector 310 and lamellar of lamellar
Area, makes the source electrode 230 and source lead 500 of conducting strip 300 and chip 200 be adhesively fixed reliability, while transistor can be improved
Radiating efficiency, it is to avoid local accumulated heat；Further, conducting strip 300 is additionally provided with the first connector 310 and the second connector 320
Transition body 330, the first connector 310 is longitudinally staggered setting by transition body 330 and the second connector 320, thus chip 200
Source electrode 230 longitudinally can stagger with source lead 500, source lead 500 is separated with framework；Preferably, conducting strip 300 is copper
The Metal Flake conductors such as piece conductor, aluminium flake conductor, stannum piece conductor, silver strip conductor or gold plaque conductor, are easy to radiating.Further
, the grid 220 of chip 200 is electrically connected with gate lead 400 by wire 10, it is to avoid the grid 220 of chip 200 and chip
200 source electrode 230 is short-circuit；Preferably, one end of wire 10 bridges the fixed, other end and gate lead with the grid 220 of chip
400 fix.Further, gate lead 400 and source lead 500 are arranged at intervals at both sides and the difference of drain lead 110
Insulate with drain lead 110；Preferably, 400 free end of gate lead, the free end of source lead 500 and drain lead 110 are exhausted
Edge.
Each technical characteristic of embodiment described above arbitrarily can be combined, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses several embodiments of the present utility model, and its description is more concrete and detailed,
But therefore can not be interpreted as the restriction to utility model patent scope.It should be pointed out that for the common skill of this area
For art personnel, without departing from the concept of the premise utility, some deformations and improvement can also be made, these belong to
Protection domain of the present utility model.Therefore, the protection domain of this utility model patent should be defined by claims.
Claims (10)
1. a kind of semiconductor FET transistor structure, it is characterised in that including carrying central layer, chip, gate lead, source lead
And conducting strip, the load central layer is provided with drain lead, and the chip is provided with drain electrode, grid and source electrode, and the chip is fixedly arranged on institute
State and carry the drain electrode of central layer and the chip and electrically connected with the drain lead by the load central layer, the grid of the chip and
The gate lead electrical connection, the two ends of the conducting strip are bonding with the source electrode of the chip and the source lead solid respectively
It is fixed.
2. semiconductor FET transistor structure according to claim 1, it is characterised in that one end of the conducting strip leads to
Cross that conductive adhesive is electrically connected with the source electrode of the chip, the other end is electrically connected with the source lead by conductive adhesive.
3. semiconductor FET transistor structure according to claim 2, it is characterised in that the conductive adhesive is stannum
Cream or silver paste.
4. semiconductor FET transistor structure according to claim 2, it is characterised in that the two ends of the conducting strip point
Second connector of first connector and lamellar of lamellar is not provided with, first connector passes through the conductive adhesive and institute
The source electrode electrical connection of chip is stated, second connector is electrically connected with the source lead by the conductive adhesive.
5. semiconductor FET transistor structure according to claim 4, it is characterised in that the conducting strip is additionally provided with
The transition body of one connector and the second connector, first connector pass through the transition body and the second connector longitudinal direction
Stagger setting.
6. semiconductor FET transistor structure according to claim 1, it is characterised in that the conducting strip is led for copper sheet
Body, aluminium flake conductor, stannum piece conductor, silver strip conductor or gold plaque conductor.
7. semiconductor FET transistor structure according to claim 1, it is characterised in that the grid of the chip passes through
Wire is electrically connected with the gate lead.
8. semiconductor FET transistor structure according to claim 7, it is characterised in that one end of the wire and institute
State the grid bridge joint fixation of chip, the other end to fix with the gate lead.
9. the semiconductor FET transistor structure according to any one of claim 1 to 8, it is characterised in that the grid
Pin is arranged at intervals at the both sides of the drain lead with the source lead and is insulated with the drain lead respectively.
10. semiconductor FET transistor structure according to claim 9, it is characterised in that the gate lead freedom
The free end interval setting in the same direction of end, the free end of the source lead and drain lead insulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621094899.9U CN206076225U (en) | 2016-09-29 | 2016-09-29 | Semiconductor FET transistor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621094899.9U CN206076225U (en) | 2016-09-29 | 2016-09-29 | Semiconductor FET transistor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206076225U true CN206076225U (en) | 2017-04-05 |
Family
ID=58441392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621094899.9U Active CN206076225U (en) | 2016-09-29 | 2016-09-29 | Semiconductor FET transistor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206076225U (en) |
-
2016
- 2016-09-29 CN CN201621094899.9U patent/CN206076225U/en active Active
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190328 Address after: 510730 Baoying Avenue, Guangzhou Economic and Technological Development Zone, Guangzhou City, Guangdong Province (self-declaration) Patentee after: Guangzhou Feihong Microelectronics Co., Ltd. Address before: 510730 Baoying Avenue, Guangzhou Bonded Zone, Guangzhou, Guangdong Province, 13 Patentee before: Guangzhou Feihong Youyi Electronic Technology Co Ltd |