CN206076221U - For slowing down the chip-packaging structure of electromagnetic interference - Google Patents
For slowing down the chip-packaging structure of electromagnetic interference Download PDFInfo
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- CN206076221U CN206076221U CN201621015002.9U CN201621015002U CN206076221U CN 206076221 U CN206076221 U CN 206076221U CN 201621015002 U CN201621015002 U CN 201621015002U CN 206076221 U CN206076221 U CN 206076221U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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Abstract
This utility model discloses a kind of chip-packaging structure for slowing down electromagnetic interference, by making subsidence trough on a silicon substrate, and chip front side weld pad is imbedded into subsidence trough upward, save encapsulated space, by the inductance wiring that horizontal arrangement or vertical arrangement are formed in chip front side and silicon substrate first surface, and the capacitance wiring of horizontal arrangement or vertical arrangement is formed on the first insulating barrier, first metal is rerouted or the second metal is rerouted and soldered ball is extended on silicon substrate, realize and electrically fan out to chip pad silicon substrate, improve package reliability, process is simple, low cost；The inductance wiring of horizontal arrangement or vertical arrangement constitutes inductance, and the capacitance wiring and dielectric layer therebetween of horizontal arrangement or vertical arrangement constitute electric capacity, inductance with filtering characteristic and electric capacity can slow down the crosstalk of signal between chip internal circuit, filter the unwanted signal of telecommunication, strengthen the reliability and performance of encapsulating products, while reduces cost.
Description
Technical field
This utility model is related to a kind of field of semiconductor package, more particularly, to a kind of chip for slowing down electromagnetic interference
Encapsulating structure.
Background technology
Chip needs to carry out surface mount printed circuit board (PCB) after level package is completed, and connects other elements, realizes its function.
Electronic Packaging miniaturization, high density, multi-functional development trend, elements on circuit board quantity is followed to increase, adjacent elements spacing
From shortening, the probability that interelement occurs radiation interference when circuit works is substantially improved, and line impedance is mismatched and circuit noise
Phenomenon increases, and affects signal transmission quality.
Generally, wiring board adopts embedded set electric capacity, inductance, reduces the impact of above-mentioned phenomenon.Reducing encapsulating face
Product, while improving the integrated level of potted element, can also slow down.
The content of the invention
This utility model is to meet above-mentioned challenge, there is provided a kind of chip-packaging structure for slowing down electromagnetic interference, is led to
Direct stack capacitor, inductance or horizontal arrangement electric capacity, inductance on a single chip are crossed on single-chip vertical direction, encapsulation is reduced
Area, improves the integrated level of potted element.
Specific implementation is as follows：
A kind of chip-packaging structure for slowing down electromagnetic interference, including silicon substrate and chip, the silicon substrate have the
One surface and second surface corresponding thereto, are formed with least one recessed towards the sinking of second surface on the first surface
Groove, chip back described at least one mount the bottom land of the subsidence trough down, and the chip front side includes weld pad；Institute
State between chip the week side of boss and subsidence trough side wall, the first insulation is formed with the chip front side and the first surface
Layer；The inductance wiring of horizontal arrangement or vertical arrangement is formed with first insulating barrier, and is formed on first insulating barrier
There is the capacitance wiring of horizontal arrangement or vertical arrangement, be also formed with electrically deriving the chip pad on first insulating barrier
Metal reroute, the weld pad of inductance wiring, the capacitance wiring and the chip is electrically connected with.
Further, the rewiring of the first metal, the wiring of the first inductance, the first electric capacity cloth are formed with first insulating barrier
Line, first metal reroute the weld pad that the chip is electrically connected through first insulating barrier, the first metal weight cloth
Line, first inductance wiring, it is formed with the second insulating barrier on first capacitance wiring, is formed with second insulating barrier
Second metal is rerouted, the second inductance is connected up and the second capacitance wiring, and second metal is rerouted through the described second insulation
Layer electrical connection first metal is rerouted, between each circuit of the first inductance wiring, second inductance wiring it is each
Between circuit, first inductance wiring circuit and second inductance wiring circuit between by broken line mode continuously around
Inductance wiring is gone into, and it is parallel or close parallel between each circuit, between first capacitance wiring and second capacitance wiring
It is provided with dielectric layer；Second metal is rerouted, second inductance wiring, be coated with protection on second capacitance wiring
Layer, during second metal is rerouted, at least one circuit is extended on the silicon substrate outside the chip area.
Further, be formed with first insulating barrier the first metal reroute, the wiring of the first inductance for continuously detouring,
Middle ware is separated with least two first capacitance wirings of dielectric layer, and first metal is rerouted, the first inductance wiring and the
One capacitance wiring electrically connects the weld pad of the chip through first insulating barrier；First metal is rerouted, described first
Protective layer is coated with inductance wiring, first capacitance wiring, at least one circuit prolongs during first metal is rerouted
Reach on the silicon substrate outside the chip area.
Further, first capacitance wiring and the second capacitance wiring are equivalently-sized metal derby.
Further, the material of first insulating barrier and second insulating barrier is polymer latex.
Further, second metal reroutes the soldered ball/salient point being connected with through the protective layer.
Further, the chip back is attached to the bottom land of the subsidence trough by cohering sticker, the glue that coheres
Thickness is less than 50 microns, more than 1 micron.
Further, the number of chips for imbedding same subsidence trough is more than or equal to 2.
Further, the thickness that first metal is rerouted is more than 0.2 micron.
Advantageous Effects of the present utility model are as follows：This utility model is used for the chip package knot for slowing down electromagnetic interference
Chip front side weld pad by making subsidence trough on a silicon substrate, and is imbedded subsidence trough by structure upward, so, saves envelope
Dress space, and silicon substrate can make forming fine wiring, be vertically arranged by being formed in chip front side and silicon substrate first surface
Inductance/capacitance structure, i.e. the first metal reroute and the second metal reroute, the first inductance wiring and the second inductance wiring,
First capacitance wiring and the second capacitance wiring, the second metal is rerouted and soldered ball is extended on silicon substrate, is realized core
Piece weld pad electrically fans out to silicon substrate, improves package reliability, process is simple, low cost；First inductance is connected up and the
The wiring of two inductance constitutes inductance wiring, the first capacitance wiring and the second capacitance wiring and constitutes capacitance wiring, special with filtering
The inductance and electric capacity of property can slow down the crosstalk of signal between chip internal circuit, filter the unwanted signal of telecommunication；Or in chip
Horizontally disposed inductance/capacitance structure is formed on front and silicon substrate first surface, i.e., is rerouted same flat with the first metal
First inductance for continuously detouring in face is connected up, and middle ware is separated with least two first capacitance wirings of dielectric layer, reduces
The crosstalk of signal between chip internal circuit, strengthens the reliability and performance of encapsulating products, while reduces cost.
Description of the drawings
Fig. 1 is the generalized section that this utility model silicon substrate imbeds chip；
Fig. 2 is that this utility model forms the first insulating barrier and makes the generalized section of insulating layer openings；
Fig. 3 is that this utility model whole face on the first insulating barrier deposits the generalized section after the first Seed Layer；
Generalized sections of the Fig. 4 for this utility model coating photoresist in the first Seed Layer；
Fig. 5 be this utility model the first Seed Layer glazing carve to be formed the first metal reroute, the first inductance wiring and the
The generalized section of one capacitance wiring；
Fig. 6 is that this utility model forms the second insulating barrier on the first metal line and makes the section of insulating layer openings and shows
It is intended to；
Fig. 7 is that whole face deposits the generalized section after second sublayer to this utility model over the second dielectric；
Generalized sections of the Fig. 8 for this utility model coating photoresist in second sublayer；
Fig. 9 be this utility model second sublayer glazing carve to be formed the second metal reroute, the second inductance wiring and the
The generalized section of two capacitance wirings；
Figure 10 is that this utility model forms protective layer on the second metal line and makes the section signal of protective layer opening
Figure；
Figure 11 is the generalized section (dotted line cutaway along Figure 12) after this utility model forms soldered ball；
Schematic perspective views of the Figure 12 for 1 vertical stratification inductance capacitance of this utility model embodiment；
Generalized sections of the Figure 13 for 2 horizontal structure inductance capacitance of this utility model embodiment；
Schematic top plan views of the Figure 14 for 2 horizontal structure inductance capacitance of this utility model embodiment；
With reference to accompanying drawing, make the following instructions：
1 --- silicon substrate 101 --- first surface
102 --- second surface 103 --- groove
2 --- chip 201 --- weld pad
3 --- cohere glue
4 --- the first insulating barrier 401 --- first insulating layer openings
5 --- the first Seed Layer 501 --- first metal is rerouted
502 --- the first inductance wiring 503 --- first capacitance wiring
6 --- photoresist 7 --- second insulating barrier
701 --- the second insulating layer openings 8 --- second sublayer
Second inductance is connected up 801 --- the second metal reroutes 802 ---
803 --- the second capacitance wiring 9 --- photoresist
10 --- protective layer 1001 --- protective layer opening
11 --- soldered ball/salient point
Specific embodiment
In order to be more clearly understood that technology contents of the present utility model, describe in detail especially exemplified by following examples, its mesh
Be only that and be best understood from content of the present utility model and unrestricted protection domain of the present utility model.The structure of embodiment accompanying drawing
In each ingredient do not press normal rates scaling, therefore do not represent the actual relative size of each structure in embodiment.It is wherein described
, there be the situation of other layers above structure or face or upside comprising centre.
Embodiment 1
As is illustrated by figs. 11 and 12, a kind of chip-packaging structure for slowing down electromagnetic interference, including silicon substrate 1 and chip
2, the silicon substrate has first surface 101 and second surface corresponding thereto 102, and at least one is formed with the first surface
The individual subsidence trough 103 towards second surface, the subsidence trough be preferably straight trough or side wall and bottom surface angle 80～120 it is oblique
Groove, is not limited here.The present embodiment schematic diagram is straight trough shape.An at least chips 2 can be placed in the subsidence trough, this
To placed a chips in embodiment, and the chip front side is close to the first surface；Specifically, the chip back leads to
Cross and the attachment of glue 3 is cohered to the bottom land of the subsidence trough, realize the attachment of chip, with more preferable fixed chip, prevent chip inclined
Move.The chip front side includes weld pad 201；Between the chip the week side of boss and subsidence trough side wall, the chip front side
And on the first surface, it is formed with the first insulating barrier 4；The first metal is formed with first insulating barrier and reroutes 501, the
One inductance connects up the 502, first capacitance wiring 503, and first metal reroutes described through first insulating barrier electrical connection
The weld pad of chip, first metal is rerouted, first inductance wiring, to be formed with second on first capacitance wiring exhausted
Edge layer 7, is formed with the second metal and reroutes the wiring 802 of the 801, second inductance and the second capacitance wiring on second insulating barrier
803, second metal is rerouted and electrically connects the first metal rewiring, first inductance through second insulating barrier
Between each circuit of wiring, between each circuit of second inductance wiring, the circuit of first inductance wiring and described the
Inductance wiring is continuously detoured into by broken line mode between the circuit of two inductance wiring, and it is parallel or close parallel between each circuit,
Dielectric layer is provided with referring between the first capacitance wiring described in Figure 12 and second capacitance wiring；First inductance wiring and second
Inductance wiring constitutes inductance wiring, the first capacitance wiring and the second capacitance wiring and constitutes capacitance wiring；Inductance wiring, electric capacity
Wiring is electrically connected with the weld pad of chip；Second metal is rerouted, second inductance is connected up, second capacitance wiring
On be coated with protective layer 10, during second metal is rerouted, at least one circuit extends to the silicon substrate outside the chip area
In plate surface；Second metal reroutes the soldered ball/salient point 11 being connected with through the protective layer.
Preferably, the first capacitance wiring and the second capacitance wiring are equivalently-sized metal derby.
Preferably, the distance between the side wall of the subsidence trough and described chip are more than 1 micron, to facilitate chip to be put into
The bottom land of subsidence trough.
Preferably, the distance between the bottom land of the subsidence trough and second surface of the silicon substrate are more than 1 micron, with
Beneficial to support of the silicon substrate to chip.
Preferably, the material of first insulating barrier and second insulating barrier is polymer latex.To improve packaging body
Reliability, addition of vacuum coating makes to fill the full polymer latex in subsidence trough the gap in, with fixed chip, while ensureing absolutely
Edge performance.
Preferably, the glue that coheres is non-conductive polymer glue or thin film, and adhering chip is in the bottom land of subsidence trough, it is ensured that
In ensuing technique, chip position does not shift, and in order to obtain preferable alignment precision, acquisition is thinner to be connected up again
Lines.Polymer latex can be by preparing in chip die backsize mode, and thin film can be by pressing at the chip die back side
It is prepared by film mode.
Optionally, between the wiring of the first inductance and the first capacitance wiring, or the wiring of the second inductance and the second capacitance wiring, root
Can connect or be not connected to according to encapsulated circuit design.
As a kind of preferred embodiment, as shown in figure 12, be the wiring of the first inductance and the wiring of the second inductance it is upper and lower it is parallel around
OK, and in the horizontal direction extend in parallel.In other embodiment, as long as the wiring of the first inductance and the second inductance connect up to unroll
OK, when in inductance wiring, electric current changes, the magnetic field of surrounding also produces respective change.
The assembled package structure of inductance wiring of the present embodiment for vertical arrangement and the capacitance wiring of vertical arrangement, which can be compared with
Good is applied to the larger application scenario of inductance capacitance.
As a kind of preferred embodiment, for slow down the chip-packaging structure of electromagnetic interference manufacture method as follows
Implement：
Step 1. is referring to Fig. 1, there is provided one has first surface 101 and 102 silicon substrate disc of second surface corresponding thereto,
At least one subsidence trough 103 towards second surface is formed with the first surface, at least one chip, 2 back side is pasted down
The bottom land of the subsidence trough is attached to, the chip front side is concordant with the silicon substrate first surface or is close to concordant, the core
Piece front includes weld pad 201；
Optionally, the chip is cohered by cohering glue 3 or dry film with the subsidence trough bottom land.More excellent, cohere glue
Or dry film is non-conductive polymer glue or thin film, adhering chip and subsidence trough bottom surface.
Preferably, the shape of the subsidence trough can be trapezoidal, rectangle or other geometries.
Referring to Fig. 2, by coating or press mold technique, it is recessed with the sinking that one layer of formation covers the chip side wall to step 2.
First insulating barrier 4 in space, the first surface of the silicon substrate disk and the chip front side between groove, and described first
The first insulating layer openings 401, the positive weld pad of exposed chip 201 are made on insulating barrier at the pad locations of correspondence chip；
Optionally, the material of first insulating barrier be silicon dioxide, silicon nitride, the one kind in insulating material of polymer.
Preferably, the preparation of first insulating barrier is deposited using low temperature chemical vapor or polymer spraying or polymer rotation
The method of painting.
Optionally, the exposed mode of weld pad for alloing chip be etch, cut in one kind, when the material of the first insulating barrier
When matter is photoactive material, the weld pad of chip can be made to come out by photoetching process, photoetching process is mainly including photoresist
The operations such as coating, exposure, development.In the present embodiment, the weld pad of chip is made to come out by exposure imaging.
It is electric that step 3. forms the 501, first inductance of the rewiring wiring 502 and first of the first metal on first insulating barrier
Hold wiring 503, first metal reroutes the weld pad that the chip is electrically connected through first insulating barrier.
Specifically, as shown in figure 3, whole face deposition the first Seed Layer 5 forms the side of the first Seed Layer on the first insulating barrier
Formula can be physical vapor deposition.The material of the first Seed Layer can be in Ni/Au, CrW/Cu, Ti/W/Cu/Ni/Au, Ti/Cu
One kind.
As shown in figure 4, in the first Seed Layer coating photoresist 6, and default first gold medal is exposed by photoetching process
Category is rerouted, the first inductance is connected up, the line pattern of the first capacitance wiring.Photoetching process mainly includes the coating of photoresist 6, exposes
Light, development etc. are operated.
As shown in figure 5, forming metallic circuit by electroplating or changing plating mode on the line pattern for exposing, finally remove
Seed Layer outside line pattern, forms the rewiring of the first metal, the wiring of the first inductance, the first capacitance wiring.
Optionally, the first metal reroute, the first inductance wiring, the first capacitance wiring, material type include titanium, chromium, tungsten,
One or more in copper, aluminum.
Preferably, the first metal of formation is rerouted, the first inductance is connected up, the method for the first capacitance wiring is vacuum evaporation
One kind in method, physical vaporous deposition.One layer is laid in the present embodiment, has been physical vapour deposition (PVD) by the way of, then
Formed using wet etching, other embodiment can lay multiple structure.Per Rotating fields material be aluminum, nickel, nickel phosphorus, silver, copper,
One kind in cobalt, gold, palladium.More excellent, outermost metal is the metal with anti-oxidation effect, such as the one kind in silver, gold, palladium.
Preferably, the thickness that first metal is rerouted is more than 0.2 micron.The thickness is to strengthen the first metal to reroute
The preferred forms of the reliability being connected with weld pad, naturally it is also possible to be other thickness.
Step 4. referring to Fig. 6, by coating or press mold technique, formed one layer cover first metal reroute, it is described
The second insulating barrier 7 in the wiring of first inductance, first capacitance wiring, and in first metal rewiring, the first inductance
The second insulating layer openings are made at wiring.The material of second insulating barrier can be polymeric media material, and its material can be with the
One insulating layer material is identical.
Preferably, the dielectric constant of the second insulating barrier material is determined according to the inductance, electric capacity imbedded；
Preferably, the thickness of second insulating barrier is determined according to the electric capacity, inductive nature and shape imbedded.
It is electric that step 5. forms the 801, second inductance of the rewiring wiring 802 and second of the second metal on second insulating barrier
Hold wiring 803, second metal reroutes and first metal electrically connected through second insulating barrier and reroute, described the
Excessively described second insulating barrier of partial line Reuter of two inductance wiring electrically connects the part circuit of the first inductance wiring, makes first
Inductance is connected up and the wiring of the second inductance is constituted and continuously detours into inductance wiring, and at least one in rerouting second metal
Bar circuit is extended on the silicon substrate outside the chip area.Specifically, referring to Fig. 7, Fig. 8, Fig. 9 (with Fig. 3's to Fig. 5
Making step is the same), as shown in fig. 7, making at least one of which in second insulating layer connects the first metal weight cloth
Line and second sublayer 8 of the first inductance wiring；
As shown in figure 8, polymer latex is formed in second sublayer, and the second metal weight is formed by photoetching process
Wiring, the wiring of the second inductance, the line pattern of the second capacitance wiring.Photoetching process includes the coating of photoresist 9, exposure, development
Deng operation.As shown in figure 9, being formed on line pattern, the second metal is rerouted, the second inductance is connected up and the second capacitance wiring.
Preferably, it is identical that the material that second metal is rerouted can reroute material with the first metal.
Step 6. is rerouted referring to Figure 10 and Figure 11, in the second metal, the wiring of the second inductance, on the second capacitance wiring on make
Make protective layer 10, and reserve thereon to do salient point or plant the position of soldered ball and form protective layer opening 1001, and open in the protective layer
Conductive structure (soldered ball or salient point) is formed at mouthful；
Optionally, the material of the protective layer is polymer latex, and its material can be with the first insulating barrier and the second insulating barrier material
Matter can be with identical.
Step 7. carries out scribing to silicon substrate disc, and forming monolithic is used to slow down the chip-packaging structure of electromagnetic interference.
Embodiment 2
As shown in Figure 13 and Figure 14, a kind of chip-packaging structure for slowing down electromagnetic interference, including silicon substrate 1 and chip
2, silicon substrate has first surface 101 and second surface corresponding thereto 102, is formed with least one towards the on first surface
The subsidence trough 103 on two surfaces, at least one chip back mount the bottom land of the subsidence trough down, and chip front side is included
There is weld pad 201；The first insulating barrier 4 is formed between chip the week side of boss and subsidence trough side wall, on chip front side and first surface；The
The the first inductance wiring 502, middle ware for the first metal rewiring 501 is formed with one insulating barrier, continuously detouring is separated with electrolyte
At least two first capacitance wirings 503 of layer, the first metal is rerouted, the wiring of the first inductance and the first capacitance wiring pass through first
Insulating barrier electrically connects the weld pad of chip；First metal is rerouted, the wiring of the first inductance, be coated with protective layer on the first capacitance wiring
10, during the first metal is rerouted, at least one circuit is extended on the silicon substrate outside chip area；First metal
Soldered ball/the salient point 11 through the protective layer is connected with rewiring.
Optionally, the wiring of the first inductance and the first capacitance wiring can connect or be not connected to according to encapsulated circuit design.
The assembled package structure of inductance wiring of the present embodiment for horizontal arrangement and the capacitance wiring of horizontal arrangement, which can be compared with
Good is applied to the less application scenario of inductance, electric capacity.
In other embodiments, the inductance wiring of chip surface and capacitance wiring can also be vertical stratification and horizontal structure
Combination, such as, the capacitance wiring assembled package of vertical inductance wiring and level, or inductance wiring and the vertical electricity of level
Hold wiring combination encapsulation.
To sum up, this utility model is used for the chip-packaging structure for slowing down electromagnetic interference, by making on a silicon substrate
Groove, and chip front side weld pad is imbedded into subsidence trough upward, so, encapsulated space is saved, and silicon substrate can make essence
Thin wires, are connected up by the inductance of horizontal arrangement or vertical arrangement is formed with chip front side and silicon substrate first surface, and
The capacitance wiring of horizontal arrangement or vertical arrangement is formed with first insulating barrier, the first metal is rerouted or the second metal weight
Wiring and soldered ball are extended on silicon substrate, are realized and electrically fan out to chip pad silicon substrate, improve encapsulation
Reliability, process is simple, low cost；The inductance wiring of horizontal arrangement or vertical arrangement constitutes inductance, and horizontal arrangement or vertical
The capacitance wiring of arrangement and therebetween dielectric layer constitute electric capacity, and the inductance with filtering characteristic and electric capacity can slow down chip internal
The crosstalk of signal between circuit, filters the unwanted signal of telecommunication, strengthens the reliability and performance of encapsulating products, while reducing into
This.
Above example is referring to the drawings, preferred embodiment of the present utility model to be described in detail.The skill of this area
Art personnel by modification or change on various forms are carried out to above-described embodiment, but without departing substantially from substantive feelings of the present utility model
Under condition, all fall within protection domain of the present utility model.
Claims (9)
1. a kind of chip-packaging structure for slowing down electromagnetic interference, it is characterised in that including silicon substrate (1) and chip (2), institute
State silicon substrate and there is first surface (101) and second surface (102) corresponding thereto, on the first surface, be formed with least one
The individual subsidence trough (103) towards second surface, chip back described at least one mount the groove of the subsidence trough down
Bottom, the chip front side include weld pad (201)；Between the chip the week side of boss and subsidence trough side wall, the chip just
The first insulating barrier (4) is formed with face and the first surface；Horizontal arrangement or vertical row are formed with first insulating barrier
The inductance wiring of cloth, and the capacitance wiring of horizontal arrangement or vertical arrangement on first insulating barrier, is formed with, described first is exhausted
Be also formed with rerouting the chip pad electrically derived metal in edge layer, the inductance wiring, the capacitance wiring with
The weld pad of the chip is electrically connected with.
2. the chip-packaging structure for slowing down electromagnetic interference according to claim 1, it is characterised in that：Described first is exhausted
Be formed with edge layer the first metal reroute (501), the first inductance wiring (502), the first capacitance wiring (503), described first
Metal reroutes the weld pad that the chip is electrically connected through first insulating barrier, and first metal is rerouted, described first
The second insulating barrier (7) is formed with inductance wiring, first capacitance wiring, on second insulating barrier, the second metal is formed with
Reroute (801), the second inductance wiring (802) and the second capacitance wiring (803), second metal is rerouted and passes through described the
Two insulating barriers electrically connect first metal and reroute, between each circuit of the first inductance wiring, the second inductance cloth
By broken line mode between each circuit of line, between the circuit of first inductance wiring and the circuit of second inductance wiring
Inductance wiring is detoured into continuously, and parallel or close parallel between each circuit, first capacitance wiring and the second electric capacity cloth
Dielectric layer is provided between line；Second metal is rerouted, second inductance wiring, cover on second capacitance wiring
Matcoveredn (10), during second metal is rerouted, at least one circuit extends to the silicon substrate table outside the chip area
On face.
3. the chip-packaging structure for slowing down electromagnetic interference according to claim 1, it is characterised in that：Described first is exhausted
The first inductance for the first metal rewiring (501) is formed with edge layer, continuously detouring connects up (502), middle ware and is separated with electrolyte
At least two first capacitance wirings (503) of layer, first metal is rerouted, the wiring of the first inductance and the first capacitance wiring are saturating
Cross the weld pad that first insulating barrier electrically connects the chip；First metal is rerouted, first inductance is connected up, described
Protective layer (10) is coated with first capacitance wiring, at least one circuit extends to the core during first metal is rerouted
On the overseas silicon substrate in section.
4. the chip-packaging structure for slowing down electromagnetic interference according to claim 1, it is characterised in that：Described first is electric
It is equivalently-sized metal derby to hold wiring and the second capacitance wiring.
5. the chip-packaging structure for slowing down electromagnetic interference according to claim 2, it is characterised in that described first is exhausted
The material of edge layer and second insulating barrier is polymer latex.
6. the chip-packaging structure for slowing down electromagnetic interference according to claim 2, it is characterised in that second gold medal
Category reroutes the soldered ball/salient point (11) being connected with through the protective layer.
7. the chip-packaging structure for slowing down electromagnetic interference according to claim 1, it is characterised in that the chip back of the body
By cohering glue (3) attachment to the bottom land of the subsidence trough, the thickness for cohering glue is less than 50 microns, more than 1 micron in face.
8. the chip-packaging structure for slowing down electromagnetic interference according to claim 1, it is characterised in that embedment is with once
The number of chips of heavy groove is more than or equal to 2.
9. the chip-packaging structure for slowing down electromagnetic interference according to claim 1, it is characterised in that first gold medal
The thickness that category is rerouted is more than 0.2 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621015002.9U CN206076221U (en) | 2016-08-31 | 2016-08-31 | For slowing down the chip-packaging structure of electromagnetic interference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621015002.9U CN206076221U (en) | 2016-08-31 | 2016-08-31 | For slowing down the chip-packaging structure of electromagnetic interference |
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| Publication Number | Publication Date |
|---|---|
| CN206076221U true CN206076221U (en) | 2017-04-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201621015002.9U Expired - Fee Related CN206076221U (en) | 2016-08-31 | 2016-08-31 | For slowing down the chip-packaging structure of electromagnetic interference |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106169428A (en) * | 2016-08-31 | 2016-11-30 | 华天科技（昆山）电子有限公司 | For slowing down chip-packaging structure and the method for packing of electromagnetic interference |
| US10790225B1 (en) | 2019-03-29 | 2020-09-29 | Shanghai Avic Opto Electronics Co., Ltd. | Chip package structure and chip package method including bare chips with capacitor polar plate |
| CN111837324A (en) * | 2020-01-19 | 2020-10-27 | 深圳市汇顶科技股份有限公司 | Charge pump circuit, chip and electronic equipment |
| CN113281853A (en) * | 2020-02-19 | 2021-08-20 | 青岛海信宽带多媒体技术有限公司 | Optical module |
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2016
- 2016-08-31 CN CN201621015002.9U patent/CN206076221U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106169428A (en) * | 2016-08-31 | 2016-11-30 | 华天科技（昆山）电子有限公司 | For slowing down chip-packaging structure and the method for packing of electromagnetic interference |
| CN106169428B (en) * | 2016-08-31 | 2018-08-31 | 华天科技（昆山）电子有限公司 | Chip-packaging structure for slowing down electromagnetic interference and packaging method |
| US10790225B1 (en) | 2019-03-29 | 2020-09-29 | Shanghai Avic Opto Electronics Co., Ltd. | Chip package structure and chip package method including bare chips with capacitor polar plate |
| CN111837324A (en) * | 2020-01-19 | 2020-10-27 | 深圳市汇顶科技股份有限公司 | Charge pump circuit, chip and electronic equipment |
| CN111837324B (en) * | 2020-01-19 | 2024-02-13 | 深圳市汇顶科技股份有限公司 | Charge pump circuit, chip and electronic equipment |
| CN113281853A (en) * | 2020-02-19 | 2021-08-20 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN113281853B (en) * | 2020-02-19 | 2023-01-20 | 青岛海信宽带多媒体技术有限公司 | Optical module |
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