CN206040632U - 一种超薄贴片二极管 - Google Patents

一种超薄贴片二极管 Download PDF

Info

Publication number
CN206040632U
CN206040632U CN201621012092.6U CN201621012092U CN206040632U CN 206040632 U CN206040632 U CN 206040632U CN 201621012092 U CN201621012092 U CN 201621012092U CN 206040632 U CN206040632 U CN 206040632U
Authority
CN
China
Prior art keywords
lead
chip
lead wire
ultra
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201621012092.6U
Other languages
English (en)
Inventor
于林
杨宏民
赵卫华
马博洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Henan Crown Electronic Polytron Technologies Inc
Original Assignee
Henan Crown Electronic Polytron Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Henan Crown Electronic Polytron Technologies Inc filed Critical Henan Crown Electronic Polytron Technologies Inc
Priority to CN201621012092.6U priority Critical patent/CN206040632U/zh
Application granted granted Critical
Publication of CN206040632U publication Critical patent/CN206040632U/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

本实用新型涉及贴片二极管生产技术领域,具体涉及一种超薄贴片二极管,在不改变原有贴片二极管性能及封装厚度的情况下,减少贴片二极管的空间体积。为了达到上述目的,本实用新型是通过以下技术方案实现的:一种超薄贴片二极管,包括芯片、引线一、封装体和引线二,引线一和引线二分别焊接在芯片上下两个表面,封装体将芯片、引线一和引线二的焊接端密封包裹,引线一和引线二的自由端伸出封装体外,所述芯片倾斜设置,引线一与引线二的焊接端分别呈倾斜的尖角状,即引线一与引线二的焊接端一面平直、另一面倾斜,倾斜角度与芯片倾斜角度一致。

Description

一种超薄贴片二极管
技术领域
本实用新型涉及贴片二极管生产技术领域,具体涉及一种超薄贴片二极管。
背景技术
贴片二极管又称晶体二极管,简称二极管(diode),另外,还有早期的真空电子二极管;它是一种具有单向传导电流的电子器件。在半导体二极管内部有一个PN结两个引线端子,这种电子器件按照外加电压的方向,具备单向电流的转导性。一般来讲,贴片晶体二极管是一个由p型半导体和n型半导体烧结形成的p-n结界面。在其界面的两侧形成空间电荷层,构成自建电场。当外加电压等于零时,由于p-n 结两边载流子的浓度差引起扩散电流和由自建电场引起的漂移电流相等而处于电平衡状态,这也是常态下的二极管特性。
现有技术中,贴片二极管的加工是将两根引线夹住芯片进行焊接,然后通过玻封的形式,将芯片进行封装,使得本体外形多为圆柱形,占用空间体积较大,导致原材料浪费严重,而且难以适应客户端小型化发展趋势。随着塑封二极管的出现,很大程度上降低了二极管的空间体积,而二极管中的引线以及芯片为上下层叠式设计,随着科技的快速发展,贴片二极管的空间体积变得更为重要,越薄的贴片二极管越会得到市场及大众厂家的欢迎。
发明内容
鉴于此,本实用新型提供一种超薄贴片二极管,在不改变原有贴片二极管性能及封装厚度的情况下,减少贴片二极管的空间体积。
为了达到上述目的,本实用新型是通过以下技术方案实现的:
一种超薄贴片二极管,包括芯片、引线一、封装体和引线二,引线一和引线二分别焊接在芯片上下两个表面,封装体将芯片、引线一和引线二的焊接端密封包裹,引线一和引线二的自由端伸出封装体外,所述芯片倾斜设置,引线一与引线二的焊接端分别呈倾斜的尖角状,即引线一与引线二的焊接端一面平直、另一面倾斜,倾斜角度与芯片倾斜角度一致。
所述芯片倾斜角度为10°至40°。
所述引线一与引线二通过锡焊焊接在芯片的上下两个表面。
所述芯片为O/J芯片或GPP芯片。
所述引线一的整体形状为Z型。
本实用新型的有益效果是:芯片采用倾斜设计,两引线的焊接端也采用倾斜的匹配方式,这样的焊接方式会在厚度上吸收掉芯片本身的厚度,在芯片和引线的结构以及封装厚度不改变、焊接接触面积不改变的情况下,减小贴片二极管的空间体积,同时贴片二极管的性能不受影响。
附图说明:
图1为本实用新型总体结构示意图;
图2为原有贴片二极管的结构示意图;
图3为本实用新型与原有贴片二极管的对比图;
具体实施方式:
依照以下的附图详细说明关于本实用新型的示例性实施例。
图中序号所代表的含义为:1-引线一,2-引线二,3-芯片,4-封装体,5-锡焊。
以下结合具体情况说明本实用新型的示例性实施例:
如图1所示的一种超薄贴片二极管,包括芯片3、引线一1、封装体4和引线二2,引线一1和引线二2分别焊接在芯片3上下两个表面,封装体4将芯片3、引线一1和引线二2的焊接端密封包裹,引线一1和引线二2的自由端伸出封装体4外,所述芯片3倾斜设置,引线一1与引线二2的焊接端分别呈倾斜的尖角状,即引线一1与引线二2的焊接端一面平直、另一面倾斜,倾斜角度与芯片3倾斜角度一致。
所述芯片3倾斜角度为10°至40°。
所述引线一1与引线二2通过锡焊5焊接在芯片3的上下两个表面。
所述芯片3为O/J芯片或GPP芯片。O/J是OPEN JUNCTION的晶圆扩散工艺,在晶圆扩散后切片成晶粒,晶粒的边缘是粗糙的,电性能不稳定,需要用混合酸(洗掉边缘,然后包以硅胶并封装成型,可信赖性较差。GPP是Glassivation passivation parts的缩写,是玻璃钝化类器件的统称,该产品就是在现有产品普通硅整流扩散片的基础上对拟分割的管芯P/N结面四周烧制一层玻璃,玻璃与单晶硅有很好的结合特性,使P/N结获得最佳的保护,免受外界环境的侵扰,提高器件的稳定性,可信赖性极佳。
所述引线一1的整体形状为Z型。
原有贴片二极管的结构如图2所示,引线一、芯片、引线二上下层叠焊接,焊接后整体厚度为两个引线厚度、芯片厚度、两层锡焊厚度之和,而本实用新型的焊接后的整体厚度仅为两个引线厚度之和,如图3所示,在不改变芯片、引线、封装厚度的情况下进行对比,虚线代表原有贴片二级管,实线代表本实用新型。
以上所述仅为本实用新型示意性的具体实施方式,并非用以限定本实用新型的范围,任何本领域的技术人员在不脱离本实用新型构思和原则的前提下所做出的等同变化与修改,均应属于本实用新型保护的范围。

Claims (5)

1.一种超薄贴片二极管,包括芯片、引线一、封装体和引线二,引线一和引线二分别焊接在芯片上下两个表面,封装体将芯片、引线一和引线二的焊接端密封包裹,引线一和引线二的自由端伸出封装体外,其特征在于,所述芯片倾斜设置,引线一与引线二的焊接端分别呈倾斜的尖角状,即引线一与引线二的焊接端一面平直、另一面倾斜,倾斜角度与芯片倾斜角度一致。
2.根据权利要求1所述的超薄贴片二极管,其特征在于,所述芯片倾斜角度为10°至40°。
3.根据权利要求1所述的超薄贴片二极管,其特征在于,所述引线一与引线二通过锡焊焊接在芯片的上下两个表面。
4.根据权利要求1所述的超薄贴片二极管,其特征在于,所述芯片为O/J芯片或GPP芯片。
5.根据权利要求1所述的超薄贴片二极管,其特征在于,所述引线一的整体形状为Z型。
CN201621012092.6U 2016-08-31 2016-08-31 一种超薄贴片二极管 Expired - Fee Related CN206040632U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201621012092.6U CN206040632U (zh) 2016-08-31 2016-08-31 一种超薄贴片二极管

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201621012092.6U CN206040632U (zh) 2016-08-31 2016-08-31 一种超薄贴片二极管

Publications (1)

Publication Number Publication Date
CN206040632U true CN206040632U (zh) 2017-03-22

Family

ID=58300378

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201621012092.6U Expired - Fee Related CN206040632U (zh) 2016-08-31 2016-08-31 一种超薄贴片二极管

Country Status (1)

Country Link
CN (1) CN206040632U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112700728A (zh) * 2019-10-23 2021-04-23 Oppo广东移动通信有限公司 显示模组及电子设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112700728A (zh) * 2019-10-23 2021-04-23 Oppo广东移动通信有限公司 显示模组及电子设备

Similar Documents

Publication Publication Date Title
CN206040632U (zh) 一种超薄贴片二极管
CN201752013U (zh) 芯片与无源器件直接置放多圈引脚方式封装结构
CN207367964U (zh) 引线框架阵列及封装体
CN203733783U (zh) 一种引线框架
CN205984941U (zh) 一种使用高耐湿性肖特基势垒芯片的功率二极管
CN201681936U (zh) 无基岛无源器件封装结构
CN208706626U (zh) 一种半导体晶圆封装结构
CN201681903U (zh) 基岛露出型及下沉基岛露出型无源器件封装结构
CN206388679U (zh) 用于快速评估快恢复二极管性能的基座
CN201717265U (zh) 一种双向保护二极管芯片
CN201752004U (zh) 芯片直接置放封装结构
CN201681877U (zh) 下沉基岛露出型封装结构
CN213304105U (zh) 一种半导体二极管器件封装结构
CN205985005U (zh) 一种使用弱电检测装置的整流二极管
CN201681933U (zh) 芯片与无源器件直接置放引脚方式封装结构
CN201681935U (zh) 无基岛多圈脚静电释放圈无源器件封装结构
TWI408827B (zh) 建材一體型太陽光電模組的封裝方法及其結構
CN201681908U (zh) 基岛露出及多凸点基岛露出型多圈引脚无源器件封装结构
CN201681857U (zh) 多个多凸点基岛露出型单圈引脚封装结构
CN107170728A (zh) 一种恒流二极管设计与制造技术
CN201681842U (zh) 单基岛露出型多圈引脚引线框结构
CN204696112U (zh) 引线框
CN201681914U (zh) 下沉基岛及多凸点基岛露出型无源器件封装结构
CN201681876U (zh) 多凸点基岛露出型封装结构
CN201681874U (zh) 基岛露出型封装结构

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170322

Termination date: 20200831