CN206021242U - The FPGA programs configuration controlled based on CPLD and firmware encrypting system - Google Patents
The FPGA programs configuration controlled based on CPLD and firmware encrypting system Download PDFInfo
- Publication number
- CN206021242U CN206021242U CN201620491354.5U CN201620491354U CN206021242U CN 206021242 U CN206021242 U CN 206021242U CN 201620491354 U CN201620491354 U CN 201620491354U CN 206021242 U CN206021242 U CN 206021242U
- Authority
- CN
- China
- Prior art keywords
- cpld
- fpga
- flash
- cpld chips
- controlled based
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model discloses a kind of FPGA programs configuration controlled based on CPLD and firmware encrypting system, including communication module, CPLD chips, FLASH and FPGA, the output end of the communication module is electrically connected with the communication interface of the CPLD chips, the storage end of the CPLD chips is electrically connected with the FLASH ends, and the configuration end of the CPLD chips is electrically connected with the FPGA.The configuration of FPGA programs and firmware encrypting system that the utility model is controlled based on CPLD have received the firmware program data of host computer transmission by communication module, after being encrypted through CPLD chips, FLASH is arrived in storage, after system electrification, encryption data is read from FLASH by CPLD chips, and FPGA is configured after being decrypted.
Description
Technical field
The utility model is related to firmware program configuration system, more particularly to a kind of FPGA programs configuration controlled based on CPLD
And firmware encrypting system.
Background technology
For improving Consumer's Experience, reduce product after-sales service difficulty and cost, the upgrading of remote hardware program is essential
, while needing to be encrypted firmware program, to prevent remaining producer from cracking product, traditional maintenance upgrade data are equal
It is that directly download firmware to FPGA configuration chips as debugging and firmware program download interface using JATG/AS interfaces,
After system electrification, FPGA adopts active configuration mode, and by FPGA device boot configuration operating process, it controls external memory storage
And initialization procedure, readout data signal is actively sent from configuration device EPCS, so as to the data EPCS are read in FPGA, real
Existing programmed configurations to FPGA；But upgrade maintenance mode at this stage cannot carry out remote online upgrading, and the number to firmware
Relatively low according to encryption Chengdu, product after-sales service is difficult.
Utility model content
The purpose of this utility model is that to solve the above problems and provides a kind of FPGA journeys controlled based on CPLD
Sequence configuration and firmware encrypting system.
The utility model is achieved through the following technical solutions above-mentioned purpose：
A kind of based on CPLD control FPGA programs configuration and firmware encrypting system, including communication module, CPLD chips,
FLASH and FPGA, the output end of the communication module are electrically connected with the communication interface of the CPLD chips, the CPLD chips
Storage end is electrically connected with the FLASH ends, and the configuration end of the CPLD chips is electrically connected with the FPGA.
Specifically, the communication module is connected with host computer by radio network interface/serial line interface/SPI interface.
Preferably, model EPM570T100 of the CPLD chips, the model of the FLASH
S25FL256SAGMFI001, the FPGA are PS configuration pattern.
The beneficial effects of the utility model are：
The configuration of FPGA programs and firmware encrypting system that the utility model is controlled based on CPLD is have received by communication module
The firmware program data that host computer sends, storage after being encrypted through CPLD chips arrive FLASH, after system electrification, CPLD chips
Encryption data is read from FLASH, and FPGA is configured after being decrypted.
Description of the drawings
Fig. 1 is the structural frames of the FPGA programs configuration controlled based on CPLD described in the utility model and firmware encrypting system
Figure.
Specific embodiment
The utility model is described in further detail below in conjunction with the accompanying drawings：
As shown in figure 1, a kind of FPGA programs configuration controlled based on CPLD of the utility model and firmware encrypting system, including
Communication module, CPLD chips, FLASH and FPGA, the output end of communication module are electrically connected with the communication interface of CPLD chips, CPLD
The storage end of chip is electrically connected with FLASH ends, and the configuration end of CPLD chips is electrically connected with FPGA, and communication module passes through wireless network
Interface/serial line interface/SPI interface is connected with host computer, model EPM570T100 of CPLD chips, the model of FLASH
S25FL256SAGMFI001, FPGA are PS configuration pattern.
The configuration of FPGA programs and the operation principle of firmware encrypting system that the utility model is controlled based on CPLD is as follows：
Using CPLD chips as main control chip, host computer is received by radio network interface/serial line interface/SPI interface etc.
Firmware program data, by radio network interface can long-range receiving data, realize remote firmware updating, by serial line interface
Short range receiving data can be realized with wireline interfaces such as SPI interfaces, and stored after the hardware algorithm encryption of CPLD chip internals
To in FLASH, after each system electrification, encryption data is read from FLASH by CPLD chips, and hard through the inside of CPLD chips
After the decryption of part algorithm, FPGA is configured by the PS patterns (PS configuration pattern) of FPGA.
Model EPM570T100 of CPLD chips, is non-volatile memory chip, and with multiple advantages, low cost is low
Power consumption, standby current as little as 29uA；Instantaneous upper electricity, the up to non-volatile memory of 8Kbits, strong security；Press I/O interfaces more,
Support 3.3v, 2.5v, 1.8v, and 1.5v logic level；Bus-type framework, including programmable transition speed, drives intensity and can
Programming pull-up resistor, and the program Solidification of CPLD is entered CPLD chips in the present system, the firmware program in CPLD is to read
Go out, AES and decipherment algorithm are realized it being feasible in CPLD using this.
Model S25FL256SAGMFI001 of FLASH, is 256 megabits of flash non-volatile storages, and program rate reaches
The page programming buffering of the bytes of 1.5Mbytes/s, 256 or 512, erasing speed store two in FLASH up to 0.65Mbytes/s
Individual FPGA programs, one be stand-by program, one be system operation programs, stand-by program only working procedure load failure
Just in the case of enable, in order to prevent remote online program storage failure in the case of, product also normally can start, can continue grasp
Make.
The PS patterns of FPGA are PS configuration pattern, by outer computer or controller control configuration process.Pass through
Completing, CPLD chips, are write data into FPGA as memory as control device for peripheral control unit and memory
In FPGA, the programming to FPGA is realized.The pattern can be realized to FPGA online programmables.
The technical solution of the utility model is not limited to the restriction of above-mentioned specific embodiment, every according to skill of the present utility model
The technology deformation that art scheme is made, each falls within protection domain of the present utility model.
Claims (3)
1. a kind of FPGA programs controlled based on CPLD are configured and firmware encrypting system, it is characterised in that：Including communication module,
CPLD chips, FLASH and FPGA, the output end of the communication module are electrically connected with the communication interface of the CPLD chips, described
The storage end of CPLD chips is electrically connected with the FLASH ends, and the configuration end of the CPLD chips is electrically connected with the FPGA.
2. the FPGA programs controlled based on CPLD according to claim 1 are configured and firmware encrypting system, it is characterised in that：
The communication module is connected with host computer by radio network interface/serial line interface/SPI interface.
3. the FPGA programs controlled based on CPLD according to claim 1 are configured and firmware encrypting system, it is characterised in that：
Model EPM570T100 of the CPLD chips, model S25FL256SAGMFI001 of the FLASH, the FPGA is
PS configuration pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620491354.5U CN206021242U (en) | 2016-05-25 | 2016-05-25 | The FPGA programs configuration controlled based on CPLD and firmware encrypting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620491354.5U CN206021242U (en) | 2016-05-25 | 2016-05-25 | The FPGA programs configuration controlled based on CPLD and firmware encrypting system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206021242U true CN206021242U (en) | 2017-03-15 |
Family
ID=58241145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620491354.5U Active CN206021242U (en) | 2016-05-25 | 2016-05-25 | The FPGA programs configuration controlled based on CPLD and firmware encrypting system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206021242U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107341034A (en) * | 2017-07-02 | 2017-11-10 | 中国航空工业集团公司雷华电子技术研究所 | A kind of structure and method that FPGA program curings are updated using UART interface |
| CN108763114A (en) * | 2018-07-23 | 2018-11-06 | 无锡航天江南数据系统科技有限公司 | A kind of cipher card and its working method based on PCIe104 interfaces |
| CN109255258A (en) * | 2018-08-27 | 2019-01-22 | 重庆天箭惯性科技股份有限公司 | Encrypt navigational computer circuit |
| CN109542838A (en) * | 2018-12-29 | 2019-03-29 | 西安智多晶微电子有限公司 | A kind of FPGA and its system supporting more bit stream downloadings |
| CN110909317A (en) * | 2019-11-19 | 2020-03-24 | 天津津航计算技术研究所 | General encryption method for FPGA storage program |
| CN111555914A (en) * | 2020-04-24 | 2020-08-18 | 深圳国人无线通信有限公司 | FPGA remote configuration method |
-
2016
- 2016-05-25 CN CN201620491354.5U patent/CN206021242U/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107341034A (en) * | 2017-07-02 | 2017-11-10 | 中国航空工业集团公司雷华电子技术研究所 | A kind of structure and method that FPGA program curings are updated using UART interface |
| CN107341034B (en) * | 2017-07-02 | 2021-06-18 | 中国航空工业集团公司雷华电子技术研究所 | Structure and method for updating FPGA (field programmable Gate array) curing program by adopting UART (Universal asynchronous receiver/transmitter) interface |
| CN108763114A (en) * | 2018-07-23 | 2018-11-06 | 无锡航天江南数据系统科技有限公司 | A kind of cipher card and its working method based on PCIe104 interfaces |
| CN109255258A (en) * | 2018-08-27 | 2019-01-22 | 重庆天箭惯性科技股份有限公司 | Encrypt navigational computer circuit |
| CN109255258B (en) * | 2018-08-27 | 2020-07-14 | 重庆天箭惯性科技股份有限公司 | Encrypted navigation computer circuit |
| CN109542838A (en) * | 2018-12-29 | 2019-03-29 | 西安智多晶微电子有限公司 | A kind of FPGA and its system supporting more bit stream downloadings |
| CN109542838B (en) * | 2018-12-29 | 2024-04-30 | 西安智多晶微电子有限公司 | FPGA supporting multi-bit stream downloading and system thereof |
| CN110909317A (en) * | 2019-11-19 | 2020-03-24 | 天津津航计算技术研究所 | General encryption method for FPGA storage program |
| CN111555914A (en) * | 2020-04-24 | 2020-08-18 | 深圳国人无线通信有限公司 | FPGA remote configuration method |
| CN111555914B (en) * | 2020-04-24 | 2023-03-14 | 深圳国人无线通信有限公司 | FPGA remote configuration method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206021242U (en) | The FPGA programs configuration controlled based on CPLD and firmware encrypting system | |
| CN104391813B (en) | A kind of embedded data security system SOC | |
| CN102609287A (en) | Device for updating FPGA (Field Programmable Gate Array) from a long distance by CPU (Central Processing Unit) and method therefor | |
| CN102945217A (en) | Triple modular redundancy based satellite-borne comprehensive electronic system | |
| CN104391770B (en) | The on-line debugging of a kind of embedded data security system SOC and Upper machine communication module | |
| CN107908413A (en) | A kind of method of Domestic Platform remote maintenance mainboard BIOS | |
| CN202795350U (en) | Management device for USB ports | |
| CN105159731A (en) | Field programmable gate array (FPGA) configuration file remote upgrading device | |
| CN105320531A (en) | Online FPGA software upgrading method based on MicroBlaze soft core | |
| CN205692166U (en) | Core board based on PowerPC framework central processing unit | |
| CN106874054A (en) | A kind of repeater inner module program on-line upgrading method and system | |
| CN104798010A (en) | Serial storage protocol compatible frame conversion, at least in part | |
| CN104777761A (en) | Method and circuit for realizing safety of MCU (micro controller unit) | |
| CN113228021A (en) | Secure transfer of log reports in a memory subsystem | |
| CN205176901U (en) | Electronic tags reads and writes equipment | |
| CN106453258B (en) | High-speed data encryption and decryption system | |
| CN202205195U (en) | Equipment for reading and writing physical memory of computer through IEEE 1394 interface | |
| CN204347827U (en) | A kind of external high-speed memory system of expansion with PXI e interface adapter | |
| CN206348798U (en) | A kind of encrypted card of many USB controllers | |
| CN105868042B (en) | A kind of watchdog circuit | |
| CN108877647A (en) | LED control system and LED display device | |
| CN203102265U (en) | Solid state disk (SSD) control chip | |
| CN203552241U (en) | Refrigerator electric control program updating device and refrigerator using same | |
| CN104317449B (en) | The display of touch display one with Redundancy Design | |
| CN204990312U (en) | USB interface fingerprint equipment and encryption and decryption system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |