CN205982552U - IC testing arrangement - Google Patents
IC testing arrangement Download PDFInfo
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- CN205982552U CN205982552U CN201621046448.8U CN201621046448U CN205982552U CN 205982552 U CN205982552 U CN 205982552U CN 201621046448 U CN201621046448 U CN 201621046448U CN 205982552 U CN205982552 U CN 205982552U
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Abstract
The utility model discloses a IC testing arrangement, the terminal comprises a microcontroller. With the socket seat be connected of examination chip that awaits measuring, USB interface, UART interface, display screen, SD card, EEPROM, flash memory, SRAM memory, temperature chip, the test be connected with microcontroller respectively start mode -selection module, button cell and type coding module, the input is connected with microcontroller, the output produces the circuit with the programmable power supply that the socket seat is connected, programme -controlled signal produces circuit and clock production module, the frequency divider that the input is connected with the socket seat, output and microcontroller are connected, the input is connected with the one end of assembling analog switch, output and an adc, comparison / catch passageway and GPIO module that microcontroller is connected, assembles analog switch's the other end and is connected with the socket seat, first relay, the 2nd adc. This IC testing arrangement chooses for use some conventional components and parts can realize the test to NULL, simple structure and with low costs.
Description
Technical field
This utility model is related to chip testing technology field, more particularly to a kind of IC test device.
Background technology
With the development of microelectric technique, integrated chip is developed rapidly, and the function of integrated chip becomes increasingly complex,
Performance requirement more and more higher, power consumption requirements are more and more lower, but cost also requires that more and more lower, current integrated chip single chip
Manufacturing cost reduce continuous, but the cost of packaging and testing is but being continuously increased, packaging cost is mainly with packing material
(gold, silver with copper etc.) are related with packaging technology level, for chip design companies, the limited space of reduction, and integrated core
The testing cost of piece volume production then constantly can be reduced by modes such as design optimization, chip test tool optimizations.
In integrated chip manufacture process, due to the defect of manufacturing process, material etc., or due to electrostatic, or due to
The reasons such as encapsulation damage lead to high-volume integrated chip always to there is bad piece or the underproof integrated chip of performance in producing.Typically
Selecting of integrated chip is completed using ATE equipment, this scheme is mainly disadvantageous in that ATE test equipment is unusual in industry
Costliness, even if the ATE equipment renting test company is also very expensive, general medium-sized and small enterprises hold and can't stand ATE equipment
Testing cost.
Therefore, a kind of scheme solving above-mentioned technical problem how is provided to be that those skilled in the art need to solve at present
Problem.
Utility model content
The purpose of this utility model is to provide a kind of IC test device, is enabled to collection from some conventional components and parts
Become the test of chip, structure is simple and low cost.
For solving above-mentioned technical problem, this utility model provides a kind of IC test device, including microcontroller；With to be measured
Examination chip connects, the Socket seat for coupling together described chip to be tested with described test device；
The USB interface that is connected with described microcontroller respectively, UART interface, display screen, SD card, EEPROM, Flash storage
Device, SRAM memory, chip temperature, test starting mode selection module, button cell and type coding module；Wherein, institute
State USB interface for carrying out data transmission between described test device and PC；Described UART interface is used for described survey
The Debugging message that trial assembly is put in debugging process transmits to described PC；Described display screen is used for described Debugging message and described
Test device test start, test in and test end test information shown；Described SD card is used for storing described
All test datas in test process for the test device；Described EEPROM is used for storing No. ID of described chip to be tested；Institute
State flash storage for storing the calibration data of described test device and the test program of described chip to be tested；Described
SRAM memory is used for storing SNR data and DFT data, and carries out FFT computing；Described chip temperature is used for calibrating described to be measured
Try the temperature sensor in chip and record current test environment temperature；Described test starting mode selection module is used for selecting
Select the test pattern that presently described test device needs to use；Described button cell is used for the RTC in microcontroller is powered；Institute
State type coding module for distinguishing described test device and the species of described chip to be tested；
Input is connected with described microcontroller, outfan is connected with described Socket seat program-controlled electric source generating circuit,
Program control signal produces circuit and clock generation module；Input is connected with described Socket seat, outfan and described microcontroller
The frequency divider that device connects；Wherein, described program-controlled electric source generating circuit is used for providing adjustable power supply for described chip to be tested
Voltage, and measure power consumption；Described program control signal produces circuit and is used for producing amplitude needed for chip to be tested, frequency, phase place
And bias all adjustable test signal；Described clock generation module is used for generating desired clock signal and exports to described
Chip to be tested；Described frequency divider is used for the high-frequency signal output frequency division measurement to described chip to be tested；
The first analog digital conversion that input is connected with one end of total analog switch, outfan is connected with described microcontroller
Device, compare/capture passage and GPIO module, the other end of described total analog switch is connected with described Socket seat；Wherein, institute
State the first analog-digital converter for measuring the analog quantity of described chip to be tested；Described comparison/capture passage is used for by described
The break-make of total analog switch realizes the connection needing capture and the pin comparing and described microcontroller of described chip to be tested；
Described GPIO module is used for the GPIO function of described chip to be tested is tested；
Control end is connected with described microcontroller, first end is connected with load, the second end is connected, uses with described Socket seat
In realizing controlling whether the linear stable in described chip to be tested carries by the described microprocessor controls break-make of itself
The first relay carrying；
Input is connected with the second end of described first relay, outfan is connected with described microcontroller, be used for measuring
Described linear stable is in the second analog-digital converter with carrying with the magnitude of voltage under zero load.
Preferably, described program-controlled electric source generating circuit includes：
Input is as the input of described program-controlled electric source generating circuit, Voltage Reference end and first voltage reference source even
Connect, outfan is connected with the input of high current amplifier, for the control signal and described the according to described microcontroller
One voltage reference source exports the first digital to analog converter of analog voltage；
Outfan is connected with the first end of sampling resistor and the input of the 3rd analog-digital converter, respectively for described
Analog voltage is amplified obtaining the described high current amplifier of supply voltage；
Outfan is connected with described microcontroller, for being provided after described supply voltage acquisition process treating to described
Described 3rd analog-digital converter of the supply voltage of test chip；
First end and the second end are connected with the input of instrument amplifier, the first end also with the second relay for second end
The described sampling resistor connecting；
Outfan is connected with the input of the 4th analog-digital converter, the differential voltage for gathering on described sampling resistor,
And described differential voltage is amplified being amplified the described instrument amplifier of voltage；
Outfan is connected with described microcontroller, be used for gathering described amplification voltage after send and carry out to described microcontroller
Described 4th analog-digital converter processing；
Control end is connected with described microcontroller, the second end is connected with described Socket seat, for by described microcontroller
Device controls the break-make of itself to realize whether described program-controlled electric source generating circuit is described the second of described chip power supply to be tested
Relay.
Preferably, described program-controlled electric source generating circuit also includes：
Control end is connected with described microcontroller, first end is connected with the second end of described second relay, the second end with
Discharge circuit connects, for whether realizing described discharge circuit to described to be measured by the described microprocessor controls break-make of itself
3rd relay of the examination quick power down of chip.
Preferably, described program-controlled electric source generating circuit also includes：
First end is connected with the outfan of described high current amplifier, the second end is connected with the first end of described sampling resistor
Resettable fuse.
Preferably, described program-controlled electric source generating circuit also includes：
First end is connected with the second end of described resettable fuse, the input of the second end and described 3rd analog-digital converter
The first bleeder circuit that end connects.
Preferably, described program control signal produces circuit and includes：
Input is connected with described microcontroller, outfan is connected with the first end of the second bleeder circuit, Voltage Reference end
It is connected with second voltage reference source, be used for exporting according to the control signal of described microcontroller and described second voltage reference source
Second digital to analog converter of analogue signal；
Described second bleeder circuit that second end is connected with the first end of voltage follower；
The described voltage follower that second end is connected with the first input end of the first analog switch；
Second input is connected with simulation ground, outfan is connected with described Socket seat, control end and described microcontroller
Connect, be used for select output or the simulation of voltage follower according to the control signal of described microcontroller to described Socket
Described first analog switch of seat.
Preferably, this test device also includes：
It is connected with described microcontroller by optocoupler, be used for selecting separator to connect parallel with what described microcontroller was connected
Mouthful.
Preferably, this test device also includes：
It is connected with described microcontroller, be used for triggering described test device and described chip testing to be tested started or stops
Button only.
Preferably, this test device also includes：
It is connected with described microcontroller, start or terminate, in test, the report that test is reported to the police for described test device
Alarm device.
Preferably, described total analog switch is that N level cascaded analogue switchs, and N is integer.
This utility model provides a kind of IC test device, including microcontroller；The Socket being connected with chip to be tested
Seat；The USB interface that is connected with microcontroller respectively, UART interface, display screen, SD card, EEPROM, flash storage, SRAM are deposited
Reservoir, chip temperature, test starting mode selection module, button cell and type coding module；Input and microcontroller
The program-controlled electric source generating circuit that connection, outfan are connected with Socket seat, program control signal produce circuit and clock generation module；
The frequency divider that input is connected with Socket seat, outfan is connected with microcontroller；Input is connected with one end of total analog switch
Connect, the first analog-digital converter that outfan is connected with microcontroller, compare/capture passage and GPIO module, total analog switch
The other end be connected with Socket seat；Control end is connected with microcontroller, first end is connected with load, the second end and Socket seat
The first relay connecting；The second mould that input is connected with the second end of the first relay, outfan is connected with microcontroller
Number converter.Compared with expensive ATE equipment in prior art, can be real from some conventional components and parts in this utility model
The now test to integrated chip, structure is simple and low cost.
Brief description
In order to be illustrated more clearly that the technical scheme in this utility model embodiment, below will be to prior art and embodiment
In required use accompanying drawing be briefly described it should be apparent that, drawings in the following description are only of the present utility model
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to this
A little accompanying drawings obtain other accompanying drawings.
A kind of structural representation of IC test device that Fig. 1 provides for this utility model；
The structural representation of another kind of IC test device that Fig. 2 provides for this utility model；
A kind of structural representation of program-controlled electric source generating circuit that Fig. 3 provides for this utility model；
Fig. 4 produces the structural representation of circuit for a kind of program control signal that this utility model provides.
Specific embodiment
Core of the present utility model is to provide a kind of IC test device, is enabled to collection from some conventional components and parts
Become the test of chip, structure is simple and low cost.
Purpose, technical scheme and advantage for making this utility model embodiment are clearer, new below in conjunction with this practicality
Accompanying drawing in type embodiment, is clearly and completely described it is clear that being retouched to the technical scheme in this utility model embodiment
The embodiment stated is a part of embodiment of this utility model, rather than whole embodiments.Based on the enforcement in this utility model
Example, the every other embodiment that those of ordinary skill in the art are obtained under the premise of not making creative work, broadly fall into
The scope of this utility model protection.
Embodiment one
Refer to Fig. 1, a kind of structural representation of IC test device that Fig. 1 provides for this utility model；
This IC test device includes microcontroller 1；
Microcontroller 1 is the core devices of whole test device, coordinates to control peripheral module to complete to treat test chip
Test.
Specifically, STM32F4 family chip can be chosen here as microcontroller 1, it is of course also possible to choose other be
As microcontroller 1, this utility model here is not particularly limited the chip of row.
Be connected with chip to be tested, for the Socket seat that couples together described chip to be tested with described test device
2；
Socket seat 2 is for connecting chip to be tested and test device, by whole resources of chip to be tested even
It is connected in test device, can be by changing different Socket seats for different encapsulation and different types of chip to be tested
2 completing the connection of chip to be tested and test device, in addition, can also add keyset at this to complete different chips to be tested
Connection and test device between.
The USB interface 3 that is connected with microcontroller 1 respectively, UART interface 4, display screen 5, SD card 6, EEPROM 7, Flash
Memorizer 8, SRAM memory 9, chip temperature 10, test starting mode selection module 11, button cell 12 and type coding
Module 13；Wherein, USB interface 3 is used for carrying out data transmission between test device and PC；UART interface 4 is used for surveying
The Debugging message that trial assembly is put in debugging process transmits to PC；Display screen 5 is used for Debugging message and test device in test
Start, test in and test terminate test information shown；SD card 6 is used for storing test device in test process
All test datas；EEPROM 7 is used for storing No. ID of chip to be tested；Flash storage 8 is used for storing test device
Calibration data and the test program of chip to be tested；SRAM memory 9 is used for storing SNR data and DFT data, and carries out FFT
Computing；Chip temperature 10 is used for calibrating the temperature sensor in chip to be tested and recording current test environment temperature；Survey
Experimental starting mode selection module 11 is used for selecting current test setup to need the test pattern using；Button cell 12 is used for micro-
RTC in controller 1 powers；Type coding module 13 is used for the species of differentiating measurement device and chip to be tested；
Specifically, USB interface 3 is used for transmission data, the data that test device is tested between test device and PC
It is transferred to PC, to be analyzed to these test datas on PC and to count, extract useful information, test device carries
Supply USB interface 3 it is only necessary to be connected a USB data line between PC and test device.
UART interface 4 is that test device reserves out debugging use, can be using UART during debugging test device
Debugging message is transferred on PC interface 4, provides convenience to debugging.
Display screen 5 is used for starting, test the test information of neutralization test end and carry out treating test chip and carry out testing
Show in real time, facilitate operator to watch the real-time status of test device；In addition, can also be used for showing in the test device debugging stage
Show Debugging message, convenient debugging.
Specifically, display screen 5 here can be LCD display or LCDs, it is, of course, also possible to be other classes
The display screen of type, this utility model here is not particularly limited.
SD card 6 is all test datas for storing test device during volume production, operator think analysis and
During statistical test data, directly SD card 6 can be extracted, be connected with PC by card reader, test data is imported to PC
On processed, or SD card 6 need not be extracted it is only necessary to be connected USB cable between PC and the USB interface 3 of test device
Line, PC directly passes through USB interface 3 read test data from the SD card 6 of test device.
EEPROM 7 is mainly used in storing No. ID of chip to be tested, and this No. ID has uniqueness, and test device is in test
After the completion of treat test chip and write No. ID of unique number.
Flash storage 8 is mainly used in storing test program of the calibration data of test device and chip to be tested etc., this
A little calibration data include difference between different test devices, the difference between some devices, chip temperature 10 in test device
Difference between itself etc., by these calibration data ensure all test devices concordance so that test device it
Between difference be minimized.
SRAM memory 9 is the plug-in RAM of microcontroller 1, is mainly used in carrying out some complex calculation and data storage, example
As stored SNR data and DFT data, and carry out FFT computing etc..
Chip temperature 10 as standard temperature, is mainly used in calibrating the temperature sensing in chip to be tested in test device
Device, is additionally operable to record the information such as the ambient temperature of current test.
Test starting mode selection module 11 is used for selecting current test setup to need the test pattern using, for example, repeat
Property test pattern, normal test mode, calibration mode etc., it is possible to use toggle switch is realizing this part.
Button cell 12 is mainly to the RTC part power supply in microcontroller 1 so that the RTC circuit of microcontroller 1 is being surveyed
Trial assembly put under powering-off state can also normal work it is ensured that test device is when testing each chip to be tested, can
The correct dat recorder of test is got off, is saved in SD card 6, so that subsequent query uses.
Type coding module 13 is used for the species of differentiating measurement device and chip to be tested, and each test device has only
One numbering, different types of chip to be tested also has a unique numbering, and this two parts has collectively constituted type coding,
The microcontroller 1 of test device using EEPROM 7 treat test chip carry out write ID when, it will compile using to type
Code module 13 in numbering, thus ensure No. ID of chip to be tested uniqueness (may using multiple test devices to be measured
Examination chip is tested).
Input is connected with microcontroller 1, outfan is connected with Socket seat 2 program-controlled electric source generating circuit 14, program control
Signal generating circuit 15 and clock generation module 16；Input is connected with Socket seat 2, outfan is connected with microcontroller 1
Frequency divider 17；Wherein, program-controlled electric source generating circuit 14 is used for providing adjustable supply voltage for chip to be tested, and surveys
Amount power consumption；Program control signal produce circuit 15 be used for producing amplitude needed for chip to be tested, frequency, phase place and biasing all adjustable
The test signal of section；Clock generation module 16 is used for generating desired clock signal and exporting to chip to be tested；Frequency divider 17
High-frequency signal output frequency division for treating test chip measures；
Program-controlled electric source generating circuit 14 is mainly used in providing supply voltage for chip to be tested, and measures on this circuit
Electric current and voltage swing, to reach the purpose testing chip power-consumption to be tested, can design many in test device according to demand
Road, to complete to treat the different electrical power pin powered of test chip, for example, is main power source pin, the RTC of chip to be tested simultaneously
Power pins and core voltage power pins etc. are independently-powered, the power consumption on the different power supply pin of test.
Program control signal produces circuit 15 and mainly provides various test signals for chip to be tested, for example sinusoidal
Signal, serrated signal and scalable direct current signal etc., program control signal here produce circuit 15 can according to real needs, if
Count into multichannel, to meet the different test signal demands of chip to be tested, the signal that program control signal produces circuit 15 generation is frequency
The signal that rate, amplitude, phase place and biasing etc. can arbitrarily be adjusted.
Clock generation module 16 is controlled by microcontroller 1, produces desired clock signal and is supplied to chip to be tested, for example
After chip to be tested starts power up, the crystal oscillating circuit starting of oscillation of chip periphery to be tested is slower, and now microcontroller 1 just can be controlled
Clock generation module 16 processed, to produce desired clock signal, is supplied to chip to be tested so that the crystal oscillator of chip to be tested rises
Shake acceleration, save crystal oscillating circuit Induction Peried, or when treating test chip pulse per second (PPS) output test, produce mould using clock
Block 16 is treated test chip clock and is accelerated, and improves testing efficiency.
Frequency divider 17 is mainly used in treating the high-frequency signal output frequency division measurement of test chip, chip output for example to be tested
The clock of 26MHz, directly use microcontroller 1 capturing function be capture less than, so need to treat test chip exporting
The clock of 26MHz first divided, reuse microcontroller 1 and capture process carried out to the clock after frequency dividing.
The first analog-digital converter that input is connected with one end of total analog switch 21, outfan is connected with microcontroller 1
18th, compare/capture passage 19 and GPIO module 20, the other end of total analog switch 21 is connected with Socket seat；Wherein, first
Analog-digital converter 18 is used for measuring the analog quantity of chip to be tested；Relatively/capture passage 19 is used for by total analog switch 21
Break-make realizes the connection needing capture and the pin comparing and microcontroller 1 of chip to be tested；GPIO module 20 is used for treating
The GPIO function of test chip is tested；
First analog-digital converter 18 is mainly used to measure the analog quantity of chip to be tested, and the LCD of chip for example to be tested drives
The signal of dynamic device output, voltage of reference voltage REF, integrated linear stable voltage LDO and DAC output etc., be also here
Microcontroller 1 gates the analog signalses of chip to be tested to the first analog-digital converter 18 by controlling total analog switch 21
On, whether the analog signalses that microcontroller 1 measures chip to be tested by the first analog-digital converter 18 are normal.
Relatively/capture passage 19 is the functional module of microcontroller 1, and microcontroller 1 can control total analog switch 21
Gate chip to be tested need to compare/pin of capturing function to comparing/capturing on passage 19, complete to treat the institute of test chip
Capture in need and need the test compared, namely microcontroller 1 can control total analog switch 21 by the institute of chip to be tested
There is pin to be strobed into compare/capture on passage 19.
GPIO module 20 is the GPIO function of microcontroller 1, is mainly used in treating the GPIO functional test of test chip, tool
Body ground, microcontroller 1 controls total analog switch 21 that all GPIO of chip to be tested are strobed in GPIO module 20 successively, surveys
The GPIO function of testing chip to be tested successively is put in trial assembly, and whether all GPIO testing chip to be tested successively can be normal
Input and output low and high level.
Control end is connected with microcontroller 1, first end is connected with load, the second end is connected with Socket seat 2, be used for passing through
Microcontroller 1 controls the break-make of itself to realize controlling linear stable in chip to be tested whether the first relay with load
22；
Load and tested for the load capacity treating the integrated linear stable LDO of test chip, load here
Big I to be controlled by microcontroller 1, to increase the motility of test device；First relay 22 is used for controlling chip to be tested
Whether integrated linear stable LDO carries load, is carried with facilitating the linear stable LDO testing integrated chip to be tested unloaded and carrying
Under voltage, this first relay 22 controls on or off by microcontroller 1.
Input is connected with the second end of the first relay 22, outfan is connected with microcontroller 1, it is linearly steady to be used for measuring
Potential source is in the second analog-digital converter 23 with carrying with the magnitude of voltage under zero load.
This utility model provides a kind of IC test device, including microcontroller；The Socket being connected with chip to be tested
Seat；The USB interface that is connected with microcontroller respectively, UART interface, display screen, SD card, EEPROM, flash storage, SRAM are deposited
Reservoir, chip temperature, test starting mode selection module, button cell and type coding module；Input and microcontroller
The program-controlled electric source generating circuit that connection, outfan are connected with Socket seat, program control signal produce circuit and clock generation module；
The frequency divider that input is connected with Socket seat, outfan is connected with microcontroller；Input is connected with one end of total analog switch
Connect, the first analog-digital converter that outfan is connected with microcontroller, compare/capture passage and GPIO module, total analog switch
The other end be connected with Socket seat；Control end is connected with microcontroller, first end is connected with load, the second end and Socket seat
The first relay connecting；The second mould that input is connected with the second end of the first relay, outfan is connected with microcontroller
Number converter.Compared with expensive ATE equipment in prior art, can be real from some conventional components and parts in this utility model
The now test to integrated chip, structure is simple and low cost.
Embodiment two
Refer to Fig. 2, the structural representation of another kind of IC test device that Fig. 2 provides for this utility model, in embodiment
On the basis of the IC test device of one offer：
Preferably, program-controlled electric source generating circuit 14 includes：
Input is as the input of program-controlled electric source generating circuit 14, Voltage Reference end and first voltage reference source 142 even
Connect, outfan is connected with the input of high current amplifier 143, for electric according to the control signal of microcontroller 1 and first
Pressure reference source 142 exports the first digital to analog converter 141 of analog voltage；
Outfan is connected, is used for the first end of sampling resistor 145 and the input of the 3rd analog-digital converter 144 respectively
Analog voltage is amplified obtain the high current amplifier 143 of supply voltage；
Outfan is connected with microcontroller 1, for being provided after supply voltage acquisition process to chip to be tested
3rd analog-digital converter 144 of supply voltage；
First end and the second end are connected with the input of instrument amplifier 1451, the second end also with the second relay 146
First end connect sampling resistor 145；
Outfan is connected with the input of the 4th analog-digital converter 1452, the differential electrical for gathering on sampling resistor 145
Pressure, and differential voltage is amplified being amplified the instrument amplifier 1451 of voltage；
Outfan is connected with microcontroller 1, amplify for collection send after voltage to microcontroller 1 processed the 4th
Analog-digital converter 1452；
Control end is connected with microcontroller 1, the second end is connected with Socket seat 2, for by microcontroller 1 control itself
Break-make realizing the second relay 146 whether program-controlled electric source generating circuit 14 is chip power supply to be tested.
Preferably, program-controlled electric source generating circuit 14 also includes：
Control end is connected with microcontroller 1, first end is connected with the second end of the second relay 146, the second end and electric discharge
Circuit 148 connects, for controlling the break-make of itself to realize discharge circuit 148 by microcontroller 1, whether to treat test chip fast
3rd relay 147 of fast power down.
Specifically, refer to Fig. 3, a kind of structural representation of program-controlled electric source generating circuit that Fig. 3 provides for this utility model
Figure.
Microcontroller 1 controls the first digital to analog converter 141 to export an analog voltage, and the analog voltage size of output is by micro-
Controller 1 is transferred to the control signal of the first digital to analog converter 141 and first voltage reference source 142 determines, first voltage is joined
Examine source 142 for providing reference voltage, the analog voltage warp of the first digital to analog converter 141 output for the first digital to analog converter 141
Supply voltage after being amplified after super-high-current amplifier 143 amplification.
Current measurement on program-controlled electric source generating circuit 14 is through instrument by the 4th analog-digital converter 1452 acquisition process
The voltage of the sampling resistor 145 after table amplifier 1451 amplification, the differential voltage flowing through on collection sampling resistor 145, so
The electric current flowing through on sampling resistor 145 can be conversed, be employed herein instrument amplifier 1451, without consideration collection electric current electricity
The effect of leakage on road, precision is very high；Second relay 146 is controlled by microcontroller 1, and its effect is to control programmable power supply to produce
Whether raw circuit 14 turns on the power pins of chip to be tested, microcontroller 1 control the when starting to test chip to be tested
Three relays 147 turn off, control the second relay 146 turn on, make program-controlled electric source generating circuit 14 give chip power supply to be tested, when
After the completion of test, microcontroller 1 controls the second relay 146 to turn off, and controls the 3rd relay 147 to turn on, and so that programmable power supply is produced
Raw circuit 14 stopping is treated test chip and is powered, and discharge circuit 148 works, and treats the quick power down of test chip, finally real
Existing taking and putting measured examination chip is power-down operation.
Specifically, relay mentioned above can also be replaced using other switching devices, such as metal-oxide-semiconductor, transistor etc.,
This utility model here is not particularly limited.
Preferably, program-controlled electric source generating circuit 14 also includes：
First end is connected with the outfan of high current amplifier 143, the second end is connected with the first end of sampling resistor 145
Resettable fuse 149.
This supply voltage is supplied to through sampling resistor 145 and the second relay 146 after resettable fuse 149 again
Chip to be tested, resettable fuse 149 plays hardware overcurrent protection.
Preferably, program-controlled electric source generating circuit 14 also includes：
First end is connected with the second end of resettable fuse 149, the input of the second end and the 3rd analog-digital converter 144
The first bleeder circuit 140 connecting.
Due to amplify after supply voltage may ratio larger, may exceed the 3rd analog-digital converter 144 measurement range,
Therefore, the application is also provided with the first bleeder circuit 140, the first bleeder circuit 140 by amplify after source voltage after, then
It is provided to the supply voltage of chip to be tested by after the 3rd analog-digital converter 144 acquisition process.
Preferably, program control signal produces circuit 15 and includes：
Input is connected with microcontroller 1, outfan is connected with the first end of the second bleeder circuit 153, Voltage Reference end
It is connected with second voltage reference source 152, the control signal for foundation microcontroller 1 and second voltage reference source 152 export
Second digital to analog converter 151 of analogue signal；
The second bleeder circuit 153 that second end is connected with the first end of voltage follower 154；
The voltage follower 154 that second end is connected with the first input end of the first analog switch 156；
Second input is connected with simulation ground 155, outfan is connected with Socket seat 2, control end and microcontroller 1 connect
Connect, be used for selecting according to the control signal of microcontroller 1 output or simulation ground 155 to the Socket seat 2 of voltage follower 154
The first analog switch 156.
Specifically, refer to Fig. 4, Fig. 4 produces the structural representation of circuit for a kind of program control signal that this utility model provides
Figure.
Microcontroller 1 controls the second digital to analog converter 151 to export mould under second voltage reference source 152 is as reference voltage
Intend signal, the frequency of this analogue signal, amplitude, phase place, biasing etc. are controlled by microcontroller 1, and this analogue signal is through second point
It is transferred to voltage follower 154, the effect of voltage follower 154 is for impedance matching first after volt circuit 153 voltage division processing
Analog switch 156 can select the program control signal after voltage follower 154 or simulation ground under the control of microcontroller 1
155 arrive chip to be tested (Socket seat 2), complete the test of the ADC of chip to be tested, select after voltage follower 154
Program control signal when, for the proper testing of ADC, select the SNR test for ADC during simulation ground 155.
In addition, only needing to the signal that amplitude is several millivolts or tens millivolts, this Shen to meet some chips to be tested
Please be also provided with the second bleeder circuit 153.
Preferably, this test device also includes：
Be connected with microcontroller 1 by optocoupler 24, for selecting the parallel interface 25 that separator is connected with microcontroller 1.
Parallel interface 25 is the interface for communicating with separator；Optocoupler 24 is used for isolating the electricity of separator and test device
Source, plays insulation blocking effect.
Preferably, this test device also includes：
It is connected with microcontroller 1, treat the button 26 that test chip test starts or stops for trigger test device.
Button 26 is mainly used in operator using during test device manual test, triggers test using button 26
Device is treated test chip test and is started or stop.
Preferably, this test device also includes：
It is connected with microcontroller 1, start or terminate, in test, the alarm device that test is reported to the police for test device
27.
It is understood that the warning that alarm device 27 is mainly used in when test device test beginning or end test carries
It is shown as using, during operator carry out manual test using test device, particularly have preferable effect.
Specifically, alarm device 27 here can be buzzer, it is, of course, also possible to be other kinds of alarm device,
This utility model here is not particularly limited.
Preferably, total analog switch 21 is that N level cascaded analogue switchs, and N is integer.
Specifically, total analog switch 21 is 3 grades of cascaded analogue switches, and this 3 grades of cascaded analogue switches include the second simulation and open
Close the 211, the 3rd analog switch 212 and the 4th analog switch 213, concatenated here three-level analog switch mainly consider for
The especially many chips to be tested of some pins, the resource of microcontroller 1 is not enough, and the application being capable of consolidating using microcontroller 1
Fixed several GPIO resources just can test a lot of resources of chip to be tested with timesharing.
In addition, chip to be tested is the chip needing high-volume test, put it in Socket seat 2 in test.
The pin that Socket seat 2 is also much directly connected with microcontroller 1, the UART of chip such as to be tested, JTAG, SPI,
SNR code stream output pin etc.；In order to save the GPIO resource of microcontroller 1 further, the first analog switch 156, second is simulated
The control signal of switch the 211, the 3rd analog switch 212 and the 4th analog switch 213 can be with being controlled using displacement latch.
The work process of the test device providing with regard to the application below is described：
Operator write the program of microcontroller 1 on PC and are burnt in the microcontroller 1 of test device, compile
Finish writing the program treating burning/recording chip, write calibration file, then operator use USB cable line to connect PC and test dress
The USB interface 3 put, calibration file and the program file treating burning/recording chip etc. are transferred to test device by USB cable line
In flash storage 8.Here USB interface 3 can not also be used, and directly the SD card 6 of test device be pulled, by reading
Card device is connected with PC, calibration file and the program file treating burning/recording chip etc. is copied in SD card 6, then this SD card 6 is inserted
Enter SD card 6 position of test device, test device is automatically by the calibration file in SD card 6 and the program file treating burning/recording chip etc.
Copy in flash storage 8, if board is tested automatically then connects separator and test device by parallel-port electrical cable
Parallel interface 25, makes separator and test device collaborative work by optocoupler 24 isolation.If necessary to viewing Debugging message, then make
Connect the UART interface 4 of PC and test device with Serial Port Line, some Debugging message can be printed to the upper of PC by test device
On the interface of position machine software, watch the state of test device for operator；Operator also need to choose test device
Test starting pattern, if selecting is reperformance test pattern, test device will carry out many to same chip to be tested
Secondary (such as 100,000 times) retest, to observe stability and the performance of this test device；If select is proper testing mould
Formula, then test device will carry out proper testing production to large batch of chip to be tested；If select is calibration mode,
The microcontroller 1 of test device will read calibration file from flash storage 8, and test device is calibrated, and makes to own
Being consistent property of test device etc..To electricity in test device, the microcontroller 1 of test device will detect test starting mould first
Formula is which kind of start-up mode (reperformance test pattern, normal test mode, calibration mode etc.), and detection type coding module
13, by the numbering of type coding module 13, microcontroller 1 is able to know that type and the model of chip to be tested, operator
(manual testing) or mechanical hand (automatically testing) put into chip to be tested in Socket seat 2, and operator click manually
The start button 26 of test device, or board pass through parallel interface 25 initiate start test order, test device start survey
Try chip to be tested, microcontroller 1 will control program-controlled electric source generating circuit 14 to chip power supply to be tested, and will be from
Read the program of corresponding chip to be tested in flash storage 8, and be burnt to by modes such as JTAG or UART or SPI
In chip to be tested, start to treat test chip according to test starting pattern and start to test, real on display screen 5 in test process
When show test item, after the completion of test, unique chip id number will be write to the chip to be tested not writing No. ID, write
No. ID to be microcontroller 1 be calculated according to the cumulative data of type coding module 13 and EEPROM 7 the inside storage, that is, wrap
Include test device numbering, cumulative data composition in test chip type and model and EEPROM 7, to be measured to guarantee to write
The ID uniqueness of examination chip, will ignore write chip id number for the chip having been written into No. ID, and test data will be preserved
To in SD card 6, in UART interface 4 in test process, also can print some Debugging message, these information are not required, only
Trouble-shoots are facilitated to use, after the completion of once testing, microcontroller 1 will control program-controlled electric source generating circuit 14 to treat test chip
Chip to be tested is taken out classification from Socket seat 2 by power down, operator (manual testing) or mechanical hand (automatically testing)
Packaging, after continue by operator (manual testing) or board test command and determine to start to test next time.When
When operator want to analyze the chip to be tested crossed with statistical test, test dress can be imported on PC by USB cable line
Put the data being stored in SD card 6, or do not use USB cable line, directly SD card 6 is pulled, PC is connected by card reader
Machine, test data is copied on PC, then completes analysis and the statistics of test data, finds the excellent of yield according to test data
Change item, test device is optimized etc..
It is further to note that being merely given as the test device of 1 site above, for raising chip to be tested
One method of testing efficiency is exactly to be tested together using multiple site, so can also synthesize test device recited above
Multiple site such as 4site, 8site completing the test of large batch of chip to be tested, to improve testing efficiency further.
In sum, the application has the advantage that：
It is designed with multichannel program-controlled electric source generating circuit 14, can treat test chip provides adjustable electricity in test device
Source voltage, and be capable of and high-precision measure the normal power consumption of chip to be tested and dormancy power consumption and RTC power supply power consumption (precision will
Ask less than 0.01uA, realized using instrument amplifier 1451 and the 4th analog-digital converter 1452) etc.；And this power supply passes through first point
The closed loop control that supply voltage exports realized by volt circuit 140 and the 3rd analog-digital converter 144, makes to be supplied to the electricity of chip to be tested
Source voltage accuracy is higher；In addition this program-controlled electric source generating circuit 14 controls the second relay 146 and the 3rd to continue by microcontroller 1
The power-down operation of chip to be tested realized by electrical equipment 147, is power-down operation in taking and putting measured examination chip, it is to avoid because of powered behaviour
Make and damage chip to be tested etc..
Test device is designed with multichannel program control signal and produces circuit 15, and this circuit can produce any waveform and frequency, width
Value, phase place and biasing all can real-time regulations；Increase by the second bleeder circuit 153 in the line, can complete to export small-signal to treating
Test chip naturally it is also possible to remove the second bleeder circuit 153 export than more larger signal give chip to be tested it is also possible to
Export adjustable direct current signal to chip to be tested；An impedance matching made by voltage follower 154, and program control signal produces electricity
Devise the first analog switch 156 in road 15, can flexibly select the signal of voltage follower 154 output, adjustable to complete
Section analogue signal supply, complete certain analogue signal input in the case of chip to be tested analog module (such as
ADC, metering, detection of power loss threshold value etc.) function and performance test it is also possible to by the first analog switch 156 gating simulation
Ground 155 is connected to the analog module of chip to be tested, such as SNR performance of test ADC etc..
Devise GPIO module 20 in test device, compare/capture passage 19, first analog-digital converter the 18, second simulation
Switch the 211, the 3rd analog switch 212 and the 4th analog switch 213 coordinate GPIO function, the mould completing to test chip to be tested
Intend function, pulse per second (PPS), CF pulse, clock signal etc., save the GPIO resource of a large amount of microcontrollers 1, and this design extension
Property is good, when chip to be tested is replaced with GPIO pin with many integrated chips it is only necessary to whole GPIO are connected to the 4th mould
Intend switch 213；When the GPIO pin resource of microcontroller 1 is nervous, first can also be controlled using displacement latch
Analog switch 156, the second analog switch 211, the 3rd analog switch 212 and the 4th analog switch 213 etc., displacement here is latched
Device can select 74HC595 device.
Durability is good, when needing to test another kind of chip to be tested it is only necessary to change Socket seat 2, and updates preservation
The program of the chip to be tested in flash storage 8, same test device can test the to be tested of different model
Chip, the exploitation for the test device of later new chip to be tested is highly beneficial, greatly shortens the construction cycle.
This device enables manual testing and automatically tests, both seamless switchings, when needing manual testing, operator
Press start button 26, you can start to test, certainly think that midway stops testing, operator by stopping test button 26 can be
The test of chip to be tested can be immediately finished, this is very useful in early stage small lot prototype test；Automatically survey when needing to use
During examination, the parallel interface 25 of this test device is connected with tester table, separator etc. by parallel-port electrical cable, tester table is sent out
Send beginning test command to test device, you can start the test of chip to be tested, after test terminates, test device sends to be surveyed
Examination end signal is to tester table, and the chip to be tested of test is passed through separator class wrapping according to good piece or bad piece,
This is generally used for high-volume volume production.
Man-machine interaction is good, and test device can show current test item, good by display screen 5 in test process in real time
Rate, test chip total quantity, test passes quantity, each test item do not pass through the information such as quantity.Can also be in test process
Debugging message is constantly printed by UART interface 4, these debugging signals include test device real-time testing data, some promptings
Sentence etc., has good effect to the running status of control test device, when operator need to be concerned about these Debugging message
When it is only necessary to be connected a Serial Port Line between PC and the UART interface 4 of test device, you can in the upper computer software of PC
Interface on show these information.Test device additionally provides button 26, specifically includes two main buttons 26, one makes to open
Dynamic button 26, for starting the test starting chip to be tested, another is off testing button 26, current for stopping immediately
Test, typically do not use.Test device additionally provides a buzzer for alarm, when test beginning and test terminate
When sounding alarm to point out, practical under manual testing's mode.USB interface 3 and SD card 6 can will test chip to be tested
Test data import on PC, then just a series of data analysiss, process and statistics etc. can be done on PC, thus
Analyzing the main test item of impact yield, thus improving yield, also having certain reference for operation and chip designer
Be worth etc..
It should be noted that in this manual, such as first and second or the like relational terms are used merely to one
Individual entity or operation are made a distinction with another entity or operation, and not necessarily require or imply these entities or operate it
Between there is any this actual relation or order.And, term " inclusion ", "comprising" or its any other variant are intended to
Cover comprising of nonexcludability, so that including a series of process of key elements, method, article or equipment not only include those
Key element, but also include other key elements being not expressly set out, or also include for this process, method, article or set
Standby intrinsic key element.In the absence of more restrictions, the key element that limited by sentence "including a ..." it is not excluded that
Also there is other identical element in process, method, article or the equipment including described key element.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or new using this practicality
Type.Multiple modifications to these embodiments will be apparent from for those skilled in the art, is determined herein
The General Principle of justice can be realized in the case of without departing from spirit or scope of the present utility model in other embodiments.Cause
This, this utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The wide scope consistent with features of novelty.
Claims (10)
1. a kind of IC test device is it is characterised in that include microcontroller；It is connected with chip to be tested, being used for will be described to be measured
The Socket seat that examination chip is coupled together with described test device；
The USB interface that is connected with described microcontroller respectively, UART interface, display screen, SD card, EEPROM, flash storage,
SRAM memory, chip temperature, test starting mode selection module, button cell and type coding module；Wherein, described
USB interface is used for carrying out data transmission between described test device and PC；Described UART interface is used for described test
Debugging message during device debugging transmits to described PC；Described display screen is used for described Debugging message and described survey
The test information that trial assembly is put in test starts, tests and test terminates is shown；Described SD card is used for storing described survey
The all test datas in test process are put in trial assembly；Described EEPROM is used for storing No. ID of described chip to be tested；Described
Flash storage is used for storing the calibration data of described test device and the test program of described chip to be tested；Described SRAM
Memorizer is used for storing SNR data and DFT data, and carries out FFT computing；Described chip temperature is used for calibrating described core to be tested
Temperature sensor in piece and record current test environment temperature；Described test starting mode selection module is used for selecting to work as
Front described test device needs the test pattern using；Described button cell is used for the RTC in microcontroller is powered；Described class
Type coding module is used for distinguishing described test device and the species of described chip to be tested；
Input is connected with described microcontroller, outfan is connected with described Socket seat program-controlled electric source generating circuit, program control
Signal generating circuit and clock generation module；Input is connected with described Socket seat, outfan is connected with described microcontroller
The frequency divider connecing；Wherein, described program-controlled electric source generating circuit is used for providing adjustable supply voltage for described chip to be tested,
And measure power consumption；Described program control signal produces circuit and is used for producing amplitude needed for chip to be tested, frequency, phase place and partially
Put all adjustable test signal；Described clock generation module is used for generating desired clock signal and exports to described to be tested
Chip；Described frequency divider is used for the high-frequency signal output frequency division measurement to described chip to be tested；
Input is connected with one end of total analog switch, outfan is connected with described microcontroller the first analog-digital converter, ratio
Relatively/capture passage and GPIO module, the other end of described total analog switch is connected with described Socket seat；Wherein, described
One analog-digital converter is used for measuring the analog quantity of described chip to be tested；Described comparison/capture passage is used for by described total mould
Intend switching on-off the connection needing capture and the pin comparing and described microcontroller realizing described chip to be tested；Described
GPIO module is used for the GPIO function of described chip to be tested is tested；
Control end is connected with described microcontroller, first end is connected with load, the second end is connected with described Socket seat, is used for leading to
Cross the described microprocessor controls break-make of itself to realize whether controlling the linear stable in described chip to be tested with load
First relay；
Input is connected with the second end of described first relay, outfan is connected with described microcontroller, be used for measuring described
Linear stable is in the second analog-digital converter with carrying with the magnitude of voltage under zero load.
2. IC test device as claimed in claim 1 is it is characterised in that described program-controlled electric source generating circuit includes：
Input is connected with first voltage reference source as the input of described program-controlled electric source generating circuit, Voltage Reference end, defeated
Go out end to be connected with the input of high current amplifier, be used for the control signal according to described microcontroller and described first voltage
Reference source exports the first digital to analog converter of analog voltage；
Outfan is connected with the first end of sampling resistor and the input of the 3rd analog-digital converter, respectively for described simulation
Voltage is amplified obtaining the described high current amplifier of supply voltage；
Outfan is connected with described microcontroller, for being provided after described supply voltage acquisition process to described to be tested
Described 3rd analog-digital converter of the supply voltage of chip；
First end and the second end is connected with the input of instrument amplifier, the second end is also connected with the first end of the second relay
Described sampling resistor；
Outfan is connected with the input of the 4th analog-digital converter, the differential voltage for gathering on described sampling resistor, and will
Described differential voltage is amplified being amplified the described instrument amplifier of voltage；
Outfan is connected with described microcontroller, be used for gathering described amplification voltage after send and processed to described microcontroller
Described 4th analog-digital converter；
Control end is connected with described microcontroller, the second end is connected with described Socket seat, for by described microcontroller control
Make the break-make of itself to realize described second relay whether described program-controlled electric source generating circuit is described chip power supply to be tested
Device.
3. IC test device as claimed in claim 2 is it is characterised in that described program-controlled electric source generating circuit also includes：
Control end is connected with described microcontroller, first end is connected with the second end of described second relay, the second end and electric discharge
Circuit connects, for whether realizing described discharge circuit to described core to be tested by the described microprocessor controls break-make of itself
3rd relay of the quick power down of piece.
4. IC test device as claimed in claim 2 is it is characterised in that described program-controlled electric source generating circuit also includes：
First end is connected with the outfan of described high current amplifier, the second end is connected with the first end of described sampling resistor from
Recover electric fuse.
5. IC test device as claimed in claim 4 is it is characterised in that described program-controlled electric source generating circuit also includes：
First end is connected with the second end of described resettable fuse, the second end is connected with the input of described 3rd analog-digital converter
The first bleeder circuit connecing.
6. IC test device as claimed in claim 1 is it is characterised in that described program control signal generation circuit includes：
Input is connected with described microcontroller, outfan is connected with the first end of the second bleeder circuit, Voltage Reference end and the
Two voltage reference sources connect, for exporting simulation according to the control signal of described microcontroller and described second voltage reference source
Second digital to analog converter of signal；
Described second bleeder circuit that second end is connected with the first end of voltage follower；
The described voltage follower that second end is connected with the first input end of the first analog switch；
Second input is connected with simulation ground, outfan is connected with described Socket seat, control end is connected with described microcontroller,
For select according to the control signal of described microcontroller voltage follower output or simulation to described Socket seat
Described first analog switch.
7. IC test device as claimed in claim 1 is it is characterised in that this test device also includes：
Be connected with described microcontroller by optocoupler, for selecting the parallel interface that separator is connected with described microcontroller.
8. IC test device as claimed in claim 1 is it is characterised in that this test device also includes：
It is connected with described microcontroller, described chip testing to be tested started or stop for triggering described test device
Button.
9. IC test device as claimed in claim 1 is it is characterised in that this test device also includes：
It is connected with described microcontroller, start or terminate, in test, the warning dress that test is reported to the police for described test device
Put.
10. IC test device as claimed in claim 1 is it is characterised in that described total analog switch is opened for N level cascaded analogue
Close, N is integer.
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|---|---|---|---|
| CN201621046448.8U CN205982552U (en) | 2016-09-09 | 2016-09-09 | IC testing arrangement |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621046448.8U CN205982552U (en) | 2016-09-09 | 2016-09-09 | IC testing arrangement |
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| CN107656235A (en) * | 2017-10-31 | 2018-02-02 | 国网冀北电力有限公司电力科学研究院 | A kind of measurement apparatus and method of computation chip reference voltage |
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