CN205944069U - Novel chip structure - Google Patents

Novel chip structure Download PDF

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Publication number
CN205944069U
CN205944069U CN201620997668.2U CN201620997668U CN205944069U CN 205944069 U CN205944069 U CN 205944069U CN 201620997668 U CN201620997668 U CN 201620997668U CN 205944069 U CN205944069 U CN 205944069U
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CN
China
Prior art keywords
layer
chip
packed layer
electrode
metal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201620997668.2U
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Chinese (zh)
Inventor
沈琴
夏辉
吴迪
张辉
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Wuxi Aoli Core Electronic Technology Co Ltd
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Wuxi Aoli Core Electronic Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to CN201620997668.2U priority Critical patent/CN205944069U/en
Application granted granted Critical
Publication of CN205944069U publication Critical patent/CN205944069U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model discloses a novel chip structure, including insulating metal substrate, the upper surface of insulating metal substrate is equipped with the solder layer, the upper end welding of solder layer has printed circuit board, printed circuit board includes the base plate, be equipped with the chip on the base plate, the chip includes the P electrode, the lower extreme of P electrode is equipped with the silicon board, the lower extreme of silicon board is equipped with the weld metal layer, the lower extreme on weld metal layer is equipped with the ohmic contact layer, the lower extreme on ohmic contact layer is equipped with the electrode material filling layer, the lateral wall of electrode material filling layer is equipped with the passivation layer. The utility model discloses simple structure, design benefit, convenient to use adopts flip chip technology, outside having increased heat conducting effect, has also played simultaneously the effect of connecting and supporting to a certain extent to do not change the size of chip, in the chip efficiency of improving production, reduce production chip cost, have good radiating effect in, also guaranteed the stability of chip.

Description

A kind of novel chip structure
Technical field
The utility model is related to electronic component technology field, specially a kind of novel chip structure.
Background technology
Electronic consumer products outward appearance increasingly minimizes and frivolous, the PCB of the inside(Printed Circuit Board, Printed circuit board)Board area is less and less, and chip integration increases substantially, and adds outside the plastics adopting under cost pressure Shell, bring product attractive in appearance and high performance work under relative high temperature for a long time simultaneously, the stability of system receives chooses War, the radiating of product becomes problem demanding prompt solution.Existing product radiating mainly breaks up heat by product casing appropriate location Fin is installed in hole, high power consumption device surface or the mode of installation fan solves, and the solution of louvre belongs to wandering Heat, is only applicable to indoor type, and high power consumption device surface is installed fin and belonged to heat loss through conduction, can only effectively reduce local Temperature, and easily limited by structure, increase hardware cost simultaneously;The mode installing fan belongs to forced convertion radiating, can increase Plus product size, typically it is only applicable to indoor large frame or frame-type product, in the prior art, generally by reducing weldering Pad size to ensure a number of the single chip on wafer, however, reducing weld pad size can lead to weld pad and conducting wire The area being electrically connected with diminishes, and reduces the stability of chip, for the problems referred to above, a kind of novel chip structure of special proposition.
Utility model content
The purpose of this utility model is to provide a kind of logistics equipment automatic fault diagnosis to report to the police and long distance control system, with Solve the problems, such as to propose in above-mentioned background technology.
For achieving the above object, the utility model provides following technical scheme:A kind of novel chip structure, including insulation gold Belong to substrate, the upper surface of described insulating metal substrate is provided with solder layer, and the two ends of described solder layer are equipped with pad, described weldering The upper end of the bed of material is welded with printed circuit board (PCB), and described printed circuit board (PCB) includes substrate, and described substrate is provided with chip, described chip Including P electrode, the lower end of described P electrode is provided with silicon plate, and the lower end of described silicon plate is provided with weld metal layers, described weld metal layers Lower end be provided with ohmic contact layer, the lower end of described ohmic contact layer is provided with electrode material packed layer, described electrode material filling Layer is from top to bottom followed successively by P-GaN packed layer, MQW packed layer and N-GaN packed layer, the lower end peace of described electrode material packed layer Equipped with N electrode, the lateral wall of described electrode material packed layer is provided with passivation layer.
Preferably, side is provided with the first radiating groove and the second radiating respectively inwards the top surface of described insulating metal substrate and bottom surface Groove, and the first radiating groove and the interlaced arrangement of the second radiating groove.
Preferably, it is provided with encapsulating material packed layer at described insulating metal substrate and the lateral wall of solder layer junction.
Preferably, the top of described printed circuit board (PCB) is provided with limited impression, and the quantity of limited impression at least five.
Compared with prior art, the beneficial effects of the utility model are:A kind of novel chip structure, structure is simple, design Ingenious, easy to use, using flip chip technology, outside the effect increasing heat transfer, the also company of serving to a certain extent simultaneously The effect connecing and supporting, and do not change the size of chip, produce chip efficiency, reduce production chip cost, have improving While great heat radiation effect, also ensure that the stability of chip.
Brief description
Fig. 1 is the utility model structural representation;
Fig. 2 is the structural representation of the utility model chips.
In figure:1st, insulating metal substrate, the 11, first radiating groove, the 12, second radiating groove, 2, solder layer, 21, pad, 3, Printed circuit board (PCB), 31, limited impression, 4, substrate, 5, chip, 51, P electrode, 52, silicon plate, 53, weld metal layers, 54, ohm connects Contact layer, 55, electrode material packed layer, 551, P-GaN packed layer, 552, MQW packed layer, 553, N-GaN packed layer, 56, N electricity Pole, 57, passivation layer, 6, encapsulating material packed layer.
Specific embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out Clearly and completely description is it is clear that described embodiment is only a part of embodiment of the utility model rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of making creative work The every other embodiment being obtained, broadly falls into the scope of the utility model protection.
Refer to Fig. 1-2, the utility model provides a kind of technical scheme:A kind of novel chip structure, including insulated metal Substrate 1, the upper surface of described insulating metal substrate 1 is provided with solder layer 2, and the two ends of described solder layer 2 are equipped with pad 21, institute The upper end stating solder layer 2 is welded with printed circuit board (PCB) 3, and described printed circuit board (PCB) 3 includes substrate 4, and described substrate 4 is provided with chip 5, described chip 5 includes P electrode 51, and the lower end of described P electrode 51 is provided with silicon plate 52, and the lower end of described silicon plate 52 is provided with welding gold Belong to layer 53, the lower end of described weld metal layers 53 is provided with ohmic contact layer 54, and the lower end of described ohmic contact layer 54 is provided with electrode Material packed layer 55, described electrode material packed layer 55 is from top to bottom followed successively by P-GaN packed layer 551, MQW packed layer 552 and N-GaN packed layer 553, the lower end of described electrode material packed layer 55 is provided with N electrode 56, described electrode material packed layer 55 Lateral wall is provided with passivation layer 57, and structure is simple, and design is ingenious, easy to use, using flip chip technology, is increasing the work of heat transfer With outer, also serve the effect connecting and supporting to a certain extent simultaneously, and do not change the size of chip, produce improving While chip efficiency, reduction produce chip cost, have great heat radiation effect, also ensure that the stability of chip.
Specifically, side is provided with the first radiating groove 11 and respectively inwards the top surface of described insulating metal substrate 1 and bottom surface Two radiating grooves 12, and the first radiating groove 11 and the interlaced arrangement of the second radiating groove 12, can make insulating metal substrate 1 have more Good radiating effect.
Specifically, it is provided with encapsulating material packed layer at described insulating metal substrate 1 and the lateral wall of solder layer 2 junction 6, insulating metal substrate 1 and solder layer 2 can be made to have better seal, and can prevent from leaking electricity.
Specifically, the top of described printed circuit board (PCB) 3 is provided with limited impression 31, and the quantity of limited impression 31 is at least Five, auxiliary stopper can be carried out to this novel chip structure.
Operation principle:When using, respectively P electrode 51 and N electrode 56 are linked in operating circuit, in work process This novel chip structure can produce heat, makes chip 5 can more pass through solder layer 2 and insulated metal base by flip chip technology Plate 1 contacts, and heat can preferably pass to insulating metal substrate 1, after heat transfer is to insulating metal substrate 1, leads to Cross the first radiating groove 11 being provided with and the second radiating groove 12 can radiate to insulating metal substrate 1.
While there has been shown and described that embodiment of the present utility model, for the ordinary skill in the art, It is appreciated that these embodiments can be carried out with multiple changes in the case of without departing from principle of the present utility model and spirit, repair Change, replace and modification, scope of the present utility model is defined by the appended claims and the equivalents thereof.

Claims (4)

1. a kind of novel chip structure, including insulating metal substrate(1)It is characterised in that:Described insulating metal substrate(1)Upper Surface is provided with solder layer(2), described solder layer(2)Two ends be equipped with pad(21), described solder layer(2)Upper end welding There is printed circuit board (PCB)(3), described printed circuit board (PCB)(3)Including substrate(4), described substrate(4)It is provided with chip(5), described core Piece(5)Including P electrode(51), described P electrode(51)Lower end be provided with silicon plate(52), described silicon plate(52)Lower end be provided with welding Metal level(53), described weld metal layers(53)Lower end be provided with ohmic contact layer(54), described ohmic contact layer(54)Under End is provided with electrode material packed layer(55), described electrode material packed layer(55)From top to bottom it is followed successively by P-GaN packed layer (551), MQW packed layer(552)With N-GaN packed layer(553), described electrode material packed layer(55)Lower end be provided with N electricity Pole(56), described electrode material packed layer(55)Lateral wall be provided with passivation layer(57).
2. a kind of novel chip structure according to claim 1 it is characterised in that:Described insulating metal substrate(1)Top Side is provided with the first radiating groove respectively inwards for face and bottom surface(11)With the second radiating groove(12), and the first radiating groove(11)Dissipate with second Heat channel(12)Interlaced arrangement.
3. a kind of novel chip structure according to claim 1 it is characterised in that:Described insulating metal substrate(1)With weldering The bed of material(2)It is provided with encapsulating material packed layer at the lateral wall of junction(6).
4. a kind of novel chip structure according to claim 1 it is characterised in that:Described printed circuit board (PCB)(3)Top It is provided with limited impression(31), and limited impression(31)Quantity at least five.
CN201620997668.2U 2016-08-29 2016-08-29 Novel chip structure Expired - Fee Related CN205944069U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201620997668.2U CN205944069U (en) 2016-08-29 2016-08-29 Novel chip structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201620997668.2U CN205944069U (en) 2016-08-29 2016-08-29 Novel chip structure

Publications (1)

Publication Number Publication Date
CN205944069U true CN205944069U (en) 2017-02-08

Family

ID=57955348

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201620997668.2U Expired - Fee Related CN205944069U (en) 2016-08-29 2016-08-29 Novel chip structure

Country Status (1)

Country Link
CN (1) CN205944069U (en)

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170208

Termination date: 20170829

CF01 Termination of patent right due to non-payment of annual fee